RE: [IBIS-Users] Warning message for MISMATCH

Hello, YY Lau,
 
This is a modeling issue.  The tolerance allowed on V-t table endpoints is a
modeling decision.  Large mismatches can lead to simulation problems (hence
parser mismatch error/warning messages). If the mismatch is between 2% and
10%, the parser issues a warning.
 
Common causes are too few points in the I-V tables, or not waiting until the
V-t transition is fully complete (in which case, V-t data might look OK, but
with enough slope to cause this warning).
 
The transistor strength requirement is not evaluated by IBIS.  That is a
design/application requirement.
 
Best regards,
Lynne
 
 
"IBIS training when you need it, where you need it."
 
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com
 
 


  _____  

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of lau yy
Sent: Thursday, April 06, 2006 3:23 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Warning message for MISMATCH


Hi ALL,
 
Below I attach a model for an IO pin. The model pass with warning. I show 1
of the warning message as below:
 
WARNING - Model IO: The [Falling Waveform] 
      with [R_fixture]=50 Ohms and [V_fixture_max]=3.6V
      has MAX column DC endpoints of  1.98V and  3.53v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.94V and  3.39V),
      a difference of  2.36% and  3.96%, respectively.

I study the rising and falling datas, can see that the pin is already stable
but is just the voltage level can fall to 0 or reach VCC. Is this a design
issue or modeling issue? I belive that is the pullup and pulldown transistor
not strong enough. Am I right?
 
PLease comment.
 
Thanks
 
rdgs
yylau




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