[IBIS-Users] different duty-cycle for same [Diff Pin] asignment

From: <Naftali.Refaeli_at_.....>
Date: Sun Apr 09 2006 - 05:35:29 PDT
Hello Scott.

Can you find why there is a "different duty-cycle" between two output pins
of the SAME model used in [Diff Pin] keyword?
Can you help?

Details:
1) I used the same model for Diff pair Driver.
2) On simulation I see difference between Pos  Output and Neg Output (See
attached file).

[Pin] signal_name  model_name  R_pin  L_pin C_pin
|
1 Q0 819366_OUT1
2 _Q0 819366_OUT1
.
 .
  ...
[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
|
1 2 NA NA NA NA
...

(See attached file: Asymetric_WaveForms.pdf)
*****************************************
Naftali Refaeli
EDS CAD Division
Petah-Tikva 49133  Israel
Tl.     +972-3-9266973       Fax:   +972-3-9268188
*****************************************


                                                                           
             Scott McMorrow                                                
             <scott@teraspeed.                                             
             com>                                                       To 
             Sent by:                  tom@teraspeed.com                   
             owner-ibis@eda.or                                          cc 
             g                         "Lynne D. Green"                    
                                       <lgreen22@mindspring.com>,          
                                       seshadri.kirankumar@wipro.com,      
             06/04/2006 20:47          ibis@eda.org, ibis-users@eda.org    
                                                                   Subject 
                                       [IBIS] Re: [IBIS-Users] How to      
                                       include Differential and Normal     
                                       IO's of same pins                   
                                                                           
                                                                           
                                                                           
                                                                           
                                                                           
                                                                           




All

the best solution is to produce two different models.  One with
differential buffers and one with single ended.  The same problem occurs
in parts that interface to multiple types of busses, like SPI4, TCAM,
RLDRAM ... etc    The easiest way to design models to handle these
programmable features is to create separate models for each.  Otherwise
you end up with customer issues.  For each option, you provide a
separate component model.

scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Tom Dagostino wrote:
> Lynne
>
> I think you are missing the point.  The two pins used for a differential
> pair in one case are able to be driven by single ended buffers in a
> non-differential mode at other times.  The best solution to this that I
can
> think of is to use a model selector to toggle between the differential
> buffer and the SE buffer.  But when in the SE mode, comment out the [Diff
> pin] section for those 2 pins.
>
> Tom Dagostino
> Teraspeed(R) Labs
> 13610 SW Harness Lane
> Beaverton, OR 97008
> 503-430-1065
> tom@teraspeed.com
> www.teraspeed.com
>
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> 401-284-1827
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
> Behalf Of Lynne D. Green
> Sent: Thursday, April 06, 2006 10:01 AM
> To: seshadri.kirankumar@wipro.com; ibis@eda.org; ibis-users@eda.org
> Subject: RE: [IBIS-Users] How to include Differential and Normal IO's of
> same pins
>
>
> Hello, Kiran Kumar,
>
> Here is an example using the same IBIS buffer for both differential and
> non-differential buffers. If the buffer is fully symmetric (same edge
rate,
> edge delay, etc.), then one can (should) use the same model for both
sides
> of the diff I/O.  This also removes the need to set two model selectors
for
> one diff pair.
>
> Also, since tdelay_typ defaults to 0nsec, I would recommend setting it
> explicitly to that value.
>
> [Pin]     signal_name      model_name              R_pin        L_pin
> C_pin
> |
> Pin1         CLKP             io1
> Pin2         CLKN            io1
> Pin3         Single              io1
> |
> [Diff_pin]       inv_pin         vdiff       tdelay_typ     tdelay_min
> tdelay_max
> |
> Pin1             Pin2            200mV      0.0n              NA
> NA
> |
>
> Best regards,
> Lynne
>
>
> "IBIS training when you need it, where you need it."
>
> Dr. Lynne Green
> Green Streak Programs
> http://www.greenstreakprograms.com
> 425-788-0412
> lgreen22@mindspring.com
>
>
>
>
> ________________________________
>
>            From: owner-ibis-users@eda.org
[mailto:owner-ibis-users@eda.org] On
> Behalf Of seshadri.kirankumar@wipro.com
>            Sent: Thursday, April 06, 2006 6:10 AM
>            To: ibis@eda.org; ibis-users@eda.org
>            Subject: [IBIS-Users] How to include Differential and Normal
IO's of
> same pins
>
>
>
>            Hi Experts,
>
>
>
>                      I have a doubt regarding IBIS model of incorporating
> Differential and Non-differential Buffers in the same IBIS file
>
>
>
>            As an Example there are 2 pins and corresponding LVDS
definition is
> as follows
>
>            [Pin]     signal_name      model_name              R_pin
> L_pin         C_pin
>
>            |
>
>            Pin1         CLKP             LVDS_1
>
>            Pin2         CLKN             LVDS_2
>
>            |
>
>            [Diff_pin]       inv_pin         vdiff       tdelay_typ
> tdelay_min     tdelay_max
>
>            |
>
>            Pin1             Pin2            200mV      NA              NA
> NA
>
>
>
>            For  the same 2 above pins there exist normal(Non
differential) IO's
> too,  my doubt is that will it be possible to include both Differential
and
> Normal IO's with any IBIS mechanism like how a {Model Selector] chooses
> different models for the same pin? If so please let me know on how?
>
>
>
>                Suppose same if I do using [Model Selector] then what will
be
> the impact of [Diff_pin] section on this pins when I am using only Normal
> models, this prototype is as listed below
>
>            [Pin]     signal_name      model_name              R_pin
> L_pin         C_pin
>
>            |
>
>            Pin1         CLKP             MODEL_1
>
>            Pin2         CLKN             MODEL_2
>
>            |
>
>            [Diff_pin]       inv_pin         vdiff       tdelay_typ
> tdelay_min     tdelay_max
>
>            |
>
>            Pin1             Pin2            200mV      NA              NA
> NA
>
>            |
>
>            [Model Selector]     MODEL_1
>
>            LVDS_1                     lvds model
>
>            BUFFER_1                 normal output buffer
>
>            |
>
>            [Model Selector]     MODEL_2
>
>            LVDS_2                     lvds model
>
>            BUFFER_2                 normal output buffer
>
>            |
>
>            What my opinion is option 2 is not proper as there is still
> valid(uncommented) [Diff_pin]  section exist for the same pins while
using
> normal IO's mode, please correct me if my concept is wrong
>
>
>
>            Any Help on this is appreciable
>
>
>
>            Thanks & Best Regards
>
>            Kiran Kumar
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
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Received on Sun Apr 9 05:39:17 2006

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