[IBIS-Users] Re: [IBIS] Open drain strange behaviour

Hello Michael

  thanks for your feedback.
  In my Open drain Ibis model there is no extra delay portion,
  because I have inserted as falling and rising waveform tables
  the result of transistor level simulation, that I am considering
  for comparison.
  I obtain this delay both Eldo and Hspice simulation.

  Best regards

             Roberto

Michael Schaeder wrote:

>Hello Roberto,
>
>I guess there is an extra delay portion in the
>[Rising/Falling Waveform]s of your IBIS model.
>
>Regards, Mic.
>
>Monday, September 11, 2006, 2:17:18 PM, you wrote:
>
>  
>
>>Hello everybody
>>
>>  I 'd like to have some information about a strange behaviour of Open
>>drain buffer
>>  Ibis model. I have noticed a mismatch between Transistor level and 
>>Ibis model
>>  voltage output during a transient analysis. In fact in presence of the
>>same input voltage
>>  wave and the same value of load resistance (for example 70 ohm),
>>  we can observe a delay between TL output and Ibis output. This delay
>>is the same
>>  if we change the value of  load resistance. What is the cause of this
>>strange behaviour?
>>
>>  Thanks and best regards
>>
>>        Roberto Izzi
>>    
>>
>--
>Dipl. Ing. Michael Schaeder                   Tel: +49 5251-150-670
>Zuken - EMC Technology Center                 Fax: +49 5251-150-700
>Vattmannstrasse 3             E-mail: Michael.Schaeder@pad.zuken.de
>D-33100 Paderborn                                Web: www.zuken.com
>Germany              PGP Key: http://mail.pad.zuken.de/~mic/msc.asc
>
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