Hi ibis experts, In my Level traslator , I have VCC1 in the input side (where there is "in" Pin) and VCC2 in the output side (where there is "out" Pin) . With VCC1=1.8V and VCC2=2.9V. In which way I can explain this condition? is this correct? [Pin] signal_name model_name R_pin L_pin C_pin | in in mod_in out out mod_out VSS VSS GND VCC1 VCC1 POWER VCC2 VCC2 POWER Or I must use Pin Mapping ? thank you for any possible response. Regards, Fabio -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Fri Oct 20 01:05:30 2006
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