RE: [IBIS-Users] IBIS load

From: NG,MEI-YEE <mei-yee.ng_at_.....>
Date: Mon Dec 04 2006 - 20:08:04 PST
OK, but according to the cookbook, we need to append 1R+1F waveforms for
suggested pullup resistor, which in my case is 1.5K Ohm. Is it ok if I
just put 1.5K ohm as Rref instead?

 

Best regards,

Mei Yee

SID, Avago Technologies (Malaysia)

Tel no.:604-6108515

________________________________

From: Tom Dagostino [mailto:tom@teraspeed.com] 
Sent: Tuesday, December 05, 2006 11:38 AM
To: NG,MEI-YEE; ibis-users@server.eda.org; ibis-users@server.eda.org
Subject: RE: [IBIS-Users] IBIS load

 

I would say do the extraction with the 50 Ohm load and put the datasheet
timing load into the model in the Rref, Cref, Vref section.

 

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 

	-----Original Message-----
	From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of NG,MEI-YEE
	Sent: Monday, December 04, 2006 5:28 PM
	To: ibis-users@server.eda.org; ibis-users@server.eda.org
	Subject: [IBIS-Users] IBIS load

	Hi experts,

	 

	According to the cookbook, when extracting V-T data, it is
recommended to use a load circuit of 1R + 1F into manufacturer's
suggested pullup resistor termination and voltage. However, when I use
the suggested pullup resistor (1.5K), the rising waveform takes up to
100ns to stabilize, but the falling waveform requires less than 10ns.
This creates inaccuracy due to the resolution of the points (when I use
100ns simulation time). In the IBIS model, I also included a waveform
for 50Ohm pullup resistor (as recommended by cookbook). The rising
waveform for this is also within 10ns. I wonder if I can generate IBIS
model with ONLY 50 Ohm pullup because the resolution is more appropriate
in this case? I have verified this model and the simulation shows
acceptable waveforms.

	 

	Kindly advice whether it is a MUST to have a 1.5K pullup
resistor V-T table.

	 

	Thank you.

	 

	Best regards,

	 

	Mei Yee Ng

	IC Design Engineer 

	Illumination and Color Management

	Solid-state Illumination Division

	Avago Technologies Malaysia

	Tel no: +604-6108515

	 


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Received on Mon Dec 4 20:08:13 2006

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