RE: [IBIS-Users] Ibis open drain strange behaviour

Hi everybody, 

I would like to say that I experienced the same phenomenon as Roberto,
with the IBIS waveform delayed compared to the transistor level
simulation. Aubrey, what do you mean by IBIS model doesn't contain
buffer delay? How does that explain IBIS model being delayed in the
output response?

Appreciate any feedback. Thank you.

Best regards,
Mei Yee

-----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of
Aubrey_Sparkman@dell.com
Sent: Friday, January 12, 2007 12:15 AM
To: roberto.izzi@st.com; ibis@server.eda-stds.org;
ibis-users@server.eda.org
Subject: RE: [IBIS-Users] Ibis open drain strange behaviour

Is your only concern the time delay? IBIS and Spice aren't always
aligned in time since IBIS doesn't contain the buffer delay.


Aubrey Sparkman 
Enterprise Engineering Signal Integrity Team
Dell, Inc. 
Aubrey_Sparkman@Dell.com 
(512) 723-3592

The Greatest Pleasure in Life is Doing what People say can't be done...

-----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI
Sent: Thursday, January 11, 2007 10:08 AM
To: ibis@server.eda-stds.org; ibis-users@server.eda.org
Subject: [IBIS-Users] Ibis open drain strange behaviour

Hello everybody

I 'd like to have some information about a strange behaviour of Open
drain buffer Ibis model.
I have noticed a mismatch between Transistor level and Ibis model
voltage output during a transient analysis, considering the same buffer.
In fact in presence of the same input voltage wave and for a high value
of load resistance(for example 20Kohm)connected to power, we can observe
a delay between TL output and Ibis output. 
In the Ibis file, for Open drain, Rise and fall waves tables have been
extracted considering the same resistance connected to Power (20Kohm).
What is the cause of this strange behaviour?

  Thanks and best regards

        Roberto Izzi
    


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