Do not use the 400 pF as a load during VT table extraction. In an actual circuit implementation the load seen by the driver is a combination of transmission lines and lumped loads. in 99.999% of the cases the first thing the driver is going to see is a segment of transmission line. It will never see a 400 pF lumped load. The capacitive loads will be distributed linked together by segments of transmission lines. Let the SI simulator take care of the topology of the loads. If you slow the driver by placing heavy loads on it during VT extractions the SI simulator will have to compute the unloaded VT curves which, from my experience, does not work well. The model's job is to describe the buffer's characteristics. The SI simulator's job is to show how the driver interacts with the board's environment. Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, February 07, 2007 6:38 AM To: Lynne D. Green; ibis-users@server.eda.org Subject: [IBIS-Users] Rref and R_fixture clarifications Hi Lynne and all, Actually I am taking one of my previous question and I am asking this question also. Sometime back lynne has mentioned that, Rref and Cref are for timing checks and R_fixture corresponds to loading conditions. And he also mentions that one should not use reactive loads to measure V-t tables as it breaks some of the tool's algorithms. Now i have a specific case. For IIC we need to connect a load of 400 pF. Its a very slow cell. Its a IIC system requirement. In the specification they say, in a system there will be around 40 recievers connected to 1 driver through IIC bus. If you convert the distributed loading of these 40 Rcx to 1 lumped loading it comes around 400 pF. So do i need to connect a C_fixture of 400 pF load while generating V-t tables ? If not where this load should be specified and what load has to be used for generating V-t tables? Let me know your response. Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. Ph:+91-80-40267073 Fax: +91-80-4026 7855 seri:sudarsha@inpsblr E-mail: sudarshan.honnudike@nxp.com "Lynne D. Green" <lgreen22@mindspring.com> 2007-01-10 04:33 PM To "'Alex Hilbers'" <alex.hilbers@asml.com> "'Sudarshan Honnudike'" <sudarshan.honnudike@nxp.com> <ibis-users@eda.org> cc Subject RE: [IBIS-Users] Information on Vref, Rref & Cref Classification I was somewhat confused about the loading question and reply. Rref and Cref are for timing checks, not for simulation. The loading for V-t tables is R_fixture. So both are needed in a model. One should not use reactive loading in a V-t table. This has been observed to "break" the algorithm as implemented by some SI tools. The underlying algorithms have been published in two papers: * The Development of Analog SPICE Behavioral Model Based on IBIS Model Ying Wang & Han Ngee Tan * Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS P. Tehrani, Y. Chen & J. Fang - Lynne "IBIS training when you need it, where you need it." Dr. Lynne Green Green Streak Programs http://www.greenstreakprograms.com 425-788-0412 lgreen22@mindspring.com ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Alex Hilbers Sent: Wednesday, January 10, 2007 1:47 AM To: Sudarshan Honnudike; ibis-users@eda.org Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref Sudarshan, Interesting question. I always wondered how a table based model (V-I, ..), such as an IBIS model, could model any form of feedback control system, as the IO pad you describe probably is. It seems that V-t waveforms, together with a simulation tool specific algorithm, must do that job. You verify this by comparing your simulation tool with actual SPICE results. This is prone to variation based on which tool you use, I donot think this 'algorithm' is standardised. To my knowledge XTK needs the curves rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t tables are ignored. (Some vendors do provide only 1 or 2, which is useless). Interesting is what happens if you define several load conditions (Rfixture = 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What will the simualtion tool choose, will it interpolate, I donot have the faintest idea. I guess it won't work within IBIS, which may be the reason you do not get answers. Maybe a good reason to provide SPICE models for this type of buffer. Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9, should be fine. Best regards, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Alex Hilbers Signal Integrity Analysis and Thermal Management, ASML, EDEV department Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530 Email: alex.hilbers@asml.com, www.asml.com <http://www.asml.com/> ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Sudarshan Honnudike Sent: Wednesday, January 10, 2007 6:35 AM To: ibis-users@eda.org Subject: [IBIS-Users] Information on Vref, Rref & Cref Hi , If we have a IO pad which works in the different applications depending on the load applied on it, then do we to provide V-t waveforms(more than normal 4 curves) for different applications with different load settings.? Or can we specify that loading conditions under Rref, Vref and Cref for that model. Which one is preferable. ? I tested my model with Hyperlynx SI tool and it is not identifying the Rref and Vref values that I am specifying in my model. It will only take Cref and Vmeas while doing simulations. In that case we can't specify the loading conditions under Vref, Cref and Vref but we need to give all possible V-t curve combinations for different loading conditions. Please let me know your reply. PS : I am also waiting for the reply to my previous mail regarding Common Mode Voltage Range support in IBIS . Best Regards, Sudarshan HN NXP Semiconductors/CTO /PLT C-4, Manyata Tech Park, Nagawara Bangalore-560 045 , India. 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