[IBIS-Users] RE: Tolerant IO cell's Supply voltage range.?

Sudarshan,
 
The idea is to cover doubled-voltage reflections from unterminated
lines.  For example, PCI bus receivers do not terminate but the bus
instead functions using reflected-wave switching.  As a result, an
old-style 5 V PCI device, if used in a system with little line loss,
could drive a 5 V signal and see it reflected back to itself at 10 V off
the unterminated end of the line.  If you look at the original 5 V PCI
specification, the buffer overshoot section allows for something
approaching 11 V, if memory serves.  Lower speeds of USB have similar
tolerance rules.
 
You are correct that more modern drivers, particularly in low-voltage,
low-swing serdes terminated environments, are less likely to encounter
such harsh conditions.
 
- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

________________________________

From: Sudarshan Honnudike [mailto:sudarshan.honnudike@nxp.com] 
Sent: Friday, February 16, 2007 00:16
To: Mirmak, Michael
Cc: ibis-users@server.eda.org
Subject: RE: Tolerant IO cell's Supply voltage range.?



Thanks Michael for the clarifications. 

But still i want to know what is the point in providing such big ranges
of voltage if the cell doesn't work at that voltages. ? 
Because for a 5V tolerant cell, maximum it can tolerate 5V. So what is
the intention of providing the voltage range from -5V to +10V. 
Definitely at such high voltages the cell will breakdown. 

Is there any use of providing such tables in application ? 

The reason for choosing -Vdd and +2Vdd is to take care of short and open
circuit conditions. But under those conditions , cell will anyway 
will not work. So what the whole idea behind it ? 

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com 








"Mirmak, Michael" <michael.mirmak@intel.com> 

2007-02-14 11:27 PM 

To
"Sudarshan Honnudike" <sudarshan.honnudike@nxp.com>
<ibis-users@server.eda.org> 
cc
Subject
RE: Tolerant IO cell's Supply voltage range.? 
Classification

	




Sudarshan, 
  
You are indeed correct.  For 5 V tolerant buffers, the clamp tables
would cover a range based on a 5 V supply, to withstand any incoming
high-voltage signals.  The [Pullup] and/or [Pulldown] tables would cover
a range based on the 3.3 V supply.   
  
- Michael Mirmak 
  Intel Corp. 
  Chair, EIA BIS Open Forum 


________________________________

From: Sudarshan Honnudike [mailto:sudarshan.honnudike@nxp.com] 
Sent: Monday, February 12, 2007 21:56
To: ibis-users@server.eda.org; owner-ibis-users@server.eda.org
Subject: Tolerant IO cell's Supply voltage range.?


Hello All, 

I want to know what should be the voltage range for the tolerant cells
for I-V curves like [Gnd Clamp], [Power Clamp], [Pull up] & [Pull down].

I read it from one of the presentation that, say for a 3.3 V functional
5 V tolerant cell the voltage range is from -5V to +10V.  Do what curves
this range applies ?. I dont think this range has to be applied for
[Pull u] and [Pull down] curves as these are basically driver
characteristics 
and maximum they can operate under 3.3V. So is it only for Clamp curves
? 

Please let me know your answers. 

Best Regards,

Sudarshan HN
NXP Semiconductors/CTO /PLT
C-4, Manyata Tech Park, Nagawara
Bangalore-560 045 , India.    
Ph:+91-80-40267073  
Fax: +91-80-4026 7855
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@nxp.com
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