Hi April, if it will help you I was discussing on this topic some 6 months ago (please find in the attachment mail with subject: " IBIS-Users Variety of Aproaches on IBIS Modeling on Differential I O Buffers (with and without Pre- De-Emphasis).msg") - but shortly, there are many approaches, you have to find your own or if you like message is that there is no straight-forward solution. Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <mailto:radovan.vuletic@qimonda.com> ============================================================================== Qimonda AG Chairman of the Supervisory Board/ Aufsichtsratsvorsitzender: Peter J. Fischl Management Board/ Vorstand: Kin Wah Loh (Chairman/ Vorsitzender), Dr. Michael Majerus, Thomas J. Seifert Register Court/ Registergericht: München HRB 152545, Seat/ Sitz: München ============================================================================== ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of April.Hachenburg@smsc.com Sent: Monday, August 27, 2007 5:13 PM To: Mirmak, Michael Cc: Chitiz Mathema; ibis-users@server.eda.org; owner-ibis-users@server.eda.org Subject: RE: [IBIS-Users] IBIS question on C_comp Michael, Your response is helpful. I too am doing my first differential buffer so on a slightly different note .... Does the s2ibis3 script handle generation of differential buffers? If not, is there a similar script available? - April --------------------------------------------------- April Hachenburg Core Technology Design Engineer SMSC - Phoenix "Mirmak, Michael" <michael.mirmak@intel.com> Sent by: owner-ibis-users@server.eda.org 08/24/2007 05:10 PM To "Chitiz Mathema" <cit@cypress.com>, <ibis-users@server.eda.org> cc Subject RE: [IBIS-Users] IBIS question on C_comp Chitiz, Thanks for your questions on IBIS. Here are some hopefully useful answers... 1,2) The purpose of C_comp is to describe the capacitance of the buffer at the pad, as it appears "looking in." You are correct that the V-t tables and ramp information already take C_comp into account, for drivers. However, C_comp is still needed in order to describe the capacitive load the buffer presents to waveforms (reflections) coming back into the driver. In general, tools ensure that C_comp as a discrete number and its effects in the table and ramp data are not double-counted. This may be implemented by simply "backing out" or derating the V-t tables for the effects of C_comp, then adding an actual capacitor to the driver circuit in simulation. In that way, the derated-table-plus-capacitor waveforms will match the original IBIS driver data, but the system will "see" the capacitance of the buffer as a load. Specific tools may have different ways to approach the problem. 3) C_comp should exclude the effects of the package, but include all the buffer's on-die parasitic capacitances -- pad, die routing, etc. 4) Information on extraction methods for C_comp, as well as differential treatments, can be found in the IBIS Cookbook: http://www.eda.org/ibis/cookbook/cookbook-v4.pdf In addition, several presentations on C_comp issues are available in the IBIS Summit archive: http://www.eda.org/ibis/summits/index-bytitle.htm To address your concern, I would not say that IBIS per se is not properly addressing high-frequency effects. However, C_comp in traditional table-driven IBIS is a single value. Capacitance for a buffer is frequency- and voltage-dependent. Therefore, the method of extraction and the frequency at which the extracted value applies are critical when correlating the resulting IBIS model. In the case you describe, I would check to make sure that the C_comp value was not extracted at a frequency below 400 MHz. A more comprehensive treatment of buffer capacitance is possible using advanced IBIS techniques, including multi-lingual methods (IBIS 4.1, 4.2). I hope this helps! - Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum -----Original Message----- From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Chitiz Mathema Sent: Friday, August 24, 2007 4:31 PM To: ibis-users@server.eda.org Subject: [IBIS-Users] IBIS question on C_comp Hello, I have some questions about C_Comp parameter in IBIS models. I am trying to resolve some issues for IBIS models of high frequency differential output buffers. I am trying to compare my SPICE model transient simulations with the IBIS model I generated for a differential output buffer. At low frequencies (eg ~ 100MHz), the SPICE and IBIS model output simulation waveforms correlate closely. But at higher frequencies (>400MHz), the SPICE and IBIS model simulations don't match as well. I am trying to see if the mismatch is due to the C_comp parameter, or if this is just a limitation of IBIS models not being able to capture high frequency effects. 1. How IBIS simulators use the C_comp parameter during simulations? 2. Don't the V-T tables and ramp information already take into account the effect of C_comp? 3. What does the C_comp parameter exactly represent? -should it include die routes, pad capacitance, etc? 4. How should it be measured? 5. Should C_comp be measured in a special manner for differential buffers like LVDS buffers? I would appreciate your response. Thank you, -Chitiz Mathema Cypress Semiconductor -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993 -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
attached mail follows:
Hi experts, for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers. I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me. Disclaimer: I am perfectly aware that there is a possibility that I have, perhaps, wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities. Main question: I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - what is the setup that are most customers looking for? I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two. In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis. Differential Buffers w/o Pre/De-emphasis 1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement Method described (for example) by: - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf Advantages: - simple setup and usage Disadvantages: - not describing the coupling effects between pads - causes DC shifts in the signal level 2. Method described by - A. Tambone (Semiconductor Business News 2000) - no link found - http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z - http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf - http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf Advantages: - relatively "smooth" and easy flow for understanding of IBIS extraction; - relatively easy to adapt existing s2ibis2 or s2ibis3 flow; Disadvantages: - LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results; - LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies; - Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched; 3. Improved IBIS modeling approach (using only v3.2 keywords) Method described by: - http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf - http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf - http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf Advantages: - describes DC currents of a differential buffer completely and accurately - DC levels of the signals are correct under all loading conditions Disadvantages: - pretty complicated procedure for extraction of model (at least for me) - relatively big effort needed to automate the procedure - need to make some guesses for picking up the 'best" value for C_comp Questions: Q1: on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf -is written: "The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." On what is exactly meant by "The only added complexity in this procedure for differential drivers is that the subtraction is done after the common mode I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables? Q2: is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file? Q3: are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model? (Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf) Differential Buffers w/ Pre/De-emphasis 1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up treats differential buffers as four independent [Model]s (2 Main, 2 boosts) driven by a stimulus and its complement Disadvantage: - This approach was used initially for many models but required manual editing of files and/or simulation schematics 2. [Driver Shedule] Method for Pre-emphasis Buffer modeling http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule]) http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf Advantage (of V-I Through Transient simulation method): - relatively simple method Disadvantage (of V-I Through Transient simulation method): - Non-monotonic wave forms (For some EDA tools) - Single clock frequency operation (Changing the frequency needs remodeling) Advantage (of [Driver Schedule] Method): - Changing the frequency doesn't need remodeling - Eliminates the need for connecting two separate [Model]s by hand in the - Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer - Fewer transistor level (SPICE) models will need to be released to customers - Uses no more than IBIS v3.2 syntax - Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions - Reasonably good correlation with transistor level model Disadvantage (of [Driver Schedule] Method): - Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and simulation corner - The [Driver Schedule] delay parameters do not have typ., min., max. corners Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist - There are a few questions around proper handling of C_comp 3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit]) Advantage: - flexibility (I guess so) Disadvantage: - not all EDA tools support all features - relatively complicated setup Question: Q4: - can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis? 4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis as well) Method described by (and many others): http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf Advantage: - according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation - very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface) Disadvantage: - "where" is IBIS here? (not really a disadvantage, but more like a question) - need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A) - relatively high effort to create a proper setup and flow - one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - (at least in this case that wasn't my problem :-))) Questions: Q5: is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? In sum I spent around half 0of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. Btw., please find in the attachment slightly changed Perl script (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe- - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion_tool.zip can't be since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file. Q6: practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future? Q7: is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? Many thanks to those that have read this mail until here, I am hoping on some your feedback! Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ Qimonda AG QAG PD PDE MEM MUC/10.2.236 AP 3 Am Campeon 1-12 D-85579 Neuebiberg Phone: +49 (0)89 60088 1233 Fax (PC): +49 (0)89 60088 45 5305 E-mail: radovan.vuletic@qimonda.com <<ibis2ams.pl>> -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993
This archive was generated by hypermail 2.1.8 : Mon Aug 27 2007 - 23:15:21 PDT