[IBIS-Users] Reminder: CIE-SF 2007 Annual Short Course, EPMC-04, Latest Development in High Performance Lead-Frame Packaging and Applications, this coming Saturday afternoon at SJSU Engineering Building Room 339

Hi All,

This is a reminder that CIE-SF 2007 Annual Short Course, EPMC-04, Latest
Development in High Performance Lead-Frame Packaging and Applications, will
be held on this coming Saturday (10/13) afternoon 1:30 pm at San Jose State
University, Engineering Building, room 339.

Lead frame packaging technology

Putting extraordinary technology in ever smaller packages, this simple and
typically low cost packaging is still the best solution for many consumer
applications.  The Quad flat no-lead (QFN) package is a surface mount
plastic package with lead pads located on the bottom surface of the package.
With the QFN (Quad Flat No-lead) packaging technology entering into mass
production several years ago, the packaging industry experienced a
significant paradigm shift in the low-pin-count to medium-pin-count IC
packaging arena.  The same success story of performance enhancement and cost
reduction through miniaturization repeated itself for another time.  Not
only did QFN packages revolutionized lead frame-based packaging technology,
but also it entered into IC packaging areas that are traditionally
considered less competitive for lead frame packaging against laminate
packaging.

Since then, small form factor and high density lead frame packaging became a
very active research and development area.  Several new approaches and
technologies were developed to improve over QFN packages in terms of size,
density and cost. This talk attempts to provide an overview of the current
high-density lead frame packaging technologies and directions the industry
that is moving to.

This EPMC04 short course will be presented by Dr. Weiping (Bill) Li, who is
currently GM of North America Operations, Jiangsu Changjiang Electronics
Technology (JCET), a leading packaging company in China.  Prior to his
current work, he was a Senior Product Manager with Amkor Technology,
Principal Staff Engineer with Motorola Semiconductor Product Sector and
Product Engineer with Delphi Delco Electronics Systems.  He has been working
in the areas of System-in-Package (SiP), flip-chip BGA packaging, embedded
passives and HDI.  Dr. Li is a US patent holder with multiple corporate
invention disclosures.  He has published dozens of technical papers in the
areas of high-density interconnection, flip chip, embedded passives and
packaging materials, process and reliability.  Dr. Li obtained his Ph.D
degree from Georgia Institute of Technology in Materials Science and
Engineering and MS and BS degrees from Shanghai Jiao Tong University in
Materials Science.

The CIE-SF 2007 Annual Short Course is co-sponsored by CIE-SF EPMC and San
Jose State University.  This is the last short course, the previous 3 short
courses are Introduction to Electronic Packaging, presented by Mr. Andy
Tseng; Electrical and Thermal issues in Electronic Packaging, presented by
Dr. An-Yu Kuo; and System in Package (SIP) Design Flow and Applications,
presented by Mr. Shawn Nikoukary.

It is free to San Jose State University students/faculties, and Santa Clara
University students; for CIE members, it will be $20; for non-CIE members,
it will be $25.

Pre-registration is highly recommended.  Please email to
cie_shortcourse2007@yahoo.com with your name and email address.  Thanks.

Location: San Jose State University, Engineering Building (located on San
Fernando St. between 7th and 8th street)
Map: http://www.sjsu.edu/about_sjsu/docs/SJSU_campus_map.pdf
Free parking is available during weekends at Fourth St. Garage, 44 South
Fourth St., at San Fernando St. across from Dr. Martin Luther King, Jr.
Library

2007 CIE-SF Short Course Organizing Committee


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