Re: [IBIS-Users] How to decide on simulation time.

Hi Shrikant,
Of course the simulation time is dependent on the nominal frequency, but as 
Itzhak already mentioned it is dependent on buffer strength too. In general,
the simulation time should be:
1) long enough in order to reach the steady state with desired resolution (I 
mean the resolution the ibischk routine allows about V/T and  I/V tables
correlation, less than 2% for warning, if I remember correctly),
2) but not too long in order to get "overclocking free" tables, let's say:
     Tsimulation < Half of minimum nominal clock period.
(5nsec in your case of max 100MHz frequency). Otherwise you take a risk of 
some clipping problems in case the specific IBIS simulator does not use 
overclocking time tables correctly. For example, Hspice simulator does no 
special treatment, as far as I know.

By the way, if there is some kind of incompatibility between the two "rules" 
above, something is wrong with your buffer - it does not make sense that the
buffer is too weak to complete the transition in half of nominal clock 
period, this means that the buffer probably not functional at this frequency
(or that this is some "dead delay" in the V/T tables).

Best regards,
         Michael.
--
Michael Fishman,
Consulting Engineer,
iDEA++ Ltd.
http://www.ideapplications.net

----- Original Message ----- 
From: "Shrikant G Kadadevar" <Shrikant.G.Kadadevar@nsc.com>
To: "ibis-user" <ibis-users@server.eda.org>; "ibis" <ibis@server.eda.org>
Sent: Tuesday, March 04, 2008 11:30 AM
Subject: [IBIS-Users] How to decide on simulation time.


> Hello All,
>
> Please can you help me to know, how we come to conclusion on the maximum
> simulation time.
> Should this value depends on frequency.
> Suppose if i have 100MHz frequency buffer what must be maximum simulation
> time.
> Should the value be equal to 1/100MHz or  1/(2*100MHz).
> Or should it be independent.
>
>
> Thanking you
> Shrikant GK
>
>
> -- 
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