Re: [IBIS-Users] Understanding usage of ( Vmeas Vref Cref Rref )

Muniswara,

Thanks for your interest in IBIS!  Please note that traditional IBIS
(i.e., IBIS based on tables of I-V and V-t data, plus C_comp) does not
include any information about the buffer's stimulus from the core,
latches, die logic, etc.  So, the timing measurement parameters Rref,
Cref, Vref and Vmeas do not characterize Tco, Tvalid or any
clock-to-output or core-to-output behavior.  The IBIS timing measurement
parameters only describe the load used to characterize the time taken by
the output to reach the given measurement level (Vmeas) from the
stimulus edge presented to the IBIS model by the simulator.

Therefore, you may see a difference in delay time between the output
from a SPICE transistor-level model and an IBIS model of the same buffer
into the same load.  The overall shape of the waveform after the
transition begins should be identical, however, depending on the quality
of the IBIS model.

Some good presentations on these topics can be found on the IBIS website
at:

http://www.eda.org/ibis/training/

I hope this helps!

- Michael Mirmak
  Intel Corp. 
  Chair, IBIS Open Forum
  http://www.eigroup.org/ibis/
  http://www.eda.org/ibis/

------------------------------------------------------------------------

Hi,

If Timing Measurement Conditions describing parameters (Vmeas  Rref Vref
Cref) are included in a model, 

Does this imply that the delay ( core i/p to pad ) of IBIS or SPICE
Buffer  with this load conditions and measured at Vmeas will be same. 

      Tdelay (Vmeas  Rref  Vref  Cref )  (IBIS)     =  Tdelay (Vmeas
Rref  Vref  Cref )  (SPICE/Lab measurement)
         Tdelay <=  Delay from input to Pad
                 

With regards,

Muniswara Reddy . V

Design engineer, PIPD-IO group,

Bangalore.


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