[IBIS-Users] How to model Flip-Chip Die IBIS model

Hello All,

I need help to model a Flip-Chip die.

I have a .pkg file which models the RLC from the die bump to the BGA 
balls. I also have the IBIS models of individual IO?s.

On the die there is a connection from the IO to the Die Bump 
for which I have the Spice netlist.

1) Is there a way to plug this spice netlist between the IO and 
the die bump?

2) If not how do we consider the parasitics of this interconnect 
on the Chip Level IBIS model? It cannot be done inside the .pkg file
as it contains the impedance values which are frequency dependent.

3) Can we use a spice file instead of .pkg file for package 
modeling. If yes how?

Any help is highly appreciated.

Regards

Aman


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