RE: [IBIS-Users] IBIS Simulation algorithm

Andy,

You are making some really good points, but some of the
detail in your writing may be misleading or incorrect.

First, in modeling the transitions, we need to describe
two things. One is how the transistor of the buffer is
turning on, and the other is how it turns off. In plain
vanilla CMOS buffers we have a pullup and a pulldown
transistor in the output. When the buffer goes High to
Low, the pullup transistor gets turned off, and the
pulldown gets turned on. For Low to High transitions
the pulldown turns off and the pullup turns on. Since
designers try to avoid crow bar currents, they usually
turn the transistors off much faster then they turn the
other transistor on, so that they wouldn't be on together.

You can observe this very easily with a few simple
simulations. Take a buffer and put a resistor between
its output and ground. Take a second copy of the same
buffer and put a resistor of the same value between its
output and the power supply. Simulate a H to L and a
L to H transition with both and compare the four waveforms.

1) With the L to H transition with R to GND, rising edge
you see how the PU turns on. Initially the PD was on,
which is a low impedance path to GND, but the resistor was
also connected to GND, so the resistor and the transistor
are in parallel between the output and GND. No matter
whether this transistor is on or off, the resistor will
keep the output at 0 V. The only time the output voltage
will become different is when the pullup starts turning
on. When this happens, the output voltage will have a
value which is determined by the voltage division between
the pullup transistor connected to the supply rail and the
resistor connected to GND. This is why this waveform tells
us how the PU turns on.

2) With a H to L transition and the R still connected to
GND, we start with the pullup being on. As described above,
this creates a voltage divider between the power and GND.
As soon as the pullup transistor begins to turn off, the
resistor will start lowering the voltage towards GND. The
voltage will reach 0 V before the pulldown transistor
even begins to turn on. So this falling waveform will
show us how the pullup turned off.

The same thinking can also be applied to the situation
when the resistor is connected to the power rail. In that
case the rising edge will tell us how the pulldown turned
off and the falling edge will tell us how the pulldown
turned on.

If you looked at the loading conditions of [Ramp], you will
see that it gives you only the information about how the
transistors turn on, but it doesn't tell us how they turn
off (unless the buffer is an open_*** type). You will have
a hard time to implement a behavioral buffer algorithm
without knowing how to turn off the transistors. You will
have to guess, or assume something. (By the way, this is
what the "tune" parameters are for in the HSPICE B-element,
if I remember correctly). Since guessing leaves a lot of
room for inaccuracies, this is why we added the waveform
tables so quickly in IBIS v2.1 and stated that it was
highly recommended to have at least four waveform tables
in each [Model]. The added benefit of the waveform tables
is that the data contained in them can describe the shape
of the transition also, instead of just a straight line
(trapezoidal) edge.

Since I don't like to leave things to be guessed in my
simulations, I tend to stay away from using the [Ramp]
and tend to highly recommend the usage of the waveform
tables, and recommend four tables per CMOS buffer.

I hope my reasons are clear...

Arpad
============================================================

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Andrew Ingraham
Sent: Thursday, August 26, 2010 9:39 PM
To: ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS Simulation algorithm

> I also observe that, even if I remove the V-T table and supply only
the
> [Ramp] information, HSPICE is able to simulate the buffer model with
almost
> the same accuracy. [I have 4 VT (2 Rise and 2 Fall) tables originally]

Originally, IBIS had no V-T tables, and it worked OK. They were added
in a later revision to improve the transient accuracy.

Even after they were added to the IBIS spec, many simulators did not
use them. (Hspice took a while to catch up.)

How or why does it work without V-T tables? For most buffers,
waveforms are largely determined by the interaction between the
transistors (by way of their drive strengths in their On state), and
the load. How a driver gets from Off to On, is far less important
than how it interacts with the load, as described by its I-V curves.

For many buffers, their transistors are switched between Off and On
states faster than their outputs slew from L to H or H to L, because
of that interaction with the load. That means they spend most of the
time either Off (I=0), or fully On (I described by I-V table).

Without V-T tables, the simulator transitions between one transistor
fully On, to the other transistor fully On, over some short period of
time. The Ramp data helps the simulator control how quickly it should
go from one state to the other.

Andy

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