RE: [IBIS-Users] Overclocking Issue

Surendra,
 
SPICE simulators can handle over clocking because they use the
full transistor netlist (schematic) of a buffer and therefore
all the interactions inside the buffer are modeled. A behavioral
model like IBIS does not have all these details, and due to the
simplifications certain assumptions have to be made. One of these
assumptions in IBIS is that the buffer completes the transition
before it starts the next transition.
 
It is possible to write behavioral models which can model over
clocking, but the algorithms will have to be made more complicated.
The question then becomes can we write an algorithm which can
describe everything that goes on inside the buffer in a general
way so that all kinds of technologies and circuit design tricks
are covered when over clocking is happening? The answer may be a
no, and that why it is hard to include such effects using a few
generalized parameters in a specification like IBIS.
 
Arpad
=====================================================================

________________________________

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of surendra.deshmukh@wipro.com
Sent: Monday, September 20, 2010 1:53 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Overclocking Issue

Hi,

      Thanks to all who helped me by responding to my previous queries.

I want to know about "Over-clocking" issue. I get few doubts when I
think about Over-clocking.

How it affects the simulation result and what is the solution to
overcome this problem?

If spice simulator can handle it efficiently then why IBIS simulators
can not do it?

Thanks in advance.

Regards

Surendra

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