RE: [IBIS-Users]: Using HSPICE to run IBIS model

Bonnie,
 
I was working at Intel when the B-element and its variants were
added to HSPICE, and I worked quite a lot with the developer to
help him to get it right. I tested a lot of his work before and
after it was released. The various buffer types were all working
correctly as far as I remember. Your problem description doesn't
give me all the details to be able to pinpoint the problem, but I
wonder how do you expect the signal to move up or down when the
buffer turns off its (only) transistor but your circuit doesn't
seem to have a resistive connection to GND or Vcc?
 
Arpad
=================================================================

________________________________

From: Xuefeng Chen [mailto:Xuefeng.Chen@synopsys.com]
Sent: Wednesday, October 13, 2010 11:48 PM
To: Baker, Bonnie; Muranyi, Arpad; ibis-users@eda.org
Subject: RE: [IBIS-Users]: Using HSPICE to run IBIS model

Hi Bonnie,

  I am sure HSPICE supports all kinds of IBIS buffer types except external model of VERILOG-AMS or VHDL-A(MS).

  From the mail without the ibis file, it’s hard to figure out the issue. Would you like contact HSPICE related AC or CAE for help.

Thanks,
Xuefeng

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Baker, Bonnie
Sent: 2010年10月14日 11:53
To: Muranyi, Arpad; ibis-users@eda.org
Subject: [IBIS-Users]: Using HSPICE to run IBIS model

I am using Hspice to run IBIS and comparing it to a Spice simulation. The Spice simulates the buffer well but the Hspice program is having problems. My buffer type is I/O_open_drain.

The circuit diagram is:

-------------

I/O / R=0.5 L=2,5e-9

Open- /-----------/¥/¥/¥/¥-------|------/¥_/¥_/¥_/¥---------|---------O output

Drain / | |

Buffer / --- ----

------------ --- C=1e-12 ---- C=5e-12

                                             | |

                                         GND GND

The I/O buffer is driven with a rail to rail input signal. The output signal does to reach the rail as expected. It actually looks like:

---------------------expected-output-high--------------------------------------------------

                                                                       _______

                                                       _______/

                                      _______/

                          _____/

                  ___/

            __/

         _/

        /

       /

      /

__/______________________________________________________

I expect

---------------------expected-and-actual-output-high--------------------------------------------------

                /

               /

              /

             /

            /

           /

          /

         /

        /

       /

      /

__/______________________________________________________

It appears as if Hspice does not recognize the fact that this buffer is open drain.

Has anyone else experienced this and is the a work around?

The Hspice netlist is:

*

* HSPICED IBIS I/O open drain BUFFER TEST BENCH

* Temperature

.TEMP 27

* POWER SUPPLIES and SIGNAL VOLTAGES

VVCC VCC 0 DC=VCC

VGND GND 0 DC=GND

*PARAMETER DEFINITIONS

.PARAM GND = 0V

.PARAM VCC = VCC_typ

.PARAM VCC_typ = 1.8

* Simulation Options

.OPTIONS ACCT ACCURATE NOPAGE OPTS POST SCALE=1e-6

.OPTIONS METHOD=GEAR

 *=========TRANSIENT ANALYSIS sim========

.TRAN 0.1e-9 13000e-9 START =0.0e-9

* TD

VIN_ibis IN_ibis GND PULSE VCC GND 0ps 0.01ns 0.01ns 149.99ns 300n

*******************AC LOAD**************

B_IO nd_pu nd_pd Out_ibis IN_ibis nd_en SDA_signal nd_pc nd_gc

+ file = 'tsc2014_nokia_3.ibs' model = 'SDA_1'

+ typ = typ power = on

+ buffer = 6

+ ramp_fwf=1 ramp_rwf=1

Rpcb Out_ibis n1_pcb 0.50

Lpcb n1_pcb OUT_pcb_ibis 2.5e-9

Cpcb n1_pcb GND 1e-12

Cpcbload OUT_pcb_ibis GND 5e-12

Bonnie

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