hello Yuancheng,
there will be a talk at the upcoming DAC IBIS forum that may be of interest
to you.
In summary, the BIRD-95/98 power-aware IBIS features work surprisingly well
to match the balance of pwr/gnd/signal currents you observe in
transistor-level models.
To apply power-aware IBIS models you will need both a
transistor-to-behavioral model translator as well as a circuit simulator
than can each apply IBIS 5.0 compliant models. Both are available
commercially, though not yet common.
cheers,
-Brad
For reference you might want to see
http://www.eda.org/ibis/summits/may11/wolff.pdf
Also, coming up will be
IBIS SUMMIT MEETING, DAC, San Diego, CA, USA
Tuesday, June 7, 2011
9:00 AM IBIS PDN Feature Simulation Studies
Randy Wolff, Micron
Lance Wang, IO Methodology
_____
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of ji xiao
Sent: Tuesday, May 31, 2011 11:20 PM
To: ibis-users
Subject: [IBIS-Users] IBIS ver5.0 [composite current] and [ISSO PU/PD]
Dear all,
As I know, for solving the SSN problem, IBIS version 5.0 adds section
[composite current] and [ISSO PU/PD]. Then I have some questions:
1. How will the simulator work with the [composite current]? Does it
directly adopt the power terminal current value at the [composite current]
when the input voltage over the threshold voltage? But I feel different
rise/fall time will lead to different current value at the power terminal.
2. The section [ISSO PU/PD] is likely to provide a gate modulation
coefficent on the original output current. In specification, the
Ipu=Kpu(t)*Ipu(Vcc-Vout(t))*Ksso_pu(Vtable_pu) and
Ipd=Kpd(t)*Ipd(Vout(t))*Ksso_pd(Vtabke_pd). so does it mean the total output
current is Ipu+Ipd? how does the simulator decide the value of Kpu(t) and
Kpd(t) according to the data in IBIS file?
Thanks and regards,
Yuancheng
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