("pe_4tap.dml" (IbisIOCell (pe_4tap (MacroModel (MacroType TDiffIO ) (NumberOfTerminals 8 ) (Parameters (MinTypMaxParams (bitp 200p ) (rt 50 ) (scale 0.5 ) (padcap 1p ) (cf0 1 ) (cf1 0.269 ) (cf2 0.013 ) (cf3 0.1 ) (inv0 0 ) (inv1 1 ) (inv2 0 ) (inv3 1 ) ) ) (SubCircuits " * * The comment character inside the SubCircuits double quotes is a *. * * This model is for a 4-tap driver with pre-emphasis. * * The items listed in the Parameters section above are passed in and override * items in the various subcircuits below. * The Parameters for this particular Macromodel are as follows: * * Parameter bitp is for bit period. * Parameter rt is termination resistance. * Parameter scale is used to adjust the pulldown current source. * Parameter padcap is for die capacitance. * The cf values are coefficients for the 4 taps used in pre-emphasis. * The derived cf values were 1, 0.269, 0.013, 0.1. * To turn off pre-emphasis, set cf1-3 to 0. Leave cf0 as 1. * The inv values define current direction for the 4 taps. For example, * if inv3 is set for 1, then the current direction for tap3 is the opposite * of that used for tap2. * * ======================================================================== * * This MacroModel is of MacroType TDiffIO. It is a differential bdrvr. This * differs from a single-ended MacroModel, which uses a 7-terminal subcircuit. * A differential MacroModel such as this uses an 8-terminal subcircuit, the extra * terminal being the N-side output. * * The terminals in an 8-terminal differential MacroModel are as follows: * power = 1 * outp = 2 * ground = 3 * input = 4 * enable = 5 * power_clamp_reference = 6 * ground_clamp_reference = 7 * outn = 8 * * ======================================================================== * * This is the top-level subcircuit for MacroModel pe_4tap. * It MUST have the same name as the IOCell, or it will not work. * .subckt pe_4tap nvdd outp ngnd in en pcl gcl outn + bitp=400p + cf0=0 + cf1=1 + cf2=0 + cf3=0 + inv0=1 + inv1=0 + inv2=1 + inv3=0 + scale=2.75 + padcap=2p + rt=50 * Some voltage sources are defined to drive the MacroModel. This uses an E element, * which is a VCVS, or voltage controlled voltage source. * * P side input voltage to differential buffer einp in2 ngnd v='v(in, ngnd)' * v(in, ngnd) means the potential difference between nodes in and ngnd * * N side input voltage to differential buffer einn inn ngnd v='1 - v(in2, ngnd)' * The node_param statement tells tlsim to save this waveform for SigWave display. * Using the special syntax below, tlsim automatically increments a unique name suffix. .node_param in2 name=(tx_ name(in)) print * The VCVS below derives a differential voltage. etx tx 0 v='v(outp, outn)' * This is then saved in the sim file for SigWave with the node_param statement below. .node_param tx name=(tx_ name(outp)) print * There are 2 drivers in this macromodel, for both the P side and N side. * P side driver subcircuit call xp nvdd outp ngnd in2 en txpre_2 bitp=bitp + inv0=inv0 inv1=inv1 inv2=inv2 inv3=inv3 + scale=scale + padcap=padcap + cf0=cf0 + cf1=cf1 + cf2=cf2 + cf3=cf3 + rt=rt * N side driver subcircuit call xn nvdd outn ngnd inn en txpre_2 bitp=bitp + inv0=inv0 inv1=inv1 inv2=inv2 inv3=inv3 + scale=scale + padcap=padcap + cf0=cf0 + cf1=cf1 + cf2=cf2 + cf3=cf3 + rt=rt * Here is the main single-ended driver subcircuit, called txpre_2. .subckt txpre_2 nvdd out ngnd in en + bitp=400p + inv0=1 + inv1=0 + inv2=1 + inv3=0 + cf0=0 + cf1=1 + cf2=0 + cf3=0 + scale=2 + padcap=2p + rt=50 * Termination resistor and pad capacitance elements. r nvdd out 'rt' c out ngnd 'padcap' * Here are the subcircuit calls for tap inputs, using subcircuit delayin. xin0 in0 in ngnd delayin inv=inv0 xin1 in1 in ngnd delayin inv=inv1 del='bitp' xin2 in2 in ngnd delayin inv=inv2 del='2 * bitp' xin3 in3 in ngnd delayin inv=inv3 del='3 * bitp' * Here are the subcircuit calls for subcircuit tx, containing the current * source used for the taps. xtx0 nvdd out ngnd in0 en tx scale='scale * cf0' xtx1 nvdd out ngnd in1 en tx scale='scale * cf1' xtx2 nvdd out ngnd in2 en tx scale='scale * cf2' xtx3 nvdd out ngnd in3 en tx scale='scale * cf3' * This is the subcircuit definition for tx, the current source for the taps. .subckt tx nvdd out ngnd in en scale=1 rout2 out2 out 0.1 rout3 out3 out 0.1 rout32 out3 ngnd 1e4 cout3 out3 out2 0.1p rngnd2 ngnd2 ngnd 0.1 * * This G element is the current source used for the taps. * It is dependent on the VCCS E element following it. * rin2 in in2 0.2 cin2 in2 ngnd 0.1p gdn out2 ngnd2 i='scale * v(in2) * v(en) * v(pdn)' epdn pdn 0 pwl out3 ngnd * * The data points below describe the VCCS behavior. It acts as the * pulldown for the driver, and gets scaled by the scale parameter. * It is essentially a 16mA current source in this example. * datapoints vi -0.4 -0.05 0.0 0.0 0.1 0.008 0.2 0.014 0.3 0.015 1.0 0.016 2.0 0.017 end vi .ends tx * The delayin subcircuit drives the inputs to the tx subcircuit. .subckt delayin in1 in ngnd inv=0 del=0 ein2 in2 ngnd v='inv * (1 - v(in,ngnd)) + (1-inv) * v(in,ngnd)' ein1 in1 ngnd pwl in2 ngnd delay=del datapoints vv 0 0 1 1 end vv .ends delayin .ends txpre_2 .ends pe_4tap " ) ) (Model (ModelType Output ) ) (PowerClamp (ReferenceVoltage (maximum 1.3 ) (minimum 1.3 ) (typical 1.3 ) ) ) (GroundClamp (ReferenceVoltage (maximum 0 ) (minimum 0 ) (typical 0 ) ) ) (PullDown (ReferenceVoltage (maximum 0 ) (minimum 0 ) (typical 0 ) ) ) (PullUp (ReferenceVoltage (maximum 1.3 ) (minimum 1.3 ) (typical 1.3 ) ) ) (Ramp (Fall (maximum (dt 4.2e-011 ) (dV 0.36 ) ) (minimum (dt 4.2e-011 ) (dV 0.24 ) ) (typical (dt 4.2e-011 ) (dV 0.3 ) ) ) (Rise (maximum (dt 4.2e-011 ) (dV 0.36 ) ) (minimum (dt 4.2e-011 ) (dV 0.24 ) ) (typical (dt 4.2e-011 ) (dV 0.3 ) ) ) ) (Technology CMOS ) (VIReferenceTemperature (maximum 0 ) (minimum 110 ) (typical 25 ) ) (Notes "This example MacroModel was provided by CADENCE DESIGN SYSTEMS, INC. to facilitate the work of the IBIS MacroModel Committee. The original template for this model was developed by Dr. C. Kumar." ) ) ) (LibraryVersion 136.2 ) )