// This is -*- Verilog-A -*-

// ============================================================================
//
// (c) Copyright 2005, All Rights Reserved, Philips Electronics N.V.
//
//
// Version: August 22, 2005
//
// ============================================================================

// Spice primitives
// Verilog-AMS LRM 2.0 Annex E "SPICE compatibility"

`include "disciplines.vams"
`include "constants.vams"

`ifdef CAPACITOR_VA
`else
`define CAPACITOR_VA 1

/**
 * @brief linear capacitor with initial condition.
 *
 * A linear capacitor is defined by the constituent relationship I = C*dV/dt.
 * In Verilog-A we use this differential form, but some additional code is
 * needed to handle the initial condiction.
 *
 * If the capacitance is 0, the conductor resolves to an open.
 *
 * @param c		capacitance in [F].
 * @param ic		initial condition in [V].
 */

module Capacitor (p, n);
inout p, n;
electrical p, n;
parameter c = 1n;
parameter ic = 0.0;

integer init;

analog begin

  @(initial_step)
    init = 1;

  if (init) begin
    V(p, n) <+ ic;
    init = 0;
  end

  I(p, n) <+ c * ddt(V(p, n));

end

endmodule // Capacitor

`endif