// This is -*- Verilog-A -*-

// ============================================================================
//
// (c) Copyright 2005, All Rights Reserved, Philips Electronics N.V.
//
//
// Version: August 22, 2005
//
// ============================================================================

// Spice primitives
// Verilog-AMS LRM 2.0 Annex E "SPICE compatibility"

`include "disciplines.vams"
`include "constants.vams"

`ifdef INDUCTOR_VA
`else
`define INDUCTOR_VA 1

/**
 * @brief linear inductor with initial condition.
 *
 * A linear inductor is defined by the constituent relationship V = L*dI/dt.
 * In Verilog-A we use the integral form (I = idt(V)/L) as that better fits
 * the use of modified nodal analysis used in the matrix formulations of most
 * analog simulators. It also gives an easy way to handle th initial condition.
 *
 * If the inductance is 0, the inductor resolves to a short.
 *
 * @param l		inductance in [H].
 * @param ic		initial condition in [A].
 */

module Inductor (p, n);
inout p, n;
electrical p, n;
parameter l = 1u;
parameter ic = 0.0;

analog begin

  if (l != 0.0)
    I(p, n) <+ idt(V(p, n) / l, ic);
  else
    // if l == 0 we have a short.
    V(p, n) <+ 0;

end

endmodule // Inductor

`endif