// This is -*- Verilog-A -*-

// ============================================================================
//
// (c) Copyright 2005, All Rights Reserved, Philips Electronics N.V.
//
//
// Version: August 22, 2005
//
// ============================================================================

// Spice primitives
// Verilog-AMS LRM 2.0 Annex E "SPICE compatibility"

`include "disciplines.vams"
`include "constants.vams"

`ifdef VCCS_VA
`else
`define VCCS_VA 1

/**
 * @brief linear voltage-controlled current source.
 *
 * The current output by this source is controlled by a voltage measured
 * between the sink and source nodes, and multiplied by a current gain factor
 * which is 1 by default.
 *
 * If the current gain is 0, the current source resolves to an open.
 *
 * @param gm		current gain.
 */

module Vccs (sink, src, ps, ns);
inout sink, src, ps, ns;
electrical sink, src, ps, ns;
parameter gm = 1.0;

analog begin

  I(ps, ns) <+ gm * V(sink, src);

end

endmodule // Vccs

`endif