// This is -*- Verilog-A -*-

// ============================================================================
//
// (c) Copyright 2005, All Rights Reserved, Philips Electronics N.V.
//
//
// Version: August 22, 2005
//
// ============================================================================

// Spice primitives
// Verilog-AMS LRM 2.0 Annex E "SPICE compatibility"

`include "disciplines.vams"
`include "constants.vams"

`ifdef VCVS_VA
`else
`define VCVS_VA 1

/**
 * @brief linear voltage-controlled voltage source.
 *
 * The voltage output by this source is controlled by a voltage measured
 * between the p and n nodes, and multiplied by a voltage gain factor which
 * is 1 by default.
 *
 * If the voltage gain is 0, the voltage source resolves to a short.
 *
 * @param gain		voltage gain.
 */

module Vcvs (p, n, ps, ns);
inout p, n, ps, ns;
electrical p, n, ps, ns;
parameter gain = 1.0;

analog begin

  V(ps, ns) <+ gain * V(p, n);

end

endmodule // Vcvs

`endif