>>> SPICE
*============================================================================
Vpls  Pls  0  PULSE  ( 0.0  1.0  1.0ns  1.0ns  1.0ns  4.0ns  10.0ns )
*
R1  Pls     VHDL_p  R= 100
X1  VHDL_p  0       IBIS_L_VHDL(Simple_test)
*
.IC I(L2) = -0.005
R2  Pls   RL  R= 100
L2  RL    0   L= 20.0nH
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_L_VHDL is
    port (terminal  Node_p,  Node_n  : electrical);
end entity IBIS_L_VHDL;

architecture Simple_test of IBIS_L_VHDL is

begin

   IBIS_L1 : entity MacroLib.IBIS_L(IDEAL)
      generic map ( Lval  => 10.0e-9,
                    I0    =>  -0.005,
                    Scale =>  2.0 )
      port map ( P => Node_p,
                 N => Node_n );

end architecture Simple_test;
--===========================================================================