>>> SPICE
*============================================================================
Vvcc  Vvcc  0  DC= 5.0
Vpls  Pls   0  PULSE  ( 0.0  5.0  1.0ns  1.0ps  1.0ps  4.999ns  10.0ns )
*
R1  Pls  In    R= 100
X1  In   Vvcc  0    Rcv  IBIS_INPUT_VHDL(Simple_test)
*   in   pow   gnd  rcv
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_INPUT_VHDL is
    port (terminal  Input,   Power,
                    Ground,  RcvOut  : electrical);
end entity IBIS_INPUT_VHDL;

architecture Simple_test of IBIS_INPUT_VHDL is

begin

   IBIS_INPUT1 : entity MacroLib.IBIS_INPUT(SIMPLE_RECEIVER)
   --------------------------------------------------
   --  Use ONLY ONE of the following four lines
   --------------------------------------------------
      generic map ( DataFile => ".\Macro_lib\No_ODT_IO_data.txt" )
--      generic map ( DataFile => ".\Macro_lib\ODT_to_GND_IO_data.txt" )
--      generic map ( DataFile => ".\Macro_lib\ODT_to_Vcc_IO_data.txt" )
--      generic map ( DataFile => ".\Macro_lib\ODT_to_VccGND_IO_data.txt" )
      port map ( PC_ref   => Power,
                 GC_ref   => Ground,
                 Pad      => Input,
                 Rcv_D    => RcvOut );

end architecture Simple_test;
--===========================================================================