>>> SPICE
*============================================================================
Vdc    Vdc  0  DC= 0.5
Vctrl  Pls  0  PULSE  ( 0.0  1.0  1.0ns  0.1ns  0.1ns  4.9ns  10.0ns )
*
R1  Pls      VHDL_n1         R= 60
X1  VHDL_n1  0        n2  0  IBIS_T_VHDL(Simple_test)
R2  n2       Vdc             R= 60
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_T_VHDL is
    port (terminal  Node_n1,  Node_ref1,
                    Node_n2,  Node_ref2   : electrical);
end entity IBIS_T_VHDL;

architecture Simple_test of IBIS_T_VHDL is

begin

   IBIS_T1 : entity MacroLib.IBIS_T(IDEAL)
      generic map ( Z0 => 60.0,
                    TD =>  0.5e-9 )
      port map ( N1   => Node_n1,
                 REF1 => Node_ref1,
                 N2   => Node_n2,
                 REF2 => Node_ref2 );

end architecture Simple_test;
--===========================================================================