>>> SPICE
*============================================================================
Vpls  Pls  0  PULSE  ( 0.0  1.0  1.0ns  1.0ns  1.0ns  4.0ns  10.0ns )
*
R1  Pls     VHDL_p  R= 100
X1  VHDL_p  0       IBIS_C_VHDL(Simple_test)
*
.IC V(RC) = 0.5
R2  Pls   RC  R= 100
C2  RC    0   C= 10.0pF
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_C_VHDL is
    port (terminal  Node_p,  Node_n  : electrical);
end entity IBIS_C_VHDL;

architecture Simple_test of IBIS_C_VHDL is

begin

   IBIS_C1 : entity MacroLib.IBIS_C(IDEAL)
      generic map ( Cval  =>  5.0e-12,
                    V0    =>  0.5,
                    Scale =>  2.0 )
      port map ( P => Node_p,
                 N => Node_n );

end architecture Simple_test;
--===========================================================================