`include "constants.vams"
`include "disciplines.vams"
`include "IBIS_macro_library.va"

module KT_Net (In1, In2, In3, In4);
   inout       In1, In2, In3, In4;
   electrical  In1, In2, In3, In4;

   parameter  real  Lval  =  10.0e-9;
   parameter  real  ILval =   0.1;
   parameter  real  Scale =   2.0;

//=============================================================================
// These are examples for instantiating the various building bloks in the
// Verilog-A library contained in the IBIS_macro_library.va file.
//=============================================================================

 IBIS_K #(.Lval_1(Lval), .Lval_2(Lval), .Kval(0.5), .Scale(1.0), .I0_1(0.1), .I0_2(0.1))  L1  (In1, In2, In3, In4);

// IBIS_T #(.Z0(10), .TD(1.0e-9))  T1  (In1, In2, In3, In4);

endmodule