Verilog-A buffer test
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.TRAN 1.0ps 25.0ns
.OPTIONS POST=1 POST_VERSION=9007 PROBE
.hdl ".\AMS_files\LibNet.va"
**********************************************************************
.PROBE TRAN
+ Pls = V(PlsV)
+ Out = V(Out)
+ Rcv = V(Rcv)
*
+ OutB = V(OutB)
+ RcvB = V(RcvB)
**********************************************************************
Vvcc    Vcc    0  DC= 5.0
Vvtt    Vtt    0  DC= 2.5
Vpls    PlsV   0  PULSE  ( 0.0V  1.0V 1.0ns   1.0ps   1.0ps 10.0ns 20.0ns)
**********************************************************************
*
X1      PlsV  Out  Vcc  0  Vcc  Rcv  LibNet
Rload1  Out   Vtt  R= 50.0
Rload2  Rcv   0    R= 1.0k
*
*B1  Vcc  0  OutB  PlsV  Vcc  RcvB  Vcc  0
*+ file     = 'test_ams.ibs'
*+ model    = 'io50v_no_ODT'
*+ buffer   = 3
*+ ramp_rwf = 2
*+ ramp_fwf = 2
*+ power    = off

B1  Vcc  0  OutB  PlsV  Vcc  RcvB  Vcc  0
+ file     = 'test_ams.ibs'
+ model    = 'io50v_OSrc'
+ buffer   = 10
+ ramp_rwf = 1
+ ramp_fwf = 1
+ power    = off
Rload1B  OutB   Vtt  R= 50.0
Rload2B  RcvB   0    R= 1.0k

C1  OutB 0 C= 5.0pF
**********************************************************************
.END
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