`include "constants.vams"
`include "disciplines.vams"
`include "IBIS_macro_library.va"

module T_PWL_Net (In1, In2, In3, In4);
   inout          In1, In2, In3, In4;
   electrical     In1, In2, In3, In4;

//=============================================================================
// These are examples for instantiating the various building bloks in the
// Verilog-A library contained in the IBIS_macro_library.va file.
//=============================================================================

    IBIS_VECVS_PWL  #(.Scale(1), .Edge(1))  E1  (In1, In2, In3, In4);
//  IBIS_CECVS_PWL  #(.Scale(1), .Edge(1))  E1  (In1, In2, In3, In4);
//  IBIS_VECCS_PWL  #(.Scale(1), .Edge(1))  E1  (In1, In2, In3, In4);
//  IBIS_CECCS_PWL  #(.Scale(1), .Edge(1))  E1  (In1, In2, In3, In4);

//  IBIS_TCVS_PWL  #(.Scale(1))  E1  (In1, In2);
//  IBIS_TCCS_PWL  #(.Scale(1))  E1  (In1, In2);

endmodule