`include "constants.vams"
`include "disciplines.vams"
`include "IBIS_macro_library.va"

module PWL_Net (In1, In2, In3, In4);
   inout        In1, In2, In3, In4;
   electrical   In1, In2, In3, In4;

//=============================================================================
// These are examples for instantiating the various building bloks in the
// Verilog-A library contained in the IBIS_macro_library.va file.
//=============================================================================

  IBIS_VCVS_PWL  #(.Length(4), .Y({ 0.08,  0.00,  0.00,  0.00}),
                               .X({-5.00, -1.00,  5.00, 10.00}), .Scale(2))  E1  (In1, In2, In3, In4);
//IBIS_VCCS_PWL  #(.Length(4), .Y({ 0.08,  0.00,  0.00,  0.00}),
//                             .X({-5.00, -1.00,  5.00, 10.00}))             G1  (In1, In2, In3, In4);
//IBIS_CCVS_PWL  #(.Length(4), .Y({ 0.08,  0.00,  0.00,  0.00}),
//                             .X({-5.00, -1.00,  5.00, 10.00}))             H1  (In1, In2, In3, In4);
//IBIS_CCCS_PWL  #(.Length(4), .Y({ 0.08,  0.00,  0.00,  0.00}),
//                             .X({-5.00, -1.00,  5.00, 10.00}))             F1  (In1, In2, In3, In4);

endmodule