`include "constants.vams"
`include "disciplines.vams"
`include "IBIS_macro_library.va"

module SRC_Net (In1, In2, In3, In4, In5, In6);
   inout        In1, In2, In3, In4, In5, In6;
   electrical   In1, In2, In3, In4, In5, In6;

//=============================================================================
// These are examples for instantiating the various building bloks in the
// Verilog-A library contained in the IBIS_macro_library.va file.
//=============================================================================

   IBIS_VCVS_MIN  E1  (In1, In2, In3, In4, In5, In6);
// IBIS_VCVS_MAX  E1  (In1, In2, In3, In4, In5, In6);

// IBIS_VCCS_MIN  G1  (In1, In2, In3, In4, In5, In6);
// IBIS_VCCS_MAX  G1  (In1, In2, In3, In4, In5, In6);

// IBIS_VCVS_ABS  E1  (In1, In2, In3, In4);
// IBIS_VCCS_ABS  G1  (In1, In2, In3, In4);

// IBIS_CCVS_MIN  H1  (In1, In2, In3, In4, In5, In6);
// IBIS_CCVS_MAX  H1  (In1, In2, In3, In4, In5, In6);

// IBIS_CCCS_MIN  F1  (In1, In2, In3, In4, In5, In6);
// IBIS_CCCS_MAX  F1  (In1, In2, In3, In4, In5, In6);

// IBIS_CCVS_ABS  H1  (In1, In2, In3, In4);
// IBIS_CCCS_ABS  F1  (In1, In2, In3, In4);

endmodule