`include "constants.vams"
`include "disciplines.vams"
`include "IBIS_macro_library.va"

module Buf_Net (In1, In2, In3, In4, In5, In6);
   inout        In1, In2, In3, In4, In5, In6;
   electrical   In1, In2, In3, In4, In5, In6, InX;

   parameter  real  Rval  = 100.0;
   parameter  real  Cval  =   2.0e-12;
   parameter  real  Lval  =  10.0e-9;
   parameter  real  ICval =   0.5;
   parameter  real  ILval =   0.1;
   parameter  real  Delay =   0.2e-9;
   parameter  real  Scale =   2.0;

//=============================================================================
// These are examples for instantiating the various building bloks in the
// Verilog-A library contained in the IBIS_macro_library.va file.
//=============================================================================


//=============================================================================
// This is the syntax for calling a Verilog-A IBIS buffer with the
// IV and VT data arrays inline
//-----------------------------------------------------------------------------
//  IBIS_IO  #(.IVpc_length(4), .I_pc({ 0.08,  0.00,  0.00,  0.00}),
//                              .V_pc({-5.00, -1.00,  5.00, 10.00}), 
//             .IVpu_length(4), .I_pu({ 0.10,  0.00, -0.10, -0.20}), 
//                              .V_pu({-5.00,  0.00,  5.00, 10.00}), 
//             .IVpd_length(4), .I_pd({-0.10,  0.00,  0.10,  0.20}), 
//                              .V_pd({-5.00,  0.00,  5.00, 10.00}), 
//             .IVgc_length(4), .I_gc({-0.10,  0.00,  0.10,  0.20}), 
//                              .V_gc({-5.00,  0.00,  5.00, 10.00}),
//  
//             .VTr1_length(4), .Vr1({0.00,  0.00,     1.66,     1.66}),
//                              .Tr1({0.00,  1.00e-9,  2.00e-9,  3.00e-9}),
//             .VTr2_length(6), .Vr2({1.66,  1.66,     2.50,     2.50,     3.33,     3.33}),
//                              .Tr2({0.00,  0.50e-9,  0.80e-9,  1.00e-9,  2.00e-9,  3.00e-9}),
//             .VTf1_length(6), .Vf1({3.33,  3.33,     2.50,     2.50,     1.66,     1.66}),
//                              .Tf1({0.00,  0.50e-9,  0.80e-9,  1.00e-9,  2.00e-9,  3.00e-9}),
//             .VTf2_length(4), .Vf2({1.66,  1.66,     0.00,     0.00}),
//                              .Tf2({0.00,  0.50e-9,  0.80e-9,  3.00e-9}) )
//  B1  (In3,    In4,    In2, In1,  In5,  InX,   In3,    In4);
////    (PU_ref, PD_ref, IO,  In_D, En_D, Rcv_D, PC_ref, GC_ref)
//=============================================================================


//=============================================================================
// This is the syntax for calling a Verilog-A IBIS buffer with the IV and VT
// data arrays hidden away in external files.  Please note that the external
// file MUST follow the Verilog-A syntax shown in the example files in order
// to work.  The arrays can be formatted in columns, but each line must end
// with a backslash "\" character (for line continuation), and after the last
// character of the last line there MUST be an additional "new line" character.
// I.e. the file cannot end with the closing parentheses ")" character on the
// last line of data.
//
// If multiple instances of the same IBIS_IO buffer module need to be used with 
// different IV-VT tables, the corresponding data files must have unique macro
// names at the top.  These unique macro names can then be used in the calling
// statement below.
//-----------------------------------------------------------------------------
`include "IV_data_no_ODT.dat"          // Select one of the four IV-VT pairs
`include "VT_data_no_ODT.dat"

//`include "IV_data_ODT_GND.dat"
//`include "VT_data_ODT_GND.dat"

//`include "IV_data_ODT_Vcc.dat"
//`include "VT_data_ODT_Vcc.dat"

//`include "IV_data_ODT_Vcc_GND.dat"
//`include "VT_data_ODT_Vcc_GND.dat"

//-----------------------------------------------------------------------------
// Instantiating the IBIS_IO module doesn't require parameter passing.  If
// no parameters are passed, the defaults inside the module will be in effect.
//-----------------------------------------------------------------------------
//  IBIS_IO  #(`IV_data)            B1  (In3,    In4,    In2, In1,  In5,  InX,   In3,    In4);
//  IBIS_IO  #(`IV_data, `VT_data)  B1  (In3,    In4,    In2, In1,  In5,  InX,   In3,    In4);
////                                    (PU_ref, PD_ref, IO,  In_D, En_D, Rcv_D, PC_ref, GC_ref)
//=============================================================================

    IBIS_INPUT  #(.Vinh(3.0), .Vinl(2.0))  B2  (In3,    In4,    In2,   In6);
//                                             (PC_ref, GC_ref, Input, Rcv_D);
//  IBIS_OUTPUT                            B1  (In3,    In4,    In2, In1,  In3,    In4);
//                                             (PU_ref, PD_ref, Out, In_D, PC_ref, GC_ref)
//  IBIS_3STATE                            B1  (In3,    In4,    In2, In1,  In5,  In3,    In4);
//                                             (PU_ref, PD_ref, IO,  In_D, En_D, PC_ref, GC_ref)
//  IBIS_OPENSINK                          B1  (In3,    In4,    In2, In1,  In3,    In4);
//                                             (PU_ref, PD_ref, IO,  In_D, PC_ref, GC_ref)
//  IBIS_IO_OPENSINK                       B1  (In3,    In4,    In2, In1,  In5,  InX,   In3,    In4);
//                                             (PU_ref, PD_ref, IO,  In_D, En_D, Rcv_D, PC_ref, GC_ref)
    IBIS_OPENSOURCE                        B1  (In3,    In4,    In2, In1,  In3,    In4);
//                                             (PU_ref, PD_ref, IO,  In_D, PC_ref, GC_ref)
//  IBIS_IO_OPENSOURCE                     B1  (In3,    In4,    In2, In1,  In5,  InX,   In3,    In4);
//                                             (PU_ref, PD_ref, IO,  In_D, En_D, Rcv_D, PC_ref, GC_ref)

endmodule