>>> SPICE
*============================================================================
Vdc     Vdc     0  DC= 1.0
Vctrl1  Ctrl_1  0  DC= 5.0
Vctrl2  Ctrl_2  0  PULSE  ( -1.0  1.0  1.0ns  1.0ns  1.0ns  4.0ns  10.0ns )
*
R1  Vdc     VHDL_p                        R= 100
X1  VHDL_p  0       Ctrl_1  0  Ctrl_2  0  IBIS_VCVS_DIV_VHDL(Simple_test)
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_VCVS_DIV_VHDL is
    port (terminal  Node_p,   Node_n,
                    Ctrl_p1,  Ctrl_n1,
                    Ctrl_p2,  Ctrl_n2   : electrical);
end entity IBIS_VCVS_DIV_VHDL;

architecture Simple_test of IBIS_VCVS_DIV_VHDL is

begin

   IBIS_VCVS_DIV1 : entity MacroLib.IBIS_VCVS_DIV(IDEAL)
      generic map ( Scale     => 0.1,
                    ZeroLimit => 1.0e-3 )
      port map ( P   => Node_p,
                 N   => Node_n,
                 PS1 => Ctrl_p1,
                 NS1 => Ctrl_n1,
                 PS2 => Ctrl_p2,
                 NS2 => Ctrl_n2 );

end architecture Simple_test;
--===========================================================================