>>> SPICE
*============================================================================
Vvcc  Vvcc  0  DC= 5.0
Vvtt  Vvtt  0  DC= 5.0
Vpls  Pls   0  PULSE  ( 0.0  1.0  1.0ns  0.1ns  0.1ns  9.9ns  20.0ns )
*
X1  Pls  Out  Vvcc  0    Vvcc  IBIS_IO_OPENSINK_VHDL(Simple_test)
*   in   out  pow   gnd  en
*
R1  Out  Vvtt R= 50
C1  Out  Vvtt C= 5.0pF   $ Substitutes C_comp in the VHDL-AMS model
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_IO_OPENSINK_VHDL is
    port (terminal  Input,  Output,
                    Power,  Ground,
                    Enable           : electrical);
end entity IBIS_IO_OPENSINK_VHDL;

architecture Simple_test of IBIS_IO_OPENSINK_VHDL is

begin

   IBIS_IO_OPENSINK1 : entity MacroLib.IBIS_IO_OPENSINK(IBIS_1EQ1UK)
   --------------------------------------------------
   --  Use ONLY ONE of the following four lines
   --------------------------------------------------
      generic map ( DataFile => ".\Macro_lib\No_ODT_IO_OPENSINK_data.txt",
--      generic map ( DataFile => ".\Macro_lib\ODT_to_GND_IO_OPENSINK_data.txt",
--      generic map ( DataFile => ".\Macro_lib\ODT_to_Vcc_IO_OPENSINK_data.txt",
--      generic map ( DataFile => ".\Macro_lib\ODT_to_VccGND_IO_OPENSINK_data.txt",
                    kI_pc => 1.0,
                    kI_pd => 1.0,
                    kI_gc => 1.0,
                    kt_rise => 1.0,
                    kt_fall => 1.0 )
      port map ( PU_ref   => Power,
                 PD_ref   => Ground,
                 Pad      => Output,
                 In_D     => Input,
                 EN_D     => Enable,
--                 Rcv_D    => RcvOut,
                 PC_ref   => Power,
                 GC_ref   => Ground );

end architecture Simple_test;
--===========================================================================