*Min rising waveform curve for model DQBUFF_FULL
*Spice Deck created by S2IBIS3 Version 1.1 
*North Carolina State University 
******************** 128Mx4, 64Mx8, 32Mx16 DDR400 SDRAM **********************
*******************Example HSPICE setup file for DQs and DQS*******************
***********************************************************
****           ____                                       *
****      IN--|    \                                      *
****          |     }------PAD--\/\/\/--@@@@--|--PKG_OUT  *
****   ENOUT--|____/    |        R_pkg  L_pkg |           *
****                    |                    ===C_pkg     *
****             ___    |                     |           *
****            /  +|---|                    GND          *
**** RCVR_OUT--{   -|-----VREF                            *
****            \___|-(ENOUT#)                            *
***********************************************************
**** This netlist is for the x4, x8, and x16 512Mb DDR400 DDR SDRAM **********
**** The input signals are IN (input signal) and ENOUT (output enable signal).
**** The I/O data is available on the signal PAD.
**** The output of the input receiver circuit is the node RCVR_OUT.
**** To account for package parasitics correlative impedance values
**** (netlist elements R_pkg, L_pkg, C_pkg) have been attached to the PAD
**** node.  The package output is on the signal PKG_OUT.
**** NOTE: This spice file is not designed to match datasheet timing numbers. 
****       Delay times are smaller than those given in the data sheets.
**** To run this simulation, the files "model.cnr" and "dqbuff.inc" are 
**** required to be in the same directory as this netlist.
**** Temperature settings are: Typical 40C, Slow 85C, Fast 0C   
.OPTIONS METHOD=GEAR DCON=1
.OPTIONS SEARCH=' '  $This option must be present for decryption to work
**** Input signals and power supplies setup
**** Note: vccp and vccr are regulated internal voltages
**** Match up typ, min, or max voltages for corner sims
*Vvccq   vccq  0  DC = vccq
Vvcc    vcc   0  DC = vcc 
Vvccr   vccr  0  DC = vccr 
Vvccp   vccp  0  DC = vccp 
*Vvssq   vssq  0  DC = 0
Vvref   vref  0  DC = 'vccq/2'
Vdrv    fulldrv  0  DC = vccr  $vccr = 100%, gnd = 54%
**The fulldrv node selects between Full and Reduced output drive strengths.
xi0 tscore fulldrv incore vref pad rcvr_out vccp vccq vssq vcc 0 vccr dqbuff
rload rcvr_out 0 1000000
ets tscore 0 ts 0 'vccr'
ein incore 0 in 0 'vccr'
.LIB "model.cnr" SS
.PARAM  vccq  = 2.50V
.PARAM  vcc   = 2.50V
.PARAM  vccr   = 1.925V
.PARAM  vccp   = 3.413V
RFIXS2I pad dum17854  50.0

VCCS2I vccq 0  DC 2.5
VGNDS2I vssq 0  DC 0.0

 
VENAS2I ts 0 DC 1.0
VINS2I in 0 PULSE(0.0 1.0 0 1.0E-10 1.0E-10 6.000000000000001E-9 1.2400000000000002E-8)

VFIXS2I dum17854 0 DC 0.0

.TEMP 85.0

.OPTIONS INGOLD=2.0

.TRAN 3.0000000000000006E-11 3.0000000000000004E-9 
.PRINT TRAN V(pad)

.END