>>> SPICE
*============================================================================
Vdc    Vdc  0     DC= 1.0
Ictrl  0    Ctrl  PULSE  ( -10.0  10.0  1.0ns  4.0ns  4.0ns  1.0ns  10.0ns )
*
R1  Vdc     VHDL_p           R= 100
X1  VHDL_p  0       Ctrl  0  IBIS_CCVS_PWL_VHDL(Simple_test)
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_CCVS_PWL_VHDL is
    port (terminal  Node_p,  Node_n,
                    Ctrl_p,  Ctrl_n   : electrical);
end entity IBIS_CCVS_PWL_VHDL;

architecture Simple_test of IBIS_CCVS_PWL_VHDL is

begin

   IBIS_CCVS_PWL1 : entity MacroLib.IBIS_CCVS_PWL(IDEAL)
      generic map ( Scale => 20.0 )
      port map ( P  => Node_p,
                 N  => Node_n,
                 PS => Ctrl_p,
                 NS => Ctrl_n );

end architecture Simple_test;
--===========================================================================