>>> SPICE
*============================================================================
Vpls  Pls  0  PULSE  ( 0.0  1.0  1.0ns  1.0ns  1.0ns  4.0ns  10.0ns )
*
R1  Pls     VHDL_p  R= 1.0
X1  VHDL_p  0       IBIS_I_VHDL(Simple_test)
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_I_VHDL is
    port (terminal  Node_p,  Node_n  : electrical);
end entity IBIS_I_VHDL;

architecture Simple_test of IBIS_I_VHDL is

begin

   IBIS_I1 : entity MacroLib.IBIS_I(IDEAL)
      generic map ( Idc   => -0.5,
                    Scale =>  2.0 )
      port map ( P => Node_p,
                 N => Node_n );

end architecture Simple_test;
--===========================================================================