>>> SPICE
*============================================================================
Vpls   Pls  0     PULSE  ( 0.0  1.0  1.0ns  1.0ps  1.0ps  50.0ns  100.0ns )
Ictrl  0    Ctrl  PULSE  ( 1.0  0.1  3.0ns  1.0ns  1.0ns   4.0ns   10.0ns )
*
R1  Pls     VHDL_p           R= 100
X1  VHDL_p  0       Ctrl  0  IBIS_CCC_VHDL(Simple_test)
*
*============================================================================
>>> VHDL
--===========================================================================
library IEEE, MacroLib;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity IBIS_CCC_VHDL is
    port (terminal  Node_p,  Node_n,
                    Ctrl_p,  Ctrl_n   : electrical);
end entity IBIS_CCC_VHDL;

architecture Simple_test of IBIS_CCC_VHDL is

begin

   IBIS_C1 : entity MacroLib.IBIS_CCC(IDEAL)
      generic map ( V0    =>  0.5,
                    Scale =>  2.0e-12 )
      port map ( P  => Node_p,
                 N  => Node_n,
                 PS => Ctrl_p,
                 NS => Ctrl_n );

end architecture Simple_test;
--===========================================================================