
From owner-ibis  Tue Apr  4 11:02:35 2000
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From: "Lynne Green" <lgreen@HyperLynx.com>
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Subject: Any training available?
Date: Tue, 4 Apr 2000 10:48:06 -0700
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I am looking for training on IBIS model development.
Can anyone suggest suitable seminars?
Or presenters/instructors I might contact?
Thanks,
Lynne
From owner-ibis  Tue Apr  4 11:22:20 2000
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Lynne Green wrote:
> 
> I am looking for training on IBIS model development.
> Can anyone suggest suitable seminars?
> Or presenters/instructors I might contact?

From time to time Arpad goes around presenting a short
course through the University of Arizona.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Apr  4 12:13:02 2000
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From: "Fisher, Thomas" <tomfisher@ti.com>
To: lgreen@hyperlynx.com
Cc: ibis@eda.org
Subject: RE: Any training available?
Date: Tue, 4 Apr 2000 14:10:11 -0500 
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Or another option.............

JEDEC, IBIS and Intel are pleased to offer a training presentation on
IBIS modeling.  This even will be held in San Jose, California, at the 
Silicon Valley Convention Center on April 26, the day after the DRAM 
Futures Task Group meeting and JEDEC special session.  It will run 
from 8:00 AM until 12:00 noon.

This event is free of charge, thanks to Silicon Tech's offer to
cover the cost of the facility.  However, seating is limited to 250
people, and since we have no idea how many will take advantage of this
offer, we must ask that all companies interested in sending people to
this event send a request to:

    Bill Gervasi
    bilge@transmeta.com 

In this email, please indicate how many people you would like to send to
the event.  As confirmation, you will receive a response email from me
with directions to the facility.  If it is necessary to limit
attendance, I will also indicate how many people we can accept.  To
allow people to make airplane reservations, please note the following
dates:

    IBIS training request cutoff date:  Monday, April 10
    My response to your requests:  Tuesday, April 11

Note that this event is not required, nor does it imply an endorsement
of JEDEC.  This notice is offered only for informational purposes.

-----Original Message-----
From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
Sent: Tuesday, April 04, 2000 1:20 PM
To: lgreen@hyperlynx.com
Cc: ibis@eda.org
Subject: Re: Any training available?


Lynne Green wrote:
> 
> I am looking for training on IBIS model development.
> Can anyone suggest suitable seminars?
> Or presenters/instructors I might contact?

From time to time Arpad goes around presenting a short
course through the University of Arizona.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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<TITLE>RE: Any training available?</TITLE>
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<P><FONT SIZE=2>Or another option.............</FONT>
</P>

<P><FONT SIZE=2>JEDEC, IBIS and Intel are pleased to offer a training presentation on</FONT>
<BR><FONT SIZE=2>IBIS modeling.&nbsp; This even will be held in San Jose, California, at the </FONT>
<BR><FONT SIZE=2>Silicon Valley Convention Center on April 26, the day after the DRAM </FONT>
<BR><FONT SIZE=2>Futures Task Group meeting and JEDEC special session.&nbsp; It will run </FONT>
<BR><FONT SIZE=2>from 8:00 AM until 12:00 noon.</FONT>
</P>

<P><FONT SIZE=2>This event is free of charge, thanks to Silicon Tech's offer to</FONT>
<BR><FONT SIZE=2>cover the cost of the facility.&nbsp; However, seating is limited to 250</FONT>
<BR><FONT SIZE=2>people, and since we have no idea how many will take advantage of this</FONT>
<BR><FONT SIZE=2>offer, we must ask that all companies interested in sending people to</FONT>
<BR><FONT SIZE=2>this event send a request to:</FONT>
</P>

<P><FONT SIZE=2>&nbsp;&nbsp;&nbsp; Bill Gervasi</FONT>
<BR><FONT SIZE=2>&nbsp;&nbsp;&nbsp; bilge@transmeta.com </FONT>
</P>

<P><FONT SIZE=2>In this email, please indicate how many people you would like to send to</FONT>
<BR><FONT SIZE=2>the event.&nbsp; As confirmation, you will receive a response email from me</FONT>
<BR><FONT SIZE=2>with directions to the facility.&nbsp; If it is necessary to limit</FONT>
<BR><FONT SIZE=2>attendance, I will also indicate how many people we can accept.&nbsp; To</FONT>
<BR><FONT SIZE=2>allow people to make airplane reservations, please note the following</FONT>
<BR><FONT SIZE=2>dates:</FONT>
</P>

<P><FONT SIZE=2>&nbsp;&nbsp;&nbsp; IBIS training request cutoff date:&nbsp; Monday, April 10</FONT>
<BR><FONT SIZE=2>&nbsp;&nbsp;&nbsp; My response to your requests:&nbsp; Tuesday, April 11</FONT>
</P>

<P><FONT SIZE=2>Note that this event is not required, nor does it imply an endorsement</FONT>
<BR><FONT SIZE=2>of JEDEC.&nbsp; This notice is offered only for informational purposes.</FONT>
</P>

<P><FONT SIZE=2>-----Original Message-----</FONT>
<BR><FONT SIZE=2>From: D. C. Sessions [<A HREF="mailto:dc.sessions@vlsi.com">mailto:dc.sessions@vlsi.com</A>]</FONT>
<BR><FONT SIZE=2>Sent: Tuesday, April 04, 2000 1:20 PM</FONT>
<BR><FONT SIZE=2>To: lgreen@hyperlynx.com</FONT>
<BR><FONT SIZE=2>Cc: ibis@eda.org</FONT>
<BR><FONT SIZE=2>Subject: Re: Any training available?</FONT>
</P>
<BR>

<P><FONT SIZE=2>Lynne Green wrote:</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; I am looking for training on IBIS model development.</FONT>
<BR><FONT SIZE=2>&gt; Can anyone suggest suitable seminars?</FONT>
<BR><FONT SIZE=2>&gt; Or presenters/instructors I might contact?</FONT>
</P>

<P><FONT SIZE=2>From time to time Arpad goes around presenting a short</FONT>
<BR><FONT SIZE=2>course through the University of Arizona.</FONT>
</P>

<P><FONT SIZE=2>-- </FONT>
<BR><FONT SIZE=2>D. C. Sessions</FONT>
<BR><FONT SIZE=2>dc.sessions@vlsi.com</FONT>
</P>

</BODY>
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From owner-ibis  Thu Apr  6 10:22:16 2000
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From: guy@camarillo.viewlogic.com (Guy de Burgh)
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To: ibis@eda.org
Subject: EIA IBIS Summit Meeting Minutes (3/31/00)


DATE: 4/6/00

SUBJECT: 3/31/00 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2000 PARTICIPANTS LIST:
3Com                           Roy Leventhal
Agilent (EEsof, etc.)          Mark Chang
  Hewlett Packard              Paul Gregory
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Ballesteri
Avanti                         Nikolai Bannov
Cadence Design                 Mike LaBonte, Todd Westerhoff, Ian Dodd,
                               Donald Telian, Patrick Dos Santos*
Cisco Systems                  Syed Huq, Irfan Elahi, John Fisher
Compaq                         Bob Haller, Peter LaFlamme, Ron Bellomio,
                               Shafier Rahman, Doug Burns
Cypress                        (Rajesh Manapat)
EMC Corporation                (Fabrizio Zanella),
Fairchild Semiconductor        Craig Klem
H.A.S. Electronics             (Haruny Said)
HyperLynx (& Pads Software)    Matthew Flora, Kellee Crisafulli, Gene Garat,
                               John Angulo, Al Davis, Lynne Green
IBM                            Michael Cohen
Incases                        Werner Rissiek*
Innoveda (Viewlogic Systems)   Chris Rokusek, Guy de Burgh, Jun Tian,
                               Cary Mandel*, Brad Griffin*, (Jon Powell)
Intel Corporation              Stephen Peters, Arpad Muranyi, Will Hobbs,
                               Richard Mellitz
LSI Logic                      (Larry Barnes)
Mentor Graphics (& Veribest)   Bob Ross*, Tom Dagostino*, Malcolm Ash,
                               Kim Owen, Jean Oudionot*, Sherif Hammad*,
                               Hazam Hegazy*
Mitsubishi                     Shahab Ahmed
Molex Incorporated             Gus Panella
Motorola                       Ron Werner
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre, Tony Sinker
NEC                            (Hiroshi Matsumoto)
Nortel Networks                Steve Coe, Calvin Trowell, Hassan Ali
Philips Semiconductor          D.C. Sessions
  (& VLSI Technology)
Quantic EMC                    (Mike Ventham)
Siemens AG                     Bernhard Unger, Gerald Bannert*
SiQual                         Scott McMorrow, Wis Macomson
Texas Instruments              Stephen Nolan, Ramzi Ammar, Mac McCaughey,
                               Thomas Fisher*, Jean-Claude Perrin*,
                               Jean-Yves Oberle*
Time Domain Analysis Systems   Dima Smolyansky, Steven Corey
Via Technologies               (Weber Chuang)

OTHER PARTICIPANTS IN 2000:
Actel Corp.                    Silvia Montoya
Advansis                       Mikio Kiyono
Aerospatiale Matra CCR         Lionel Dreux*, Julien Boullie*
Alcatel (Lannion, Bell)        Daniel Peron*, Steven Criel*
Brocade Communications         Robert Badal
EIA                            Cecilia Fleming
Fraunhofer Instutute           Michael Kurten*
Jet Propulsion Lab             John Treichlew
Rockwell Collins               Ron Hau
Signals & Systems Engineering  Tom Hawkins
ST Micorelectronics            Fabrice Boissiere*, Pierre Saintot*
Sun Microsystems               Victor Chang
Thomson-CSF                    Savenrio Lerose*, Pascal Vaslin*, Thierry Zak*,
                               Sylvie Lasserre*
Transfer                       Hans Klos*, Wilco Hamhuis*
Xilinx, Inc.                   Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  April 14, 2000      (916) 356-9200   8-97978          5851557

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS
The European IBIS Summit Meeting was held in Paris, France the day after the
Design Automation and Testing in Europe conference (DATE 2000) at the
Concorde La Fayette Hotel.  Cadence Design, Incases Engineering, Innoveda
(formerly Viewlogic Systems), Mentor Graphics served as co-sponsors.

About 26 people representing 12 organizations participated.  Bob Ross welcomed
the participants and noted that questions and interactive discussion was
encouraged.  Everybody introduced himself.  Semiconductor vendors, EDA
vendors and users (along with an individual from a research institute) were
all represented.  (Also, thanks to Karine Loudet and Francoise Lindecker of
Mentor Graphics for producing the posters and handling the administrative and
registration details.)

All of the presentations and meeting documentation will be uploaded at

  http://www.eda.org/pub/ibis/summits/mar00/

The notes below give some off the content and discussion.

SIEMENS ICN I/O MODEL SPECIFICATION
(Terms of Delivery for I/O Models of Digital Integrated Circuits
V50004-Y1-T210-*-7625 Revision Feb.08.2000)
Gerald Bannert, Siemens AG
Gerald Bannert passed around the above draft specification.  It includes
material presented at previous European IBIS Summit meetings.  Siemens prefers
IBIS models. However, Gerald finds that IBIS Models from manufacturers are
insufficient for Siemens needs for several reasons:

  They use older than Version 3.2 revisions of IBIS.
  Useful options are missing, and model quality is not good.
  Technical IBIS content and parameter definition in IBIS is insufficient,
    incorrect, or difficult to understand.
  Some additional parameters are needed for the internal Logical Design
    Rule Checker (LDRC) tool.

The specification contents are:

  Part 1: Quality, references, data consistency, transaction complete.
  Part 2: Technical supplement/changes to IBIS Version 3.2
  Part 3: Additional parameter requests.

The specification is being reviewed internally and is also being distributed
to major semiconductor vendors.  Additions to the document are expected for
improved accuracy, EMI, HF, and SSO.  Vendors supplying the added information
of Part 3 may become preferred vendors.

Gerald then gave an overview outline of the content (summarized here):

  Superordinate, general and technical requirements for delivery (16 pages)
    General introductory and scope material
    Guarantee, model changes (MCN) validity for models tracking device
      changes
    General requirements for IBIS models - application, data consistency,
      availability and definition of typ, min, and max parameters for
      process, Tj, and Vcc
    Requirements for other formats (underway)
    Plus parameter requirements

  Annex 1 (27 pages)
    Technical definitions (e.g., overshoot, Vdiff)
    Limits of interest
    Measurement and simulation conditions (e.g., SSO, Tj, loads)
    IBIS points of table entries
    Siemens ICN options

  Annex 2 (18 pages)
    File structure and relationship of .ibs and .sie (for Siemens)
    Technical data definition (e.g., fail safe, Vsource, slew rate, I/O type
    Functional pin mapping (e.g., clock, data)

Gerald discussed a number of these points.

The IBIS Version 3.2 specification only gives general guidelines for entering
typ, min, and max parameters.  The Siemens document gives more detailed
definitions.  The typical model should have typical process conditions within
+/- 0.5 sigma.  The standard JEDEC voltages (12, 5, 3.3, 2.5, 1.8, 1.5, and
1.3) need to be specified.  The typical junction temperature condition should
correspond to about 40 degrees C ambient.  The min and max process parameters
should be approximately the 2.3 sigma points.  The voltages should be +/- 5
percent.  The junctions temperature range should be 0 degrees C to 110
degrees C.  Some existing IBIS models from semiconductor vendors have too
large of a range to be useful in real designs.

Gerald elaborated on a needed Vdiff_max subparameter for differential pins
and how they relate to S_overshoot and D_overshoot entries.  Furthermore,
he illustrated typ, min, and maximum thresholds and their relationship to a
Vth threshold voltage.  Bob Ross commented later that pending BIRD62.6 may
cover much, if not all of these details.

The S_overshoot and D_overshoot parameters are defined for currents that
are transformed into voltages for a variety of clamping conditions that
are appropriate for the technology.  Clamping conditions range from no clamp,
leakage currents, regular clamp and zener clamp.

Some recommendations are provided for assuring that table data points are
spaced for maximum accuracy.  The changes in slow need to be with 3 to 4
percent of the previous slope.

Load conditions for [Rising Waveform] and [Falling Waveform] are given.
Also, if the overshoot exceeds 10 percent, [Driver Schedule] is recommended.

A number of topics are not covered in this draft, but are expected to be
included in the future.  The include [Driver Schedule], [TTgnd], [TTpower],
terminations and passive series elements, [Series MOSFET], [Submodel]s,
.pkg and .ebd formats.

Gerald introduced additional parameters needed for the internal Siemens tool
called Logical Design Rule Checking (LDRC).  This tool performs design checks
for connectivity, reasonableness, power, etc. that are normally not included
in EDA tools.  For example, the keyword [SI_add_pin_info] documents more
information for each pin:

  clock (clock, latch, asynchronous Set/Reset inputs)
  data (data/address inputs, synchronous Set/Reset inputs)
  logic (buffer and other combinational inputs)
  static (enable inputs, control inputs)   Vbb for ECL)
  vsource (built in voltage source such as
  analog (crystal, R/Cext, OpAmp inputs and outputs)
  pwr_gnd (Vcc, Gnd, Vee)
  dnc (physically exiting, but not connected
  nnc (pin does not exist)
  unknown (assignment to one of the above not possible)
  output (all outputs)

Gerald discussed the [SI_add_cell_information] keyword.  It would give
ioh_max, ioh_min, bushold min and max currents, technology, and leakage
current limits.  Furthermore it would define input slew rate limits.  Gerald
answered in response to a question from Tom Dagostino that the input slew rate
also covered reflected wave switching.

Technology information relates to actual driver application such as bus
driver, board and back plane application, shortest cable connections.  Also
hot insertion rules are indicated, if allowed.  Also, EOS robustness is of
concern.

The [SI_analog_model] keyword gives c_subst, r_subst_ and v_substr values.

Gerald noted that Siemens simulates 100 percent of the boards and 100 percent
of the nets.  During and after the presentation, number of these items were
discussed.  Werner Rissiek commented that the additions could be pushed
through the IBIS committee.

TIPS AND TRICKS FOR CREATING IBIS MODELS
Cary Mandel, Innoveda (formerly Viewlogic Systems)
Cary Mandel commented that Jon Powell of Innoveda Consulting Services wrote
this.  The material was based on experiences producing IBIS models from
HSPICE and testing them on an Innoveda simulator.  The overall test setup
is part of an internal Virtual Modeling Lab (VML) which allows programming
of extraction and test conditions.

Cary showed the preferred 50 ohms to ground and 50 ohms to Vcc loads for
extracting V-T tables.  Package parasitics need to be removed.  Cary noted
that Spice options need to be set for proper DC convergence, and that the
time response needs to be long enough to reach the final value.  Sometimes
the IBIS 100 point limit makes it difficult to have high accuracy for typ,
min and max columns simultaneously. Cary also noted that the input signal
should be fast enough so that does not slow down the output response.

To do the quality assurance (QA) comparisons, a mid point voltage needs to
be selected to synchronize the rising and falling edges.  Then results can
be overlayed and compared.  To further test the model, comparisons using
other test conditions such as 50 pF to ground, a transmission line load, and a
full package test case could be added.

Cary listed some common problems:

  Simulation time does not allow waveform to reach full high or low.
  Spice model does not behave well at the corners.
  Spice models need special control options to converge.
  Spice diode models create unlikely amounts of current.
  QA simulation does not reproduce some Spice features.

The difficulties with IBIS are:

  100 point limit can create difficulties in fitting large typ, min, and
    max I-V and V-T tables.  Careful linearization may be needed.
  Typ, Min and Max may not describe full range of corners desired.
  The LC package model may be insufficient.  The IBIS Version 3.2 T-line
    model is needed in many cases including RAMBUS modeling.
  The transition time (ramp) is not very useful for rise time controlled
    and many high speed advanced drivers.

Cary showed an example of a QA simulation where a model with V-T waveforms
overlayed the source data compared to the one based on ramp data with a
significant time mismatch.

Tom Dagostino commented on his experiences measuring diode currents and
suggested a limit in the order of 100 mA to 1 A.  Default generic diodes
were suggested when the Spice model contains unrealistic "ideal diodes".

IBIS ACCURACY STUDY
Sherif Hammad, Mentor Graphics
Sherif Hammad introduced some metrics for comparing model simulation results
with initial time waveform extractions.  The first two dealt with delay
comparison and alignment and the last three dealt with accuracy comparisons:

  CCPV - Cross-Correlation Peak Value
  CCTO - Cross-Correlation Time Offset

  AAD -  Average Absolute Difference in V
  AAD (%) - Average Absolute Difference in percentage

  COM (%) - Curve Overlay Metric (from the Accuracy Specification)

Then Sherif illustrated the metrics with IBIS Models constructed using four
waveforms (50 ohms to ground and Vcc), two waveforms (50 ohms to ground for
rising and 50 ohms to Vcc for falling), and then ramp specification for the
same conditions.

The illustrations and metrics showed nearly perfect correlation (99.8%) for
the four waveform cases, and worse correlation for the two waveform (96.0% to
98.2%) and ramp (97.5%) cases.  The delay metrics showed nearly zero shift
for the best four waveform cases, and up to 100 picoseconds for some other
cases.

Then Sherif illustrated testing the robustness of the four waveform based
model using a 50 ohm to Vcc/2 load (99.5%) and 30 ohm to ground load (99.2%).
The delay shift was up to 10 picoseconds.  This was just a sampling of tests.

Lionel Dreux commented that he needed to match IBIS Model loads to the actual
net loads for accuracy.  After some clarification discussion, we determined
that the best model was still based on resistive loads (not timing) loads
and that Sherif's results showed good accuracy.  However, Fabrice Boissiere
and others commented that different technologies might require different
loads consistent with their typical operating conditions (for example, GTL
uses 25 ohms to 1.0 V).

TC93WG6 EMC/EMI IC MODEL STANDARDIZATION REPORT
Jean-Claude Perrin & Jean-Yves Oberle, Texas Instruments
Jean-Claude Perrin, chair of IEC TC93WG6 introduced the EMC/EMI simulation
needs:

  IC manufacturers need to take into account EMC constraints in IC design
  and need to simulate EMC behavior and contribution

  PCB manufacturers need to comply with EMC requirements and simulate EMC
  phenomena on PCBs.

Jean-Claude summarized the history of the committee.  It began work in 1994,
introduced IEC 93/67 NP in June 1997, held an international task force
meeting in 1998, and held a recent experts meeting on March 30, 2000.

The main conclusion is that IBIS Models can be enhanced to do top-level
EMI simulation.  IBIS does not take into account:

  I/O noise due to internal activity
  Fast transitions of current through power supplies
  Direct electromagnetic emission from ICs

At this time the task group is concerned with emission and not susceptibility.
A model for behavioral simulation was shown.  It consists of:

  Zp and Ip impedance current and noise generator across the Vdd/Vss supplies,
  Sa and Ga equivalent noise generator/antenna responsible for external hf
    noise emission,
  Hx(F) transfer functions between internal generator and other input/output
    pins.

The active blocks are:

  Core power supplies
  Peripheral (I/O) power supplies
  Clock signals activity
  Package

A draft proposal for IBIS format extension consists of these new keywords:

  [Core Current]    Instantaneous current consumption
  [Pad Current]     Instantaneous current consumption
  [Die Size]        Width and length of the die
  [Clock Frequency] Clock frequencies of the device
  [Pad Clock]       List of pads connected to one of the clocks

The proposal is still in draft form and has not been made available outside
of the committee.  Jean-Claude outlined some of the remaining steps.  IEC
and the IBIS Open Forum would look at the document and assist in model
validation and vote on the document.

The document needs to show:

  Model definition
  Tem cell current measurement
  IBIS EMC specific files

Jean-Claude proposes that EDA vendors assist in validating the model adapting
their tools to do simulation of power supply and clock signals.

Jean-Yves Oberle showed measurements of the electric field radiated by an IC
for two orientations shifted 90 degrees apart.  Jean-Yves compared the
measurements to simulation results.  The shapes showed excellent agreement,
but noted that measurement setup variables are hard to control, and the
simulation used approximations.  Jean-Yves highlighted areas where the
differences were 15 dB to 25 dB, still not bad for this type of comparison.

A number of technical question and suggestions were discussed.  Jean-Yves
explained that the simulation was performed using Maxwell equations and
Spice.  Werner Rissiek liked the model.  Jean-Claude noted that a different
group, IEC TC47 is working on measurement standards.  Tom Dagostino asked
how long the simulation took and suggested a simpler test case, such as a
wire, when the response was about one day.  Based on his experiences, Lionel
Dreux suggested that closer simulations results might be achieved by also
considering magnetic sources.  This type of simulation needs to include the
decoupling network on PCBs.

Bob Ross commented that the document needs to be released for public
distribution in order for it to proceed.  Jean-Claude intends to work on the
refinements and then have it made available to the IBIS Open Forum.  Later
in the meeting Bob stated that the draft document was structured as a
Section 10 addition to IBIS Version 3.2.  This might be a good way to go
since IBIS Version 3.2 is stable.  (Bob had considered having this as a
separate stand-alone standard to make it easier to ratify.)

IBIS FUTURE ACTIVITIES
Bob Ross, Mentor Graphics
Bob Ross moved his presentation to the time slot before lunch.  Bob gave an
overview of the meeting today.  It deals with current and future specification
requirements and clarification, modeling tips and accuracy studies.  It also
deals with potential future activities including the EMI/EMC modeling,
behavioral receiver modeling, and the current IBIS development activities.

Bob gave a status update showing that IBIS Version 3.2 is now an official
ANSI/EIA-656A standard and is approved as IEC 62014-1 and is awaiting
publication.  The ibischk3.2.5 parser has been released, but some bugs have
been discovered and need to be fixed.  The IBIS Users group has released the
IBIS Connector Specification to the IBIS Open Forum Committee and also may
be resuming work on the Accuracy Specification.  The Accuracy Specification
is now targeted to be a handbook.  The IBIS Open Forum chose not to produce
a Spice to IBIS for IBIS Version 3.2 since commercial vendors are also
interested in doing this.

The main activities of the IBIS Open Forum are

  The Connector Specification
  IBIS Version 4.0
  IBIS-X for the future

The IBIS Open Forum continues to track other activities:

  TC93WG6 EMC/EMI
  EIAJ IMIC Specification
  JEDEC activities

Bob summarized some technical aspects of the Connector Specification and
noted that after a syntax review, a formal review leading to a ratification
vote will be conducted.  The Specification is expected to be ratified around
mid 2000 as a Version 1.0 document and then a syntax checker and parser
development project is expected to be initiated.

The IBIS Version 4.0 update is driven by some immediate needs by the JEDEC
for DDR memories and current SSTL-3 technologies.  BIRD62.6 is expected to
be ratified for better input specification detail.  Dr. Bernhard Unger's
solution for simultaneous switching noise (SSN) modeling is of great
interest.  Other open BIRDs and specification suggestions will be examined.
Perhaps a few other ideas such as AVC modeling might be proposed and
considered.  This upgrade is expected to be ratified sometime during 2000.

The IBIS-X activity is really a name for a group of possible proposals that
relate to longer term needs for IBIS.  Many needs have been reported on the
IBIS reflector and at several of the recent IBIS Summit Meetings.  The latest
meeting held January 31, 2000 contained several presentations that covered
IBIS-X, "BIRDxxx", macro language, application programmable interface and
other ideas.  Bob noted from one presentation that there was interest in
scalability (one node to many nodes), flexible representation (current IBIS
elements, controlled voltage and current sources, S-parameters, etc.), and
nodal representation similar to Spice.  Bob also reported that the IBIS-X
proposal might be similar and support much of IBIS.  It might also support
functional port definitions and also some Spice-like nodal constructs.  This
would allow faster production of models as technological advances occur.
(Later, Bob noted that Werner Rissiek had suggested that IBIS-X may be moving
towards becoming a modeling language (such as Spice) as opposed to a format
for model data.  Bob reported that several people planned to meet in Oregon
on Thursday, March 30, 2000 to start formulating a consensus proposal.  Bob
expected that while we may see the proposal shortly, we may take a year or
two for actual review and ratification as a separate standard.

BEHAVIORAL RECEIVER MODELING
Patrick Dos Santos, Cadence Design
After a delicious buffet lunch hosted by Cadence Design, Patrick Dos Santos
indicated that the Behavioral Receiver Modeling presentation was authored by
Donald Telian and had also been given at the January 31, 2000 IBIS Summit
Meeting.

Patrick showed the evolution of design methodology:

  Use terminations (mid-1980s)
  Driver scaling and tuning (early 1990s leading to IBIS and to tools for
    topology optimization)
  Now - more detailed receiver modeling

Receiver modeling allows optimization:

  What switching functions are needed?
  What type of pulses are to be rejected?
  What sort of propagation characteristics will work?
  What voltages should this all operate at?

The best approach is to use a nodal behavioral description because it allows
modeling of a receiver's characteristics and also is easily adaptable to
arbitrary behaviors.  Patrick noted that nodal based receivers can be derived
from measurement or simulation.

The behavioral receiver contains these blocks:

  #1: Low Pas filter - reject certain pulse spikes
  #2: Switching Function - receivers basic transfer function
  #5: Intrinsic Delay - delay for fasted edge
  #3: Edge Rate Detection - derivative of input signal affects delay
  #4: Delay Adder - dynamically adjusts circuit delay based on #3

Its implementation needs these features:

  Nodal language
  G (VCC) and E (VCVS) sources (PWL, Equation driven with derivatives,
    even driven and time-controlled as well)
  Real-time adaptive delay line
  Subcircuiting nesting and random node printing

Based on 242 difficult test cases, the simulation results showed an average
difference of 19 pS (standard deviation of 14 pS).  Simulation times were
slightly slower, but still in the same order of magnitude as Spice
simulations.  Many of the models had additional proprietary elements, slowing
the simulation.

Gerald Bannert asked whether input impedance details can be accurately
modeled.  Patrick responded yes since input elements can be added to any
level of detail using standard nodal syntax.  Also differential inputs and
clamping diodes can be modeled.

Lionel Dreux commented that the approach might be extended for field coupling
to a PCB.  It might be used for susceptibility.  Upon questioning, Patrick
stated that non-linear effects are included.

Werner Rissiek commented that the IBIS still has its place since it is
scalable to any accuracy needed.  For example, the IBIS model can be as
simple or detailed as appropriate for the analysis.  Patrick stated that the
behavioral receiver model could be scalable.

CLOSE OF MEETING
Bob Ross provided some more detail on the pending Connector Specification
regarding using cascaded sections to configure the connector for different
sockets and different board thicknesses (for the edge card side of an edge
card connector).

Bob summarized that along with current activities dealing with the Connector
Specification, IBIS Version 4.0 definition and IBIS-X definition, the IBIS
Open Forum could also be dealing with more IBIS Version 3.2 clarifications
based on the Siemens requirements, possible electronic data sheet requirements
needed by Siemens, and possibly an EMI Section 10 addition to IBIS
Version 3.2.

Bob again thanked the participants for their contributions and the
co-sponsors.  Several participants commented on the amount of interesting
material presented at this meeting and supported IBIS as an appropriate level
for the potential extensions.

NEXT MEETING:
The next teleconference meeting will be on Friday, April 14, 2000 from
8:00 AM to 10:00 AM.  BIRD62.6 will be scheduled for voting.

==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jpowell@innoveda.com
            Senior Scientist, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Signal Integrity Engineer, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            114715 N.E. 95th Street
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org/eig/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================

From owner-ibis  Fri Apr  7 02:19:42 2000
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subscribe

From owner-ibis  Fri Apr  7 11:34:50 2000
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                     IBIS Open Forum Meeting Agenda 
                               for 4/14/00

                 Bridge Number    Reservation #   Passcode
                 (916) 356-9200   8-97978         5851557

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Ross/Fleming
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Powell, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Ross/Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
          for Integrated Circuits (IMIC)                     Raghuram/Ross
     - IEC PWI 93-1 Models of Integrated Circuits for EMI 
       Behavioral Simulation (formerly designated as
       IEC 93/67/NP IBIS and EMC Simulation)                 Perrin
     - JEDEC JC-16 Modeling and Testing                      Sessions
    
     DATE2000 IBIS Summit Feedback                           Ross

     DAC2000 IBIS Summit Meeting Planning                    Ross

     Accuracy Handbook                                       Ross

     Cookbook Status                                         Peters

     IBIS Model Review Committee                             Flora

     New Administrative Issues                               All

8:45 Technical Discussion (some topics may be deferred)

     BIRD62.6 - Enhanced Chararcterization of Receiver       Peters
              Thresholds (Vote)

     BIRD66 - [Model Spec] Vref Addition                     McMorrow/Ross

     Connector Proposal Review (Continued)              Panella/Chrisafulli

     ibischk3 Bug Tracking                                   Ross
     - BUG34 - No Error Reported for Missing V/I Tables      Flora
             in Output Buffers
     - Repeated Voltage
     - 8.3 Version 2.1 Error
     - Series element does not work with I/O models

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters

     BIRD61.1 - Enhanced Characterization of Receivers       Peters

     BIRD64.1 - Package Model Selector                       Muranyi

     BIRD65 - C_comp Refinements                             Muranyi

     New Technologies                                        Cohen
     AVC                                                     Nolan

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off
From owner-ibis  Wed Apr 12 09:41:32 2000
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From: "Le, Dat (dle)" <dle@sequent.com>
To: "'Fisher, Thomas'" <tomfisher@ti.com>, lgreen@hyperlynx.com
Cc: ibis@eda.org
Subject: RE: Any training available?
Date: Wed, 12 Apr 2000 09:38:47 -0700
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I have a schedule conflict but would be interested to receive the
presentation document.

Thanks in advance,
Dat Le
dtle@us.ibm.com


> -----Original Message-----
> From:	Fisher, Thomas [SMTP:tomfisher@ti.com]
> Sent:	Tuesday, April 04, 2000 12:10 PM
> To:	lgreen@hyperlynx.com
> Cc:	ibis@eda.org
> Subject:	RE: Any training available?
> 
> Or another option............. 
> 
> JEDEC, IBIS and Intel are pleased to offer a training presentation on 
> IBIS modeling.  This even will be held in San Jose, California, at the 
> Silicon Valley Convention Center on April 26, the day after the DRAM 
> Futures Task Group meeting and JEDEC special session.  It will run 
> from 8:00 AM until 12:00 noon. 
> 
> This event is free of charge, thanks to Silicon Tech's offer to 
> cover the cost of the facility.  However, seating is limited to 250 
> people, and since we have no idea how many will take advantage of this 
> offer, we must ask that all companies interested in sending people to 
> this event send a request to: 
> 
>     Bill Gervasi 
>     bilge@transmeta.com 
> 
> In this email, please indicate how many people you would like to send to 
> the event.  As confirmation, you will receive a response email from me 
> with directions to the facility.  If it is necessary to limit 
> attendance, I will also indicate how many people we can accept.  To 
> allow people to make airplane reservations, please note the following 
> dates: 
> 
>     IBIS training request cutoff date:  Monday, April 10 
>     My response to your requests:  Tuesday, April 11 
> 
> Note that this event is not required, nor does it imply an endorsement 
> of JEDEC.  This notice is offered only for informational purposes. 
> 
> -----Original Message----- 
> From: D. C. Sessions [ <mailto:dc.sessions@vlsi.com>] 
> Sent: Tuesday, April 04, 2000 1:20 PM 
> To: lgreen@hyperlynx.com 
> Cc: ibis@eda.org 
> Subject: Re: Any training available? 
> 
> 
> Lynne Green wrote: 
> > 
> > I am looking for training on IBIS model development. 
> > Can anyone suggest suitable seminars? 
> > Or presenters/instructors I might contact? 
> 
> From time to time Arpad goes around presenting a short 
> course through the University of Arizona. 
> 
> -- 
> D. C. Sessions 
> dc.sessions@vlsi.com 
> 
From owner-ibis  Wed Apr 12 10:42:53 2000
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From: Bob Ross <bob_ross@mentorg.com>
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Dat:

The training material will be uploaded when it
is available at:

  http://www.eda.org/pub/ibis/training/

for public distribution.

Bob Ross
Mentor Graphics


"Le, Dat (dle)" wrote:
> 
> I have a schedule conflict but would be interested to receive the
> presentation document.
> 
> Thanks in advance,
> Dat Le
> dtle@us.ibm.com
> 
> > -----Original Message-----
> > From: Fisher, Thomas [SMTP:tomfisher@ti.com]
> > Sent: Tuesday, April 04, 2000 12:10 PM
> > To:   lgreen@hyperlynx.com
> > Cc:   ibis@eda.org
> > Subject:      RE: Any training available?
> >
> > Or another option.............
> >
> > JEDEC, IBIS and Intel are pleased to offer a training presentation on
> > IBIS modeling.  This even will be held in San Jose, California, at the
> > Silicon Valley Convention Center on April 26, the day after the DRAM
> > Futures Task Group meeting and JEDEC special session.  It will run
> > from 8:00 AM until 12:00 noon.
> >
From owner-ibis  Thu Apr 13 14:00:57 2000
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From: Bob Ross <bob_ross@mentorg.com>
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To All:

Discussion on BUG34 on ibischk3 is planned for the April 14, 2000
IBIS Meeting.  It is given below for reference.

Bob Ross
Mentor Graphics

******************************************************************************
********************* IBIS GOLDEN PARSER BUG REPORT FORM *********************
******************************************************************************

INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to ibischk-bug@vhdl.org.

A list of reported bugs will be maintained on vhdl.org.

******************************************************************************

PARSER VERSION NUMBER:
    Found in IBISCHK3 V3.2.1 built for DOS.  Confirmed in IBIS_CHK2 V2.1.17
    for DOS.

PLATFORM (SPARC, HP700, PC, etc.):
    PC

OS AND VERSION:
    Windows NT Server 4.0 (Build 1381: Service Pack 4)

REPORTED BY:
    Matthew Flora
    HyperLynx
    (425) 869-2320
    mbflora@hyperlynx.com

DATE:
    12 Jan 1999
    27 Oct 1999 - Amended

DESCRIPTION OF BUG:
    The parser does not report an error if an output buffer has no V/I tables
    (and therefore is not an output).

    Perhaps the parser should test for the presence of certain V/I tables for
    other Model_types as well.

  AMENDMENT:
    After an IBIS Open Forum Teleconference discussion, it was decided that a
    warning should be given rather than an error.  Furthermore, the absence of
    clamp tables would not be reported.

    The wording I propose is lengthy, but it meets the need for an
    understandable description of the problem and a remedy.

    The warning given to the user should be dependant upon the Model_type of
    the buffer:

    Input, Input_ECL, Terminator, Series, Series_switch:
        No warning given.

    Output, Output_ECL, I/O, I/O_ECL, 3-state, and 3-state_ECL; [Pullup] table
    missing:
        "WARNING - Model 'XXX' does not contain a description of the buffer's
                   DC drive characteristics for the buffer's high state (no
                   [Pullup] table).  The model is not declared to be an open
                   drain buffer.  Perhaps it should be.  Alternatively, a
                   [Pullup] table containing all zero currents could be
                   added."

    Output, Output_ECL, I/O, I/O_ECL, 3-state, and 3-state_ECL; [Pulldown]
    table missing:
        "WARNING - Model 'XXX' does not contain a description of the buffer's
                   DC drive characteristics for the buffer's low state (no
                   [Pulldown] table).  The model is not declared to be an open
                   source buffer.  Perhaps it should be.  Alternatively, a
                   [Pulldown] table containing all zero currents could be
                   added."

    Output, Output_ECL, I/O, I/O_ECL, 3-state, and 3-state_ECL; Both [Pullup]
    and [Pulldown] tables missing:
        "WARNING - Model 'XXX' does not contain a description of the buffer's
                   DC drive characteristics for the buffer's high and low
                   state (no [Pullup] nor [Pulldown] table).  Therefore, the
                   model is of little use as an output.  If this is not a
                   mistake, consider adding [Pullup] and [Pulldown] tables
                   containing all zero currents."


    Open_drain, Open_sink, I/O_open_drain, and I/O_open_sink; [Pulldown] table
    missing:
        "WARNING - Model 'XXX' does not contain a description of the buffer's
                   DC drive characteristics for the buffer's low state (no
                   [Pulldown] table).  Therefore, the model is of little use
                   as an output.  If this is not a mistake, consider adding a
                   [Pulldown] table containing all zero currents."

    Open_source and I/O_open_source; [Pullup] table missing:
        "WARNING - Model 'XXX' does not contain a description of the buffer's
                   DC drive characteristics for the buffer's high state (no
                   [Pullup] table).  Therefore, the model is of little use
                   as an output.  If this is not a mistake, consider adding a
                   [Pullup] table containing all zero currents."





INSERT IBIS FILE DEMONSTRATING THE BUG:
    [IBIS Ver]        3.1 | or 2.1 or 1.1
    [File Name]       notables.ibs
    [File Rev]        0.1
    |
    |***************************************************************
    |
    [Component]      TEST
    [Manufacturer]   Test File
    [Package]
    | variable      typ             min             max
    R_pkg           0.0m            NA              NA
    L_pkg           0.0nH           NA              NA
    C_pkg           0.0pF           NA              NA
    |
    |***************************************************************
    |
    [Pin]           signal_name     model_name
    1               One_Pin         NC
    |
    |
    |***************************************************************
    |
    [Model]     no_tables
    Model_type  Output

    |                         typ          min          max
    C_comp                    2.6000pF     NA           NA
    [Voltage Range]           3.3000V      NA           NA

    [Ramp]
    |          typ                     min                     max
    dV/dt_r    1/1ns                   NA                      NA
    dV/dt_f    1/1ns                   NA                      NA

    [End]



******************************************************************************
******************** BELOW FOR ADMINISTRATION AND TRACKING *******************
******************************************************************************

BUG NUMBER:  34

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]   ANNOYING

PRIORITY: [HIGH, MEDIUM, LOW]                                LOW

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]              OPEN

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX: At the January 15, 1999 IBIS Meeting, we deferred fixing
                  BUG34 since we needed more time to decide how to fix it.
                  BUG34 proposals for Warning messages were issued by
                  Matthew Flora October 29, 1999 per an action item.


******************************************************************************
******************************************************************************
From owner-ibis  Tue Apr 18 08:59:49 2000
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Date: Tue, 18 Apr 2000 09:00:09 -0700
From: guy@camarillo.viewlogic.com (Guy de Burgh)
Message-Id: <200004181600.JAA14474@f22.viewlogic.com>
To: ibis@eda.org
Subject: EIA IBIS Summit Meeting Minutes (4/14/00)


DATE: 4/18/00

SUBJECT: 4/14/00 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2000 PARTICIPANTS LIST:
3Com                           Roy Leventhal
Agilent (EEsof, etc.)          Mark Chang
  Hewlett Packard              Paul Gregory
Applied Simulation Technology  Raj Raghuram*, Norio Matsui, Fred Ballesteri
Avanti                         Nikolai Bannov
Cadence Design                 Mike LaBonte, Todd Westerhoff, Ian Dodd*,
                               Donald Telian, Patrick Dos Santos
Cisco Systems                  Syed Huq, Irfan Elahi, John Fisher
Compaq                         [Bob Haller], Peter LaFlamme, Ron Bellomio,
                               Shafier Rahman, Doug Burns
Cypress                        (Rajesh Manapat)
EMC Corporation                (Fabrizio Zanella),
Fairchild Semiconductor        Craig Klem
H.A.S. Electronics             (Haruny Said)
HyperLynx (& Pads Software)    Matthew Flora*, Kellee Crisafulli, Gene Garat,
                               John Angulo, Al Davis, Lynne Green
IBM                            Michael Cohen*, Greg Edlund*
Incases                        Werner Rissiek
Innoveda (Viewlogic Systems)   Chris Rokusek, Guy de Burgh*, Jun Tian,
                               Cary Mandel, Brad Griffin, (Jon Powell)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs,
                               Richard Mellitz
LSI Logic                      (Larry Barnes)
Mentor Graphics (& Veribest)   Bob Ross*, Tom Dagostino, Malcolm Ash,
                               Kim Owen, Jean Oudionot, Sherif Hammad,
                               Hazam Hegazy, Weston Beal*
Mitsubishi                     Shahab Ahmed
Molex Incorporated             Gus Panella
Motorola                       Ron Werner*
National Semiconductor         Milt Schwartz*
North East Systems Associates  Edward Sayre, Tony Sinker
NEC                            (Hiroshi Matsumoto)
Nortel Networks                Steve Coe, Calvin Trowell*, Hassan Ali
Philips Semiconductor          D.C. Sessions
  (& VLSI Technology)
Quantic EMC                    (Mike Ventham)
Siemens AG                     Bernhard Unger, Gerald Bannert
SiQual                         Scott McMorrow, Wis Macomson
Texas Instruments              Stephen Nolan, Ramzi Ammar, Mac McCaughey,
                               Thomas Fisher, Jean-Claude Perrin*,
                               Jean-Yves Oberle
Time Domain Analysis Systems   Dima Smolyansky, Steven Corey
Via Technologies               (Weber Chuang)

OTHER PARTICIPANTS IN 2000:
Actel Corp.                    Silvia Montoya
Advansis                       Mikio Kiyono
Aerospatiale Matra CCR         Lionel Dreux, Julien Boullie
Alcatel (Lannion, Bell)        Daniel Peron, Steven Criel
Brocade Communications         Robert Badal
EIA                            Cecilia Fleming*
Fraunhofer Institute           Michael Kurten
Jet Propulsion Lab             John Treichlew
Rockwell Collins               Ron Hau
Signals & Systems Engineering  Tom Hawkins
ST Micorelectronics            Fabrice Boissiere, Pierre Saintot
Sun Microsystems               Victor Chang
Thomson-CSF                    Savenrio Lerose, Pascal Vaslin, Thierry Zak,
                               Sylvie Lasserre
Transfer                       Hans Klos, Wilco Hamhuis
Xilinx, Inc.                   Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  May 5 , 2000       (916) 356-9200   3-373073          1535639
  May 26, 2000       (916) 356-9200   3-373074          77923642
  June 8, 2000 - DAC 2000 IBIS Summit Meeting (No Bridge)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Weston Beal attended from Mentor Graphics, and Greg Edlund called in from
IBM.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross reported that we have 27 Members to date this year.  Cecilia Fleming
and Bob are checking or following up on the payment status of some others.


REVIEW OF MINUTES AND AR'S
The March 17, 2000 and March 31, 2000 IBIS Minutes were approved.

The AR's will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Bob Ross reported that Bob Haller authored "The Nuts and Bolts of Signal-
Integrity Analysis" in the March 16, 2000 issue of EDN, pp. 61-78, in which
IBIS is mentioned in several locations.  The article is also available at:

  http://www.ednmag.com/ednmag/reg/2000/03162000/06ms603.htm

Bob reported that in response to the SI reflector discussion regarding general
FAQ's on signal integrity, a High Speed Digital Design Topics page now has
a "Using IBIS Models" link with general information and other links:

  http://www.scs.ch/~andrew/hsdd/hsdd.html

The Topic Coordinator is Kim Helliwell, and Bob and Abe Riazi are Topic
Peers.  Comments and assistance in developing this further are welcome.

Bob also reported that the participants list has been updated with the
Innoveda change from Viewlogic and more information from SiQual, and
upcoming events have been updated.

The Poster page also has been updated with Innoveda and SiQual logos.

Bob also noted that the EIA web site will change, but the existing address
will be retained as an alias.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross mentioned that more Motorola IBIS models can be found by searching
for IBIS.  This probably works for several other semiconductor vendors as
well.


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 3.2) - Cecilia Fleming reported no further
information regarding the progress of this document.  IEC approved the
document in December 1999, and it is awaiting publication.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
(IMIC) - Bob Ross reported that Dr. Hideki Fukuda has been elected Leader,
Takeshi Watenabe from NEC, Vice Leader.  The group has been following the
IBIS futures developments and is interested in the nodal approaches based on
the fact that the Silicon Vendors have Spice models.  The group wants to
continue to work with the IBIS Open Forum.  Bob forwarded a letter to the
IBIS Futures committee.

- IEC PWI 93-1 Models of Integrated Circuits for EMI Behavioral Simulation
(formerly designated as IEC 93/67/NP IBIS and EMC Simulation) - Jean-Claude
Perrin reported that he plans to revise the document by the end of May 2000
and then make it available to the IBIS committee.  It will contain an IBIS
style syntax.  Bob Ross noted that this was discussed at the European IBIS
Summit, and the presentation contains some information about the approach.

- JEDEC JC-16 - Bob Ross reported that JEDEC, IBIS, Silicon Tech and Intel
are co-sponsoring a free class on IBIS on Wednesday, April 26, 2000, 8 AM to
noon at the Silicon Valley Convention Center.  The signup deadline has
passed.  Bob received an estimate of 180 attendees based on 157 signups at
the deadline.  Ron Werner asked, and Bob noted that class material will be
uploaded and be made available.  Arpad Muranyi will be the instructor.


DATE2000 IBIS SUMMIT FEEDBACK
Bob Ross commented that he had good feedback regarding the informative
content of the European IBIS Summit Meeting held on March 31, 2000 in Paris,
France.  DATE 2001 is scheduled in Munich, Germany, March 12-16, 2001.  We
will probably plan another European IBIS Summit Meeting at that time.


DAC2000 IBIS SUMMIT MEETING
Bob Ross reported that DAC 2000 is being held at the Los Angeles Convention
Center.  The trade show portion is held Monday through Wednesday, June 5-7,
2000.  The IBIS Summit Meeting is planned Thursday, June 8, 2000 from the
morning through early afternoon.

The main topics will be our annual election of officers and the connector
Specification.  Other topics will be related to on going IBIS futures
activities.

A room has been reserved at the Hyatt Regency Hotel, about six blocks away
from the Convention Center and near several other hotels serving the
conference.  A room further away had been reserved, but that reservation
will be cancelled.

Guy de Burgh will be handling the signups.  The first notice is expected to
be sent out next week.  Michael Cohen asked if the agenda had been set.  Bob
noted that we will be asking for presentations, and the agenda will be formed
later based on presentations that are contributed.


ACCURACY HANDBOOK
Greg Edlund reported that as a result of recent SI list interest, he updated
the former IBIS Accuracy Specification and sent it to people on the Accuracy
committee.  It is now renamed I/O Buffer Accuracy Handbook.  It contains
SPICE model and IBIS datasheet checklists.  Greg expects to release the
document next week in .pdf format after responding to some review comments.

Greg also noted that his company is building an accuracy test board.  He
is also working on an accuracy trailer and also on an accuracy report that
discusses laboratory versus Spice and laboratory versus behavioral simulation.  
He is awaiting internal approval regarding publishing the data.  Greg expects
the board and report within several months.


COOKBOOK STATUS
Stephen Peters had no report.


IBIS MODEL REVIEW COMMITTEE DISCUSSION
Matthew Flora reported that models from Texas Instruments and Motorola have
been sent out for review.


BIRD62.6 ENHANCED CHARACTERIZATION OF RECEIVER THRESHOLDS
Bob Ross introduced BIRD62.6 by noting that this has been discussed at recent
meetings.  At the last meeting we made some changes, thus delaying a planned
vote to allow for the two-week review period.

Stephen Peters and Bob noted some of the changes.  The last change was to
convert Input_edge_rate subparameters (specified as slew rates) to time
subparameters Tslew_ac and Tdiffslew_ac since they related to times crossing
the Vin*_ac and Vdiff_ac thresholds.

Bob called for a vote.  BIRD62.6 was approved 10 Yes, 0 No, and 1 Abstention.


BIRD66 - [Model Spec] Vref ADDITION
Bob Ross reintroduced BIRD66 by noting that it opens the door to consider
related extensions.  BIRD66 adds timing test load Vref min and max values.

We probably will not add the Rser extension to the timing test load even
though it is in some JEDEC documents because JEDEC is moving toward the
IBIS timing test load specification.  We do need to consider whether to add
independent loads for rising and falling waveforms, as done in some PCI
specifications.  Finally, we could also add min and max values for Rref and
Cref.  Weston Beal noted that some buffers have different Cref values for
min and max conditions.

There are two points of view regarding application of timing test loads.  It
could be used for a common time adjustment value (to calibrate the simulator
delays to the specification delays.  From this perspective, only one test at
typical conditions is needed since the other time is already time correlated.
This also relates to how a random part might be measured for compliance to
the timing specifications.

The other point of view that is being implemented in models is that corner
different timing test loads are used for the min and max corners for a wider
range of loads.  These points of view need to be understood and resolved.
Reflector discussion on BIRD66 is needed.


IBIS VERSION 4.0
During the above discussion Stephen Peters asked which BIRDs are needed for
IBIS Version 4.0.  Should there be a cutoff list?  Bob Ross noted that we
should process the open BIRDs.  We also need a BIRD for simultaneous switching
noise and perhaps a few other BIRDs.  Bob will work on the simultaneous
switching noise proposal per Dr. Unger's January 31, 2000 IBIS Summit meeting
presentation.


BUG34 - No Error Reported for Missing V/I Tables in Output Buffers
Bob Ross sent out to the IBIS reflector BUG34 for review and discussion.  He
had planned to issue other BUG reports, but still has not yet generated them.

For background, BUG34 had been introduced in January 1999 and updated in
October 1999.  It has been classified as an "Annoying" bug and discussion on
it had been deferred while we worked on other issues including IBIS Version
3.2 ratification.

Matthew Flora, who authored BUG34, stated that he encountered the problem
while checking actual models.  The IBIS parser gave no error or warning
messages for a non-functioning output model that did not have any [Pulldown] or
[Pullup] tables.

Matthew's revised BUG34 proposed a number of Warning versus Error messages
since there were cases where [Rising Waveform] tables and [Falling Waveform]
tables or [Submodel] data introduced the correct responses, even for an
incorrect model type designation.  Bob read one Warning message for a missing
[Pullup] table for an output buffer.  After some discussion, the group 
generally supported the longer, more user friendly messages.  Matthew noted
that such a message would not occur very often.

Bob did feel that the "Perhaps it should be." statement was excessive and the
wording could be tightened up slightly.  Also, Bob commented that the Warning
for missing both the [Pullup] table and [Pulldown] table was probably not
necessary since individual messages regarding each of the tables could be
issued.  That should give adequate warning that there is an inconsistency.

Bob will work with Matthew off-line to discuss details of the message.  Then
Matthew plans to issue an updated BUG34.


CONNECTOR PROPOSAL REVIEW (CONTINUED)
Bob Ross noted that another review meeting occurred on Tuesday, April 11, 2000
with Gus Panella, Bob and Guy de Burgh.  Matthew Flora stated that Version
0.941 for the document has been uploaded in 

  http://www.eda.org/pub/ibis/connector/

with most of the changes mentioned in the March 17, 2000 IBIS teleconference
meeting.

Most of the discussion concerned the required and optional parameters of
[Begin_Cn_Model] for the three cases previously defined:

  Physical connectors using a Defined Physical Pin
  Physical connectors using Swath Matrix ([Begin_Cn_Swath])
  Auto generated connectors using the Swath Matrix and [Begin_Cn_Auto_Map].

Currently, [Begin_Cn_Model] requires the names ModelPinMap and ModelPhyMap.
However, there are cases where one or the other is not used.  Bob mentioned
that "NA" could per permitted for cases where [Begin_Cn_Pin_Map] or 
[Begin_Cn_Phy_Map] do not need to be defined.

Most of the discussion concerned the Swath matrix details.  Unlike the
package model syntax in IBIS Version 3.2 (and Version 2.1) which document the
matrix structures using actual alphanumeric pin numbers, connector model
matrices are described indirectly using indices starting sequentially with 
"1".  The Swath matrix format supports specifying extra rows and columns which
would be terminated during simulation by the [Cn_Z] resistance value.  For
example, 2 additional columns could be specified on each end of a 2 by 5
connector.  The matrices would have 18 entries (10 for the connector pins, and
4 at each end for the extra connections terminated by [Cn_Z] value.

Later, Bob noted that pin cross-over (e.g., side A pin 1 connecting to side B
pin 2, and visa versa) had been mentioned, but the existing syntax did not
appear to support this.  An addition might be made for this.

The next meeting is planned on Wednesday, April 19, 2000.  The focus will be
the input syntax for number of pins, rows, and columns and also the 
[Begin_Cn_Auto_Map] mode.  The intent is to assure that there is syntax
consistency for all situations and that the ability to enter conflicting
information is minimized.


IBIS FUTURES (IBIS-X, API, BIRDxx)
Stephen Peters reported on an all day meeting held in Oregon on Thursday,
March 30, 2000 with eight people on IBIS Future directions.  Arpad Muranyi
sent out minutes to the group.  Stephen listed a few of the conclusions:

  Transistor level behavioral support is needed.
  The ability for simulator vendors to encrypt models was discussed as a
    needed option
  A new specification is required.

The meeting covered in a number of topics including

  Review of Arpad's IBIS futures question SI-list reflector responses
  Arpad's need for die to pad interconnection.  (Bob Ross noted that IMIC also
    does this already in nodal syntax.)
  Stephen's IBIS-X requirements
  Scott McMorrow's proposal for a general way to connect pin internal models.
  Al Davis' proposed macro language.  This generated great interest.

The next set of actions is to work on the macro language and syntax for nodal
connections and netlist connections.  The description language would also
included signal integrity specification and information parameters.

The AR's for the group were:

   Al Davis make some refinements per the discussion
   Al Davis write a proposal for a wrapper syntax around the model
   Arpad Muranyi write a proposed syntax for the header section

Since the meeting covered much more than noted above, Bob suggested that
Stephen send the minutes to the IBIS reflector.

Michael Cohen mentioned that D.C. [Sessions] brought up the idea of using
VHDL_A or Verilog_A as the future of IBIS since simulators already
process these or have access.  This would yield more rapid adoption
versus defining a new language.

Bob indicated that XML formats for Web based syntax had also been proposed.
He and Weston Beal referenced a link with a new XML based Timing Diagram
Markup Language (TDML) at:

  http://www.si2.org/ecix/tdml/

So we might be motivated to consider using a similar XML format.

Bob opened the discussion regarding encryption.  Stephen noted that he
sees technologies that would require hiding the internal intellectual property
structures regardless of format.  The committee just introduced the idea.
Initially, Stephen thought that EDA vendors will do the de-encryption.  Raj
Raghuram commented that this defeats the purpose of IBIS.  Michael added that
he has had bad experience with encrypted models.

Stephen had planned for another meeting, but its details are still open. 


BIRD61.1 - ENHANCED CHARACTERIZATION OF RECEIVERS
Stephen noted that we will probably reject BIRD61.1 since the behavioral 
receiver modeling approach seems more promising.


BIRD64.1 - PACKAGE MODE SELECTOR
Not Discussed.


BIRD65 - C_comp REFINEMENTS
Not Discussed.


NEW TECHNOLOGIES
Not discussed.


NEXT MEETING:
The next teleconference meeting will be on Friday, May 5, 2000 from 8:00 AM
to 10:00 AM.

==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jpowell@innoveda.com
            Senior Scientist, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Signal Integrity Engineer, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            114715 N.E. 95th Street
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org/eig/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================

From owner-ibis  Tue Apr 18 14:18:14 2000
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From: guy@camarillo.viewlogic.com (Guy de Burgh)
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To: ibis@eda.org
Subject: DAC IBIS Meeting Announcement



             D A C   2 0 0 0   I B I S   S U M M I T   M E E T I N G
                       F I R S T   A N N O U N C E M E N T

DATE:      Thursday, June 8, 2000
TIME:      8:30 AM - 5:00 PM

CITY:      Los Angeles, California

LOCATION:  Hyatt Regency Hotel (About 6 blocks from DAC 2000)
           711 S. Hope St.
           (213) 683-1234

ROOM:      To be Announced

LUNCH:     Free Refreshments and Lunch will be provided.

AGENDA:    The agenda is being planned.  Some planned items are:

             Election of Officers for 2000 - 2001

             Connector Specification Discussion

             IBIS Version 4.0 Issues

             Future IBIS Progress and Issues

           We welcome presentations and discussions on IBIS topics.


DAC2000:   DAC is scheduled Monday - Friday, June 5 - 9, 2000.  The exhibitor
           portion is open from Monday - Wednesday.  For more information
           on DAC 2000 activities, housing, etc., visit the DAC URL:

DAC URL:   http://www.dac.com/


CALL FOR PRESENTATIONS:

           We are also open to technical presentations related to any current
           IBIS activity and to future IBIS needs.
 
           Contact Guy de Burgh regarding your presentation:

              Presenter:
              Title:
              Estimated Time:

           Please plan to use regular overhead slides for the presentation.

           We would like you to provide handouts for the meeting (about 25)
           and also an electronic copy for archiving.
          

CALL FOR ATTENDEES:

           Please let Guy de Burgh know if you are planning to attend so
           we have an estimate on food requirements. 


CONTACT:   Guy de Burgh
           gdeburgh@innoveda.com
           (805) 988-8250 xt 6823

From owner-ibis  Mon Apr 24 16:21:10 2000
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From: <bebner@earthlink.net>
To: <ibis@vhdl.org>
Date: Mon, 24 Apr 2000 15:41:12
Message-Id: <386.685384.48166@msn.com>
Subject: New stress sensor can ensure proper registration of laminate on honeycomb core!
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Dear Engineer:

I am writing to inform you of a new product of ours - a sensor 
film that, by changing color, reveals the stress distribution and 
magnitude between any two surfaces that come in contact. The 
intensity of the resultant color is quantifiable and enables you 
to determine precisely what the PSI is at any point on the 
contacting surfaces. This product is useful for assessing 
interfacial stresses that occur at gasketed and flanged 
interfaces, in lamination presses, roller systems and heat 
sealers, during welding, in materials testing and from impact 
forces. 

If you would like a FREE product sample or literature please let 
me know and I will be sure to send it out immediately. Please be 
sure to include an approximate PSI range that you want to 
experiment with for the application you have in mind. Pressurex is 
available in five sample ranges. Please choose one:

28 - 85 PSI 
70 - 350 PSI
350 - 1400 PSI
1400 - 7100 PSI
7100 - 18,500 PSI

Also be sure to include your contact information (address, phone, 
fax, etc.)

Thank you for your time.


Bill Ebner
Sensor Products Inc. 
188 Rt. 10 Ste. 307
E. Hanover, NJ 07936 USA

http:\\www.fuji-prescale.com

ph 973.560.9092
fx 973.884.1699



Further transmissions to you by the sender of this email may be 
stopped by sending a reply to this email address with the word 
remove in the text area or subject line.
















 
 
 
 
 
From owner-ibis  Tue Apr 25 06:40:33 2000
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From: Marc Humphreys <mhumphreys@nexabit.com>
To: bebner@earthlink.net, ibis@vhdl.org
Subject: RE: New stress sensor can ensure proper registration of laminate 
	on honeycomb core!
Date: Tue, 25 Apr 2000 09:38:16 -0400
MIME-Version: 1.0
X-Mailer: Internet Mail Service (5.5.2650.21)
Content-Type: text/plain

And I suppose there is an IBIS model for this too! 

At least advertise something that's somewhat related to IBIS.

And for any other smart ass, we really don't need to hear
about your creative suggestions on how it is relevant or
where to stick it! 

All done being stressed.



> -----Original Message-----
> From:	bebner@earthlink.net [SMTP:bebner@earthlink.net]
> Sent:	Monday, April 24, 2000 11:41 AM
> To:	ibis@vhdl.org
> Subject:	New stress sensor can ensure proper registration of laminate
> on honeycomb core!
> 
> Dear Engineer:
> 
> I am writing to inform you of a new product of ours - a sensor 
> film that, by changing color, reveals the stress distribution and 
> magnitude between any two surfaces that come in contact. The 
> intensity of the resultant color is quantifiable and enables you 
> to determine precisely what the PSI is at any point on the 
> contacting surfaces. This product is useful for assessing 
> interfacial stresses that occur at gasketed and flanged 
> interfaces, in lamination presses, roller systems and heat 
> sealers, during welding, in materials testing and from impact 
> forces. 
> 
> If you would like a FREE product sample or literature please let 
> me know and I will be sure to send it out immediately. Please be 
> sure to include an approximate PSI range that you want to 
> experiment with for the application you have in mind. Pressurex is 
> available in five sample ranges. Please choose one:
> 
> 28 - 85 PSI 
> 70 - 350 PSI
> 350 - 1400 PSI
> 1400 - 7100 PSI
> 7100 - 18,500 PSI
> 
> Also be sure to include your contact information (address, phone, 
> fax, etc.)
> 
> Thank you for your time.
> 
> 
> Bill Ebner
> Sensor Products Inc. 
> 188 Rt. 10 Ste. 307
> E. Hanover, NJ 07936 USA
> 
> http:\\www.fuji-prescale.com
> 
> ph 973.560.9092
> fx 973.884.1699
> 
> 
> 
> Further transmissions to you by the sender of this email may be 
> stopped by sending a reply to this email address with the word 
> remove in the text area or subject line.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>  
>  
>  
>  
>  
From owner-ibis  Fri Apr 28 11:22:28 2000
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Date: Fri, 28 Apr 2000 11:20:15 -0700
From: Bob Ross <bob_ross@mentorg.com>
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Subject: IBIS Meeting Agenda 5/5/00
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                     IBIS Open Forum Meeting Agenda 
                               for 5/5/00

                 Bridge Number    Reservation #   Passcode
                 (916) 356-9200   3-373073        1535639

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Ross/Fleming
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Powell, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Ross/Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
          for Integrated Circuits (IMIC)                     Raghuram/Ross
     - IEC PWI 93-1 Models of Integrated Circuits for EMI 
       Behavioral Simulation (formerly designated as
       IEC 93/67/NP IBIS and EMC Simulation)                 Perrin
     - JEDEC JC-16 Modeling and Testing                      Sessions
    
     DAC2000 IBIS Summit Meeting Planning                    Ross

     Accuracy Handbook                                       Ross

     Cookbook Status                                         Peters

     IBIS Model Review Committee                             Flora

     New Administrative Issues                               All

8:45 Technical Discussion (some topics may be deferred)

     BIRD66 - [Model Spec] Vref Addition                     McMorrow/Ross

     Connector Proposal Review (Continued)              Panella/Chrisafulli

     ibischk3 Bug Tracking                                   Ross
     - BUG34 - No Error Reported for Missing V/I Tables      Flora
             in Output Buffers
     - Repeated Voltage
     - 8.3 Version 2.1 Error
     - Series element does not work with I/O models

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters

     BIRD61.1 - Enhanced Characterization of Receivers       Peters

     BIRD64.1 - Package Model Selector                       Muranyi

     BIRD65 - C_comp Refinements                             Muranyi

     New Technologies                                        Cohen
     AVC                                                     Nolan

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off
