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                     IBIS Open Forum Meeting Agenda
                              for 12/8/00

                 Bridge Number    Reservation #   Passcode
                 (916) 356-9200   8-177128        7335175

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Ross/Fleming
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  LaBonte, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Ross/Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
          for Integrated Circuits (IMIC)                     Ross
     - IEC PWI 93-1 Models of Integrated Circuits for EMI 
       Behavioral Simulation (formerly designated as
       IEC 93/67/NP IBIS and EMC Simulation)                 Perrin/Ross
     - JEDEC JC-16 Modeling and Testing                      Sessions
    
     Future Summit Planning                                  Ross

     IBIS Model Review Committee                             Angulo

     New Administrative Issues                               All

8:45 Technical Discussion (some topics may be deferred)

     Connector Proposal Review                               Panella

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters

     BIRD64.4 - Alternate Package Models Selector (Vote)     Muranyi/Cohen

     BIRD66 - [Model Spec] Vref Addition (Vote)              Ross

     BIRD67.1 - Increase V-T Table 100 Point Limit (Vote)    Ross/Dodd

     BIRD65 - C_comp Refinements                             Muranyi

     BIRD68 - Clarify that Rising and Falling Waveform       Lorang
              Tables Should be Correlated

     ibischk3 Bug Tracking                                   Ross

     - BUG49 Warning Message for Unreferenced Models,        Ross/Mirmak
             Submodels
   
     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Ross

9:55 Sign Off
 
From owner-ibis Tue Dec  5 14:37:15 2000
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       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       ----------------------------------------------------------------
       DESIGNCON 2001 IBIS SUMMIT CALL FOR PARTICIPATION, PRESENTATIONS
       ----------------------------------------------------------------
       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

                    I B I S   S U M M I T   M E E T I N G

Time/Date:     8:00 PM - 5:00 PM, Monday, January 29, 2001

Location:      Santa Clara Convention Center
               Santa Clara, CA

Content:       IBIS Future Requirements is the main topic of this meeting
               These include an exchange of ideas on IBIS accuracy,
               connectors, and new requirements under discussion.

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      DesignCon 2001 & National Semiconductor Corporation

IBIS Summit Signup:
               Milt Schwartz
               schwartz@galaxy.nsc.com


                   D E S I G N C O N   2 0 0 0   M E E T I N G S

Time/Date:     Monday - Thursday, January 29 - February 1, 2001

Exhibition:    Tuesday - Wednesday, 12:30 PM - 6:30 PM, January 30-31, 2001

IBIS Booth:    #861, Exhibition Hall
               - IBIS Information

URL DesignCon2001:
               http://www.designcon.com/


CALL FOR IBIS SUMMIT PRESENTATIONS

We already have several presentations and discussion topics planned.  However,
we are also seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  If you cannot provide
                         an electronic format, then plan to bring 50
                         copies for distribution at the meeting.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Milt Schwartz
  schwartz@galaxy.nsc.com

Deadline: Wednesday, January 24, 2001 for receiving presentations for
          copying.
 

AGENDA

The agenda includes presentations, discussions, refreshments, and a free
buffet luncheon for participants.  In addition, we will have an opportunity
for Ad Hoc presentations and extended discussions.  Currently we have:

  "Spice 2 IBIS Accuracy Report", Scott McMorrow, Siqual

Milt Schwartz Interface Applications
National Semiconductor
2900 Semiconductor Dr.
Mail Stop A2595
Santa Clara, CA 95052

email: schwartz@galaxy.nsc.com
Phone:  408 721 3261
Fax  :  408 721 4785
 
From owner-ibis Wed Dec  6 15:50:51 2000
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To All:

We plan to vote on BIRDs 64.4, 66 and 67.1.  You can review them at:

  http://www.eda.org/pub/ibis/birds/index.html

Also, if time permits, we plan to discuss the resolution of BUG49
and also classify recently entered BUGs 51 and 52.  They can be
reviewed at:

  http://www.eda.org/pub/ibis/bugs/ibischk/

Bob Ross
Mentor Graphics
 
From owner-ibis Wed Dec  6 17:33:17 2000
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Please add my name to your email list . Thanks

Patrick Lam

Optimal Corporation
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Subject: EIA IBIS Open Forum Meeting Minutes (12/08/00)


Date: 12/11/00

SUBJECT: 12/8/00 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2000 PARTICIPANTS LIST:
3Com                           Roy Leventhal*
Agilent (EEsof, etc.)          Mark Chang
Ansoft Corporation             (Eric Bracken)
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Balistreri
Avanti                         Nikolai Bannov
Brocade Communications         Robert Badal
Cadence Design                 [Mike LaBonte], [Todd Westerhoff], Ian Dodd*,
                               Donald Telian, Patrick Dos Santos
Cisco Systems                  Syed Huq, Irfan Elahi, John Fisher
Compaq                         [Bob Haller], Peter LaFlamme, Ron Bellomio,
                               Shafier Rahman, Doug Burns
Cypress                        (Rajesh Manapat)
EMC Corporation                Fabrizio Zanella, Brian Arsenault,
                               Terry Jernberg, Alexander Nosovitski,
                               Elena Gutman, Shan Haq
Fairchild Semiconductor        Craig Klem
HyperLynx (& Pads Software)    Matthew Flora*, [Kellee Crisafulli],
  (Now merged with Innoveda)   Gene Garat, John Angulo, [Al Davis],
                               Lynne Green
IBM                            Michael Cohen*, Greg Edlund*, Jerry Hayes
Innoveda (Viewlogic Systems)   Chris Rokusek, Guy de Burgh*, [Jun Tian],
                               Cary Mandel, Brad Griffin, (Jon Powell)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs,
                               Richard Mellitz, Charles Phares, Meir Nakar,
                               Sigeti Gabi, Tudor Secasiu, Dave Lorang,
                               Michael Mirmak*
LSI Logic                      Larry Barnes*
Mentor Graphics (& Veribest)   Bob Ross*, Tom Dagostino, Malcolm Ash,
                               Kim Owen, Jean Oudinot, Sherif Hammad,
                               Hazam Hegazy, Weston Beal, Ken Bakalar
Micron Technology              Randy Wolff*, Son Huynh, Yong Phan*
Mitsubishi                     Shahab Ahmed, Carleen Murphy, Scott Estrich
Molex Incorporated             Gus Panella
Motorola                       Ron Werner
National Semiconductor         Milt Schwartz*
Nortel Networks                Steve Coe, Calvin Trowell, Hassan Ali
North East Systems Associates  Edward Sayre, Tony Sinker, Kathy Breda,
                               Jinhua Chen
Philips Semiconductor          D.C. Sessions, Todd Andersen
  (& VLSI Technology)
Quantic EMC                    (Mike Ventham)
Robinson-Nugent, Inc.          (Alexander Barr)
Siemens AG                     Bernhard Unger, Gerald Bannert
SiQual                         Scott McMorrow, Wis Macomson
Texas Instruments              Stephen Nolan, Ramzi Ammar, Mac McCaughey,
                               Thomas Fisher, Jean-Claude Perrin,
                               Jean-Yves Oberle
Time Domain Analysis Systems   Dima Smolyansky, Steven Corey
Tyco Electronics (AMP)         (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Werner Rissiek, John Berrie

OTHER PARTICIPANTS IN 2000:
Actel Corp.                    Silvia Montoya
Advansis                       Mikio Kiyono
Aerospatiale Matra CCR         Lionel Dreux, Julien Boullie
Alcatel (Lannion, Bell)        Daniel Peron, Steven Criel
Cereva Networks                Bob Haller
ECI Telecom                    Daniel Adar
EIA                            Cecilia Fleming*
Fraunhofer Institute           Michael Kurten
Jet Propulsion Lab             John Treichlew
KAW                            Shinichi Maeda
Hewlett Packard                Paul Gregory
RCI                            Chris Rode
Rockwell Collins               Ron Hau
Signals & Systems Engineering  Tom Hawkins
ST Microelectronics            Fabrice Boissiere, Pierre Saintot
Sun Microsystems               Victor Chang
Thomson-CSF                    Savenrio Lerose, Pascal Vaslin, Thierry Zak,
                               Sylvie Lasserre
Transfer                       Hans Klos, Wilco Hamhuis
Xilinx, Inc.                   Susan Wu
Independent, Consultant        Hideki Fukuda, Al Davis

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  January 5, 2001     (916) 356-9200   3-454694         8973669
  January 29, 2001 - IBIS Summit Meeting, No Teleconference


All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS AND MEETING QUORUM
Bob Ross noted that Ian Dodd is now the primary representative for Cadence
since Mike LaBonte has changed jobs.

Larry Barnes joined for the first time this year from LSI Logic.  He had
previously been involved in IBIS from Symbios prior to being acquired by LSI
Logic.  Larry's interest in IBIS is related to some ANSI SCSI-3 committee
work and some emerging related issues.  This will be discussed later in the
meeting.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Cecilia Fleming reported that 33 invoices for 2001 have been sent out to the
member companies.  We are still trying to find a new representative for one
company.  In 2001 HyperLynx will not invoiced since they are now merged with
Innoveda.


REVIEW OF MINUTES AND AR'S
The November 17, 2000 IBIS Minutes were approved without change.

The AR's will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None (some announcement items will be new agenda items discussed elsewhere).


PRESS AND WEB PAGE UPDATES
Cecilia Fleming reported that she received and installed web updates from Syed
Huq for Poster, Upcoming Events, and Free Utilities changes.  One company logo
was removed form the Poster page because of a company merger making the old
logo invalid.  Bob Ross mentioned that the HyperLynx logo might also be
removed per the instructions to Syed from Guy de Burgh of Innoveda.

Bob also reported that the article "Optimize Power Distribution Analysis in
High-Speed Systems Designs" by Todd Westerhoff in the November 20, 2000 issue
of Electronic Design mentions IBIS modeling.  The article can also be found
under the magazine link:

  http://www.elecdesign.com/


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that the Fujitsu flash memory IBIS model link has changed:

  http://edevice.fujitsu.com/fj/CATALOG/AD05/IBIS/index_e.html

Also, Intel has released the Pentium(R) 4 Processor models under:

  http://developer.intel.com/design/pentium4/devtools/


OPENS FOR NEW ISSUES
Michael Mirmak - BUG51 - Error Message Needed for Missing [Submodel]
Michael Mirmak - BUG52 - IBISCHK3 Hangs for [Add Submodel] Instead of
                         [Submodel]
Greg Edlund - New Accuracy figure of merit C code (New Administrative Issues)
Bob Ross - Upcoming vacations and next meeting (New Administrative Issues)
Bob Ross - IBIS Librarian (New Administrative Issues)
Roy Leventhal - Modeling Semiconductor Components from 30,000 Feet (Part of
                Future Summit Planning)
Larry Barnes - SCSI-3 Compensation Modeling (Part of Future Summit Planning)


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 3.2) - Cecilia Fleming had no further report, but
she will follow up on the status by e-mail.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
(IMIC) - No report.

- IEC PWI 93-1 Models of Integrated Circuits for EMI Behavioral Simulation
(formerly designated as IEC 93/67/NP IBIS and EMC Simulation) - Bob Ross
commented that Jean-Claude Perrin had gave us status at the November 17, 2000
meeting.  Bob had no further report.

- JEDEC JC-16 - Modeling and Testing - Bob Ross noted that the JEDEC JC-16
and JC-42 are meeting December 6-7, 2000 in Kona, Hawaii.  We should find out
more at the next meeting.  Cecilia Fleming offered to send the JEDEC minutes
to Bob to keep him informed.


FUTURE SUMMIT PLANNING (Including some new agenda items)
Bob Ross stated again the basic information that the next IBIS Summit Meeting
is planned on January 29, 2001 in Santa Clara, California along with
DesignCon 2001 (January 29 - February 1, 2000).  National Semiconductor is a
co-sponsor of this meeting and will provide the lunch.  Milt Schwartz is
planning for 50 lunches.  DesignCon is the other co-sponsor as a result of
IBIS Associate Sponsorship of DesignCon 2001.

Bob noted that the first announcement has been sent out.  Milt reported that
he has received six signups already.  Bob estimated over 10 signups so far and
will get more input from Milt offline.

We have been assigned Booth #861.  Guy de Burgh reported receiving the show
manual from Bob, and he and Jon Powell will be responsible for setting up
the booth.  Bob asked Guy to work with Jon to request the company logo 
information again for the Booth backdrop.

Bob discussed the meeting agenda to date.  Some topics were added.  The titles
listed may change.

  "Spice 2 IBIS Accuracy Report", Scott McMorrow, Siqual
  "Connector Specification Discussion", Gus Panella, Molex
  "IBIS Futures", Stephen Peters, Intel

Several New Agenda Items were discussed, and these relate to additional 
presentations:

  "Modeling Semiconductor Components from 30,000 Feet", Roy Leventhal, 3Com.
  Roy Leventhal stated that he has written a "paper" related to general
  modeling issues spanning Spice, matrix, and behavioral techniques.  He has
  sent it out for some early private review.  Eventually he would like it
  uploaded on a public site.  Bob stated that it is more like a book with
  about 250 pages, nine sections and an appendix.  Bob read the section titles
  to illustrate the broad coverage.  Roy would introduce this paper at the
  IBIS Summit Meeting.

  "SCSI-3 Compensation Modeling" Larry Barnes, LSI Logic.
  Larry Barnes is involved with an ANSI T10 committee on Low Level Parallel
  Interfaces.  He is serving as technical editor for subgroup and is using
  IBIS as part of the specification.  The committee is concerned with SCSI
  buffers driving 12 foot cables.  It defining a bit encoding technique for
  run length encoded based changes in signal amplitude.  Larry wants to
  discuss issues on how to apply IBIS.  The document is planned to be
  completed around March 2001.  Bob stated that this could be of interest for
  existing IBIS and also for the future version of IBIS.

Bob noted that we will have a full meeting.  We probably will get a few more
presentations related to Future IBIS issues.

Bob also stated the early plans for the European IBIS Summit meeting to be
held March 16, 2000 in Munich, Germany along with the Design Automation and
Testing in Europe (DATE 2001) conference and exhibit.  Bob indicated that
four companies are now planning to co-sponsor the meeting: Cadence, Innoveda,
Mentor Graphics and Zuken (Incases).


IBIS MODEL REVIEW COMMITTEE DISCUSSION
Matthew Flora reported for John Angulo who is on vacation that no models have
been recently submitted or sent out.


NEW ACCURACY FIGURE OF MERIT C CODE (New Agenda Item)
Greg Edlund reported that the IBIS Home Page Accuracy Link now has a new
C utility for calculating two existing figures of merit and also two new ones
from waveform files.  This utility is freeware and can be used and modified
by anyone.  Greg plans to send out a reflector note.  Bob Ross indicated that
there was also good documentation with it.


VACATIONS AND NEXT MEETING (New Agenda Item)
Bob Ross mentioned that several people will be out during the Christmas and
New Years holidays.

  Bob Ross:  December 11 - December 26
  Jon Angulo: Returning December 13
  Matthew Flora: December 18 - December 29
  Guy de Burgh: December 24 - January 1
  Stephen Peters: Possibly December 22

Based on this we agreed to move the December 22 meeting to January 5, 2001.
We also had considered January 12, 2001, but will cancel that reservation.
The IBIS Summit Meeting at DesignCon 2001 on January 29, 2001 will follow in
just over three weeks.


IBIS LIBRARIAN (New Agenda Item)
Bob Ross indicated that Mike LaBonte has resigned the Librarian position as a
result of accepting a new job.  Bob has several potential candidates to
replace Mike.  They include Michael Cohen and Roy Leventhal.  Anyone else
who wants to be considered for this position should contact Bob.

Bob plans that the IBIS Committee select or formally vote for someone at the
next meeting on January 5, 2001.


CONNECTOR PROPOSAL REVIEW
Bob Ross reported that the Working Group has been meeting weekly on November
21, November 28, and December 5, 2000.  The next meeting is scheduled on 
December 12, 2000.

Ian Dodd reported that there has been progress in clarifying the matrix
expansion discussion, and also there is a new, formal language for naming
pins.  Bob felt that we have agreed on most technical issues and are nearing 
completion and hopes to have a complete technical draft prior to the DesignCon
IBIS Summit.  The draft will probably not be as editorially clean as would
like.  However we want to make the technical content available as early as
possible for review and plan to clean up the document while it is being
reviewed.


IBIS FUTURES (IBIS-X, API, BIRDxx)
Bob Ross noted that the Working Group met on November 21, November 28, and
December 5, 2000.  The next meeting is scheduled on December 19, 2000.

Stephen Peters (who is taking over for Mike LaBonte) reported that the
Working Group is producing a top level specification.  There still needs to
be work on a component section to deal with die interconnect and pin to buffer
modeling.  The macro language has been developed, but it needs to be more
formally documented.  Bob noted that we would like a very readable document
that communicates the new features and shows how they relate to the existing
IBIS Version 3.2 (for upward compatibility).

Stephen would like the new Header section to be compatible with the Connector
Specification Header.  Since several members are in both Working Groups, the
Header documents should be similar.


BIRD64.4 - ALTERNATE PACKAGE MODELS
Bob Ross introduced BIRD64.4 by indicating that it had been discussed at the
November 17, 2000 meeting.  We had agreed upon some "editorial" changes.  It
is permissible to make minor changes as long as they do not impact the basic
functionality.  We ran out of time before voting on BIRD64.3 with changes.
So Mike LaBonte issued BIRD64.4 after the meeting with the editorial changes
and complied with the AR at that meeting.

Bob summarized the changes: Use "shall" instead of "may", remove part of one
slightly ambiguous portion of a sentence that constrained where [Alternative
Package Models] would be placed under the [Component] keyword, and add a
sentence that any model listed by [Package Model] could be repeated in the
[Alternative Package Models] list.

Arpad Muranyi, a co-author, supported the changes.  Bob stated that most of
the recent concerns were related to editorial preferences and not technical
issues.  After no further discussion, Bob called for a vote.

BIRD64.4 was approved by a vote of 10 YES and 0 NO.


BIRD66 - [Model Spec] Vref ADDITION
Bob Ross introduced BIRD66 by noting that it had been originally introduced
by Scott McMorrow in November 1999.  Bob stated that the Vref subparameter
would be added to the [Model Spec] lists to capture cases where Vref is 
different for min and max voltages.  An example would be for PECL technology.

Bob stated that there were cases where the timing test load would change with
supply variations.  However, there were other considerations that delayed
immediate resolution.  We thought that we might use BIRD66 to also consider
possible Rref and Cref changes.  We also might have added an series resistor
to the timing test load such as used by some SSTL configurations.  However,
based upon D.C. Sessions recommendation, we were discouraged from adding this.
Instead, JEDEC will try not to use the series resistor.  Finally, there are
some cases where the rising edge uses a different test load than the falling
edge.  Bob basically supported the notion that we should just consider Vref
only as in BIRD66.  We can issue other BIRDs if additional subparameters are
requested.

Bob also stated that there might be questions in how Rref would be used.
Originally the timing test load was considered only for use with typical
column information to get a common delay reference value.  However, in
practice, some models have been issued with timing test loads connected for
minimum and maximum voltages corners.  Bob supported adding the Vref
subparameter and letting the EDA vendors use (or ignore) the information as
appropriate.

With no further discussion, Bob called for a vote.

BIRD66 was approved by a vote of 10 YES and 0 NO.


BIRD67.1 - INCREASE V-T TABLE 100 POINT LIMIT
Bob Ross mentioned that issues regarding increasing the number of allowable
data points in V-T had been discussed in previous meetings.  We resolved to
set the limit at 1000 (versus 1001).  We also limited BIRD67.1 to V-T tables.
A separate BIRD would need to be issued for V-I table limits.  Finally, to
resolve an ambiguity raised by Michael Cohen, we changed "points" to "rows" in
BIRD67.1.  This means that the 1000 point limit is on number of rows rather
than the number of numerical entries.  So NA entries in any column are
included in the row count.

Co-author Ian Dodd had no further comments.  With no further discussion, Bob
called for a vote.

BIRD67.1 was approved by a vote of 10 YES and 0 NO.

With the resolution of the above three BIRDs and also of a previous BIRD62.6,
Bob plans to upload a new pending IBIS Version 4.0 work in progress document
that includes the resolved BIRDs.
 

BIRD65 - C_comp REFINEMENTS
Bob Ross stated that Arpad Muranyi originally issued BIRD65 in October 1999.
Bob wants to move this toward resolution.  BIRD65 describes splitting up
C_comp into components attached to four different power rails.  We had
discussed aspects of BIRD65 previously and decided to use actual capacitance
values rather than to use percentages.

Bob suggested changing the subparameter names to better associate with the
actual supply rails.  BIRD65 uses: C_comp_pu, C_comp_pd, C_comp_pcl, and
C_comp_gcl.  Bob proposed: C_comp_pullup, C_comp_pulldown, C_comp_power,
C_comp_gnd.  We have chosen names in other cases such as the [Rpower] and
[Rgnd] keywords to emphasize the association with the corresponding rail.
Arpad stated that he had similar concerns and supported the changing the
subparameter names.

We discussed briefly that BIRD65 does state rules for when all of the new
subparameters are needed.  We need to review these rules.

Also Bob commented that we need to look in the Notes on Data Derivation
section to see if some changes need to be done there to reference the new
subparameters.

Bob asked Arpad to issue BIRD65.1 with the notation change and also with any
added text needed for the Notes on Data Derivation section.  

AR - Arpad Muranyi issue BIRD65.1 with notation changes and possible Notes on
Data Derivation section changes per the above discussion.

Bob plans to schedule BIRD65.1 for a vote at the January 5, 2001 IBIS meeting.


BIRD68 - CLARIFY THAT RISING AND FALLING WAVEFORM TABLES SHOULD BE CORRELATED
Bob Ross noted that BIRD68, authored by Dave Lorang, was scheduled for
discussion at the last meeting, but we ran out of time.

Stephen Peters briefly stated that BIRD68 dealt with correlating to a common
reference time the rising and falling edge waveforms.  This is needed for
capturing internal delays correctly for each edge and for meanful eye
diagrams and intersymbol interference analysis.  Milt Schwartz added later
that this is necessary for differential drivers.  Bob Ross added later that
submodels and driver schedule models may require time correlation in certain
cases.

Stephen raised one concern.  Do we add a positive indication such as a
subparameter that the waveforms are correlated?  This would provide a method
to document correlation and be compatible with IBIS Version 3.2 models where
such compatibility may not exist.  Bob is leaning against this, but
understands that there are concerns regarding providing such models in some
special case measurement or simulation situations.

Bob also was concerned with the specific language "input stimulus is assumed
to have initiated at the logic transition".  This could be interpreted as the
time of actually triggering the transition - an undefined or hard to determine
value.  A better statement might refer to a common reference point for the
input stimulus, such as the beginning of the input stimulus waveform for each
edge.  While there might be some slight error in this approach based on input
signal amplitude or ramp rate, this approach would still be more consistent
with actual waveform extraction based on simulation or measurement.

More discussion is planned for the next meeting.


IBISCHK3 BUG TRACKING (Including New Agenda Items)
Bob Ross reported on the status of the ibischk3 parser.  Atul Agarwal plans
to provide a release around mid December 2000 that includes BUG34 and BUG47.
At the November 17, 2000 meeting we planned to do these last two bug fixes
if they could be done quickly.  We are cutting the bug fixes off at BUG47
for this release in order to get some important corrections distributed.
Matthew Flora commented that he is still receiving IBIS models with problems
that would be exposed by the newer version of ibischk3.  These include
negative ramp rates (and Michael Cohen stated zero ramp rates).  Based on
vacation schedules, we expect the ibischk3 parser to be reviewed and released
in January 2001.

The review and release process involves checking the fixes, generating
executables (Matthew Flora for Windows, Syed Huq for Linux and Guy de Burgh
for the other operating systems).  

- BUG51 - Error Message Needed for Missing [Submodel] (New Item)
  Michael Mirmak introduced BUG51.  The ibischk3 parser correctly issues an
  Error when a referenced Submodel is not defined for most cases.  However,
  BUG51 documents a failure where no Submodels are defined and no error is
  issued.

  BUG51 was classified as MODERATE, MEDIUM, OPEN, and planned to be fixed in
  a future release.

- BUG52 - IBISCHK3 Hangs for [Add Submodel] Instead of [Submodel] (New Item)
  Michael Mirmak introduced BUG52.  It is related to BUG51, but documents a
  situation where the keyword [Submodel] is incorrectly replaced by [Add 
  Submodel].  In the reported test case, ibischk3 either hangs or crashes
  and does not complete the check.

  BUG52 was classified as SERIOUS, MEDIUM, OPEN, and planned to be fixed in
  a future release.

- BUG49 - Warning Message for Unreferenced Models, Submodels
  Bob Ross commented that BUG49 was discussed at the November 17, 2000
  meeting.  Several points had been brought up.  These related to whether
  warnings should be given for FPGAs where extra models might be added to
  the file, but not referenced.  Another discussion related to differences
  between unreferenced submodels and models.  Also models referenced by
  [Series Pin Mapping] needed to be included. 

  Michael Mirmak had issued a revised BUG49 that addressed these comments.
  He also added that the revise BUG49 discussed issuing only one Warning
  message rather than multiple Warning messages for dangling Models, and
  Warnings for each dangling Submodel.  This would limit the number of
  Warnings for FPGA files.

  As time was running out, Bob planned more discussion and final resolution
  at the January 5, 2001 meeting.


NEXT MEETING:
The next teleconference meeting will be on Friday, January 5, 2001 from
8:00 AM to 10:00 AM.  BIRD65.1 is scheduled for a vote.  Also a vote on a
new IBIS Librarian will be conducted.

==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Open Position

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            angulo@hyperlynx.com
            Development Engineer, HyperLynx, Inc.
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================

 
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
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Subject: BIRD 65.1
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****************************************************************************
**
****************************************************************************
**

BIRD ID#:        65.1
ISSUE TITLE:     C_comp Refinements
REQUESTER:       Arpad Muranyi, Intel
DATE SUBMITTED:  10-25-99, 12-12-2000
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

****************************************************************************
**
****************************************************************************
**

STATEMENT OF THE ISSUE:

Currently, the IBIS specification (v3.2) uses a single constant value for
describing the total die capacitance as seen at the pad.  This value is
given
by the subparameter C_comp under the [Model] keyword.  The specification
does
not mention how this capacitance is distributed between the power and ground
references, or how it should be connected to the circuit.

****************************************************************************
**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Four new subparameters shall be introduced in the IBIS specification under
the [Model] keyword to provide means for a more detailed description for the
die capacitance.  These new subparameters, C_comp_pullup, C_comp_pulldown,
C_comp_power, and C_comp_ground are associated to the corresponding voltage
reference keywords, [Pullup Reference], [Pulldown Reference], [Power Clamp
Reference], and [GND Clamp Reference], respectively.  This mechanism allows
the association of a specific capacitance between the I/O node and the four
possible supply nodes without disturbing the submodel syntax.

The syntax of these four new subparameters are identical to the existing
C_comp subparameter.

|===========================================================================
==
|     Keyword:  [Model] 
|    Required:  Yes.
| Description:  Used to define a model, and its attributes.
|  Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp,
|**             C_comp_pullup, C_comp_pulldown, C_comp_power, and
|**             C_comp_ground Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  The
|               model name must match the one that is listed under a [Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and must
not
|               contain more than 20 characters.  A .ibs file must contain
|               enough [Model] keywords to cover all of the model names
|               specified under the [Pin], [Model Selector] and [Series Pin
|               Mapping] keywords, except for those model names that use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|               Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
|               Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|               Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|               Series, and Series_switch.
|
|               Special usage rules apply to the following.  Some
definitions
|               are included for clarification:
|
|               Input              These model types must have Vinl and Vinh
|               I/O                defined.  If they are not defined, the
|               I/O_open_drain     parser issues a warning and the default
|               I/O_open_sink      values of Vinl = 0.8 V and Vinh = 2.0 V
are
|               I/O_open_source    assumed.
|
|               Input_ECL          These model types must have Vinl and Vinh
|               I/O_ECL            defined.  If they are not defined, the
|                                  parser issues a warning and the default
|                                  values of Vinl = -1.475 V and Vinh =
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only model
|                                  that can have analog loading effects on
the
|                                  circuit being simulated but has no
digital
|                                  logic thresholds.  Examples of
Terminators
|                                  are: capacitors, termination diodes, and
|                                  pullup resistors.
|
|               Output             This model type indicates that an output
|                                  always sources and/or sinks current and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an output
|                                  can be disabled, i.e. put into a high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the
output
|               Open_drain         has an OPEN side (do not use the [Pullup]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SINKS current.  Open_drain model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the output
|                                  has an OPEN side (do not use the
[Pulldown]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the model
|               Output_ECL         represents an ECL type logic that follows
|               I/O_ECL            different conventions for the [Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models that
|                                  can be described by [R Series], [L
Series],
|                                  [Rl Series], [C Series], [Lc Series],
|                                  [Rc Series], [Series Current] and [Series
|                                  MOSFET] keywords
|                                 
|               Series_switch      This model type is for series switch
|                                  models that can be described by [On],
|                                  [Off], [R Series], [L Series], [Rl
Series],  
|                                  [C Series], [Lc Series], [Rc Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords
|
|**             The Model_type subparameter is required.  The C_comp
|**             subparameter is only required if C_comp_pullup,
|**             C_comp_pulldown, C_comp_power, and C_comp_ground are not
|**             present, or the C_comp_pullup, C_comp_pulldown,
|**             C_comp_power, and C_comp_ground subparameters are required
|**             if the C_comp subparameter is not present.
|
|               The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and
Vref
|*              subparameters are optional.  C_comp* define the silicon die
|*              capacitance.  Thse values should not include the capacitance
|*              of the package.  C_comp* are allowed to use "NA" for the min
|               and max values only.  The Polarity subparameter can be
|               defined as either Non-Inverting or Inverting, and the Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the model.
|               The Vmeas subparameter is the reference voltage level that
the
|               semiconductor vendor uses for the model.  Include Cref,
Rref,
|               Vref, and Vmeas information to facilitate board-level timing
|               simulation.  The assumed connections for Cref, Rref, and
Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND
|
| Other Notes:  A complete [Model] description normally contains the
following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND
Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac].  However,
some
|               models may have only a subset of these keywords.  For
example,
|               an input structure normally only needs the [Voltage Range],
|               [GND Clamp], and possibly the [POWER Clamp] keywords.  If
one
|               or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords are
|               used, then the Model_type must be Terminator.
|---------------------------------------------------------------------------
--
| Signals       CLK1, CLK2,...         | Optional signal list, if desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
Vmeas = 1.5V              | Reference voltage for timing measurements
Cref = 50pF               | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
| variable      typ             min             max
C_comp          12.0pF          10.0pF          15.0pF
|
|===========================================================================
==
|
[Model]         Clockbuffer
Model_type      I/O
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
|
| variable      typ             min             max
C_comp_pullup   3.0pF           2.5pF           3.5pF
C_comp_pulldown 2.0pF           1.5pF           2.5pF
C_comp_power    1.0pF           0.5pF           1.5pF
C_comp_ground   1.0pF           0.5pF           1.5pF
|
****************************************************************************
**

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Problem statement

The single (constant) C_comp value of the current IBIS specification (v3.2)
does not provide enough information for the simulator to accurately simulate
high speed signals and/or ground and supply noise.

In order to simulate the signal current return path and/or supply rail noise
(GND bounce and/or Vcc droop) accurately, a model needs to provide more
detail on the distribution of the total die capacitance between the I/O pad,
power and ground references.  This BIRD attempts to provide the means for
incorporating such information in a model.

The existing C_comp subparameter does not specify how it should be connected
between the I/O pad and the supply rails.  Most naturally it will end up
getting connected to the I/O node and ground.  However, since it not only
represents the capacitance of the pulldown device, but also the capacitance
of
the pullup device, one should split it between the I/O pin and ground, and
the
I/O pin and power rails.  One can easily see that this configuration forms a
series combination of two capacitances between power and ground.
Simulations
show a significant difference in the waveforms for the distributed or lumped
capacitance when power and ground nodes of the die are connected through the
package parasitics to the ideal power source(s).

Possible solutions

1)  Specify splitting factor coefficients
2)  Use a new subparameter under each voltage reference keyword
3)  Use a new subparameter under each I-V curve
4)  Use four new subparameters under the [Model] keyword (as presented in
    this BIRD).

****************************************************************************
**

ANY OTHER BACKGROUND INFORMATION:

Changed the names for the four C_comp* parameters as requested in the 
12-08-2000 IBIS Open Forum Teleconference meeting.  Added the next 
paragraph.

Transistors (consequently buffers) show different parasitic capacitance when
turned on or off.  Additional mechanisms need to be added to the IBIS 
specification to account for these variations.

The voltage dependency of the die capacitance should also be addressed at
some
point. (Use typ., min., max, capacitance vs. voltage tables instead of
single
values)?

****************************************************************************
**


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************************************************************************=
******
************************************************************************=
******

BIRD ID#:        65.1
ISSUE TITLE:     C_comp Refinements
REQUESTER:       Arpad Muranyi, Intel
DATE SUBMITTED:  10-25-99, 12-12-2000
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

************************************************************************=
******
************************************************************************=
******

STATEMENT OF THE ISSUE:

Currently, the IBIS specification (v3.2) uses a single constant value =
for
describing the total die capacitance as seen at the pad.  This value is =
given
by the subparameter C_comp under the [Model] keyword.  The =
specification does
not mention how this capacitance is distributed between the power and =
ground
references, or how it should be connected to the circuit.

************************************************************************=
******

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Four new subparameters shall be introduced in the IBIS specification =
under
the [Model] keyword to provide means for a more detailed description =
for the
die capacitance.  These new subparameters, C_comp_pullup, =
C_comp_pulldown,
C_comp_power, and C_comp_ground are associated to the corresponding =
voltage
reference keywords, [Pullup Reference], [Pulldown Reference], [Power =
Clamp
Reference], and [GND Clamp Reference], respectively.  This mechanism =
allows
the association of a specific capacitance between the I/O node and the =
four
possible supply nodes without disturbing the submodel syntax.

The syntax of these four new subparameters are identical to the =
existing
C_comp subparameter.

|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D
|     Keyword:  [Model]=20
|    Required:  Yes.
| Description:  Used to define a model, and its attributes.
|  Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp,
|**             C_comp_pullup, C_comp_pulldown, C_comp_power, and
|**             C_comp_ground Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  =
The
|               model name must match the one that is listed under a =
[Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and =
must not
|               contain more than 20 characters.  A .ibs file must =
contain
|               enough [Model] keywords to cover all of the model names
|               specified under the [Pin], [Model Selector] and [Series =
Pin
|               Mapping] keywords, except for those model names that =
use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|               Input, Output, I/O, 3-state, Open_drain, =
I/O_open_drain,
|               Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|               Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, =
Terminator,
|               Series, and Series_switch.
|
|               Special usage rules apply to the following.  Some =
definitions
|               are included for clarification:
|
|               Input              These model types must have Vinl and =
Vinh
|               I/O                defined.  If they are not defined, =
the
|               I/O_open_drain     parser issues a warning and the =
default
|               I/O_open_sink      values of Vinl =3D 0.8 V and Vinh =
=3D 2.0 V are
|               I/O_open_source    assumed.
|
|               Input_ECL          These model types must have Vinl and =
Vinh
|               I/O_ECL            defined.  If they are not defined, =
the
|                                  parser issues a warning and the =
default
|                                  values of Vinl =3D -1.475 V and Vinh =
=3D
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only =
model
|                                  that can have analog loading effects =
on the
|                                  circuit being simulated but has no =
digital
|                                  logic thresholds.  Examples of =
Terminators
|                                  are: capacitors, termination diodes, =
and
|                                  pullup resistors.
|
|               Output             This model type indicates that an =
output
|                                  always sources and/or sinks current =
and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an =
output
|                                  can be disabled, i.e. put into a =
high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the =
output
|               Open_drain         has an OPEN side (do not use the =
[Pullup]
|                                  keyword, or if it must be used, set =
I =3D
|                                  0 mA for all voltages specified) and =
the
|                                  output SINKS current.  Open_drain =
model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the =
output
|                                  has an OPEN side (do not use the =
[Pulldown]
|                                  keyword, or if it must be used, set =
I =3D
|                                  0 mA for all voltages specified) and =
the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the =
model
|               Output_ECL         represents an ECL type logic that =
follows
|               I/O_ECL            different conventions for the =
[Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models =
that
|                                  can be described by [R Series], [L =
Series],
|                                  [Rl Series], [C Series], [Lc =
Series],
|                                  [Rc Series], [Series Current] and =
[Series
|                                  MOSFET] keywords
|                                =20
|               Series_switch      This model type is for series switch
|                                  models that can be described by =
[On],
|                                  [Off], [R Series], [L Series], [Rl =
Series], =20
|                                  [C Series], [Lc Series], [Rc =
Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords
|
|**             The Model_type subparameter is required.  The C_comp
|**             subparameter is only required if C_comp_pullup,
|**             C_comp_pulldown, C_comp_power, and C_comp_ground are =
not
|**             present, or the C_comp_pullup, C_comp_pulldown,
|**             C_comp_power, and C_comp_ground subparameters are =
required
|**             if the C_comp subparameter is not present.
|
|               The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, =
and Vref
|*              subparameters are optional.  C_comp* define the silicon =
die
|*              capacitance.  Thse values should not include the =
capacitance
|*              of the package.  C_comp* are allowed to use "NA" for =
the min
|               and max values only.  The Polarity subparameter can be
|               defined as either Non-Inverting or Inverting, and the =
Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test =
load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the =
model.
|               The Vmeas subparameter is the reference voltage level =
that the
|               semiconductor vendor uses for the model.  Include Cref, =
Rref,
|               Vref, and Vmeas information to facilitate board-level =
timing
|               simulation.  The assumed connections for Cref, Rref, =
and Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     =3D=3D=3D Cref
|                           |_________|      |
|                                            |
|                                           GND
|
| Other Notes:  A complete [Model] description normally contains the =
following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND =
Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one =
or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac].  =
However, some
|               models may have only a subset of these keywords.  For =
example,
|               an input structure normally only needs the [Voltage =
Range],
|               [GND Clamp], and possibly the [POWER Clamp] keywords.  =
If one
|               or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords =
are
|               used, then the Model_type must be Terminator.
|-----------------------------------------------------------------------=
------
| Signals       CLK1, CLK2,...         | Optional signal list, if =
desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl =3D 0.8V                            | input logic "low" DC =
voltage, if any
Vinh =3D 2.0V                            | input logic "high" DC =
voltage, if any
Vmeas =3D 1.5V              | Reference voltage for timing measurements
Cref =3D 50pF               | Timing specification test load =
capacitance value
Rref =3D 500                | Timing specification test load resistance =
value
Vref =3D 0                  | Timing specification test load voltage
| variable      typ             min             max
C_comp          12.0pF          10.0pF          15.0pF
|
|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D
|
[Model]         Clockbuffer
Model_type      I/O
Vinl =3D 0.8V                            | input logic "low" DC =
voltage, if any
Vinh =3D 2.0V                            | input logic "high" DC =
voltage, if any
|
| variable      typ             min             max
C_comp_pullup   3.0pF           2.5pF           3.5pF
C_comp_pulldown 2.0pF           1.5pF           2.5pF
C_comp_power    1.0pF           0.5pF           1.5pF
C_comp_ground   1.0pF           0.5pF           1.5pF
|
************************************************************************=
******

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Problem statement

The single (constant) C_comp value of the current IBIS specification =
(v3.2)
does not provide enough information for the simulator to accurately =
simulate
high speed signals and/or ground and supply noise.

In order to simulate the signal current return path and/or supply rail =
noise
(GND bounce and/or Vcc droop) accurately, a model needs to provide more
detail on the distribution of the total die capacitance between the I/O =
pad,
power and ground references.  This BIRD attempts to provide the means =
for
incorporating such information in a model.

The existing C_comp subparameter does not specify how it should be =
connected
between the I/O pad and the supply rails.  Most naturally it will end =
up
getting connected to the I/O node and ground.  However, since it not =
only
represents the capacitance of the pulldown device, but also the =
capacitance of
the pullup device, one should split it between the I/O pin and ground, =
and the
I/O pin and power rails.  One can easily see that this configuration =
forms a
series combination of two capacitances between power and ground.  =
Simulations
show a significant difference in the waveforms for the distributed or =
lumped
capacitance when power and ground nodes of the die are connected =
through the
package parasitics to the ideal power source(s).

Possible solutions

1)  Specify splitting factor coefficients
2)  Use a new subparameter under each voltage reference keyword
3)  Use a new subparameter under each I-V curve
4)  Use four new subparameters under the [Model] keyword (as presented =
in
    this BIRD).

************************************************************************=
******

ANY OTHER BACKGROUND INFORMATION:

Changed the names for the four C_comp* parameters as requested in the=20
12-08-2000 IBIS Open Forum Teleconference meeting.  Added the next=20
paragraph.

Transistors (consequently buffers) show different parasitic capacitance =
when
turned on or off.  Additional mechanizms need to be added to the IBIS=20
specification to account for these variations.

The voltage dependency of the die capacitance should also be addressed =
at some
point. (Use typ., min., max, capacitance vs. voltage tables instead of =
single
values)?

************************************************************************=
******

------_=_NextPart_000_01C0649C.60911310--

 
From owner-ibis Mon Dec 18 16:39:30 2000
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Date: Mon, 18 Dec 2000 16:35:00 -0800 (PST)
From: Milt Schwartz x3261 <schwartz@galaxy.nsc.com>
Message-Id: <200012190035.QAA08545@xi.nsc.com>
To: ibis@eda.org
Subject: 2nd Send Agenda, DesignCon 2k1
X-Sun-Charset: US-ASCII

       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       ----------------------------------------------------------------
       DESIGNCON 2001 IBIS SUMMIT CALL FOR PARTICIPATION, PRESENTATIONS
       ----------------------------------------------------------------
       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

                    I B I S   S U M M I T   M E E T I N G

Time/Date:     8:00 PM - 5:00 PM, Monday, January 29, 2001

Location:      Santa Clara Convention Center
               Santa Clara, CA

Content:       IBIS Future Requirements is the main topic of this meeting
               These include an exchange of ideas on IBIS accuracy,
               connectors, and new requirements under discussion.

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      DesignCon 2001 & National Semiconductor Corporation

IBIS Summit Signup:
               Milt Schwartz
               schwartz@galaxy.nsc.com


                   D E S I G N C O N   2 0 0 0   M E E T I N G S

Time/Date:     Monday - Thursday, January 29 - February 1, 2001

Exhibition:    Tuesday - Wednesday, 12:30 PM - 6:30 PM, January 30-31, 2001

IBIS Booth:    #861, Exhibition Hall
               - IBIS Information

URL DesignCon2001:
               http://www.designcon.com/


CALL FOR IBIS SUMMIT PRESENTATIONS

We already have several presentations and discussion topics planned.  However,
we are also seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  If you cannot provide
                         an electronic format, then plan to bring 50
                         copies for distribution at the meeting.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Milt Schwartz
  schwartz@galaxy.nsc.com

Deadline: Wednesday, January 24, 2001 for receiving presentations for
          copying.
 

AGENDA

The agenda includes presentations, discussions, refreshments, and a free
buffet luncheon for participants.  In addition, we will have an opportunity
for Ad Hoc presentations and extended discussions.  Currently we have:

  "Spice 2 IBIS Accuracy Report", Scott McMorrow, Siqual

Milt Schwartz Interface Applications
National Semiconductor
2900 Semiconductor Dr.
Mail Stop A2595
Santa Clara, CA 95052

email: schwartz@galaxy.nsc.com
Phone:  408 721 3261
Fax  :  408 721 4785
 
From owner-ibis Tue Dec 19 07:02:24 2000
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Importance: Normal
Subject: example I/O buffer accuracy report
To: si-list@silab.eng.sun.com
Cc: ibis@vhdl.org, ibis-users@vhdl.org
X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000
Message-ID: <OFBE0FFD07.1104AAA6-ON862569BA.0050B615@RCHLAND.IBM.COM>
From: "Gregory R Edlund" <gedlund@us.ibm.com>
Date: Tue, 19 Dec 2000 09:00:21 -0600
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 12/19/2000 09:00:22 AM
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My colleagues and I have applied the procedures defined in the "I/O Buffer
Accuracy Handbook" to a real life part:  IDT's ALVCH16831 buffer.  We
compared IBIS, SPICE, and lab measurements.  The results look really good.
Of course, we had to use a coupled package model and lossy transmission
lines to make them look this good!  IDT was very cooperative with us; I was
most impressed by their willingness to work together.  They have an
impressive array of SPICE and IBIS model data on their web site, and I
would encourage you to have a look.  Incidentally, this particular I/O
buffer circuit is widely used in IDT's ALVCH family, so the test results
cover a lot of ground.

Why don't you grab a copy of this PDF file and email it to your favorite
semiconductor vendor?  Ask them if they can provide you this kind of data
for their parts!  I'll bet a few of them are doing this sort of thing
already, just in a different format.  We've made a lot of progress in the
model arena over the past few years, but we still have a lot of catching up
to do.

http://www.vhdl.org/pub/ibis/accuracy/

The file name is report.pdf.  Thanks to the IBIS Open Forum for hosting the
web site.  Thanks to all of you out there who contributed to this work.  It
was very much a cooperative effort.

Cheers.

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

 
From owner-ibis Tue Dec 19 07:54:38 2000
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Importance: Normal
Subject: BIRD 69:  Golden Waveforms
To: ibis@eda.org
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Message-ID: <OF3A4BE4F2.110BA6C5-ON862569BA.00529E0C@RCHLAND.IBM.COM>
From: "Gregory R Edlund" <gedlund@us.ibm.com>
Date: Tue, 19 Dec 2000 09:52:35 -0600
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--0__=862569BA00529E0C8f9e8a93df938690918c862569BA00529E0C
Content-type: text/plain; charset=us-ascii

Fellow IBIS people,

Here's a new BIRD related to - you guessed it - accuracy.  Its purpose is
to facilitate the inclusion of "Golden Waveforms" into an IBIS datasheet.
I'm sure a lot of you are on vacation this week, but Bob thought it was a
good idea to send it out anyhow.  Happy holidays to you all.


(See attached file: bird_69.txt)

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
--0__=862569BA00529E0C8f9e8a93df938690918c862569BA00529E0C
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--0__=862569BA00529E0C8f9e8a93df938690918c862569BA00529E0C--

 
From owner-ibis Tue Dec 19 06:43:19 2000
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Importance: Normal
Subject: waveform correlation calculator
To: ibis-users@vhdl.org, ibis@vhdl.org
X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000
Message-ID: <OFE4A26673.3E84DDEC-ON862569BA.00508E0A@RCHLAND.IBM.COM>
From: "Gregory R Edlund" <gedlund@us.ibm.com>
Date: Tue, 19 Dec 2000 08:41:18 -0600
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 12/19/2000 08:41:19 AM
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I have written a C program that is useful for overlaying two waveforms and
quantifying the differences between them.  The program reads two ASCII x-y
data files, slides the waveforms along the time axis until they overlay,
then examines the absolute and relative differences between each data
point.  This is pretty useful when doing I/O buffer model development work
or any simulation vs. lab correlation.

You can get a copy of the C code along with a user guide on the IBIS web
site.

http://www.vhdl.org/pub/ibis/accuracy/

The files are ack.zip and ack.tar.Z.  Instructions for compiling are in the
readme.txt file.  Don't worry about the disclaimer; I got approval from
IBM's lawyers to distribute this source code as freeware.  Hack to your
heart's content.

I tested the code when I wrote the I/O buffer accuracy report on the same
web site.  It worked fine for me, but that's not to say you won't find some
pathological cases that I haven't stumbled upon yet.  If you do, please let
me know so I can improve the algorithm.

Merry Christmas.


Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

 
From owner-ibis Tue Dec 19 10:20:31 2000
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From: "Beal, Weston" <weston_beal@mentorg.com>
To: ibis@eda.org
Subject: RE: BIRD 69:  Golden Waveforms
Date: Tue, 19 Dec 2000 10:16:44 -0800
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Greg,

This looks like a pretty good idea.  I have a question and a suggestion.

Doesn't the golden waveform apply to a driver model like a rising or falling
waveform?  If so, I think the "driver_model" parameter is redundant.

I would suggest a more definitive name for Rp* parameters.  Rp1 could be
Rpower and Rp2 could be Rgnd to be consistent with other IBIS keywords.
This would simplify the job of the IBIS author.

Regards,
Weston

-----Original Message-----
From: Gregory R Edlund [mailto:gedlund@us.ibm.com]
Sent: Tuesday, December 19, 2000 7:53 AM
To: ibis@eda.org
Subject: BIRD 69: Golden Waveforms


Fellow IBIS people,

Here's a new BIRD related to - you guessed it - accuracy.  Its purpose is
to facilitate the inclusion of "Golden Waveforms" into an IBIS datasheet.
I'm sure a lot of you are on vacation this week, but Bob thought it was a
good idea to send it out anyhow.  Happy holidays to you all.


(See attached file: bird_69.txt)

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
 
From owner-ibis Wed Dec 20 08:51:32 2000
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Dear IBIS Gurus,

Under the IBIS spec is it explicit that any [Model] referenced in a [Pin] list
must appear after that reference in the IBIS file?

If yes, shouldn't we expect an error or warning from ibischk3?


Best Regards,


Roy


 
From owner-ibis Wed Dec 20 09:06:58 2000
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Subject: A question about IBIS checker
To: ibis@eda.org
From: wzheng@amis.com
Date: Wed, 20 Dec 2000 10:04:23 -0700
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Dear Sir/Madam:

My name is William Zheng, doing IBIS models for American Microsystems, Inc.
I have a question here about IBIS parser.  If a IBIS model is checked
correctly
by Visual IBIS Editor V2.0, it also should pass under ibischk3 - right or
not?

Thank you very much for your helps.  Happy Holidays!

Best regards,
William Zheng



 
From owner-ibis Wed Dec 20 09:11:49 2000
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From: "Mirmak, Michael" <michael.mirmak@intel.com>
To: "'Roy_Leventhal@3com.com'" <Roy_Leventhal@3com.com>,
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	 <ibis@eda.org>
Subject: RE: [Model] syntax requirement?
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Roy,

I believe this is already "trapped" by ibischk3.  If you reference a [Model]

in a [Pin] list and that [Model] does not appear below it, you should see an
error resembling the following (under v3.2.5):

ERROR - Component 'xxx': Model 'yyy' for Pin 'z' not defined.

Is there a specific example or situation that you have in mind?  If so,
I'm sure that the list would love to see it!

- Michael Mirmak, Intel Corp.

-----Original Message-----
From: Roy_Leventhal@3com.com [mailto:Roy_Leventhal@3com.com]
Sent: Wednesday, December 20, 2000 8:51 AM
To: ibis@eda.org
Subject: [Model] syntax requirement?




Dear IBIS Gurus,

Under the IBIS spec is it explicit that any [Model] referenced in a [Pin]
list
must appear after that reference in the IBIS file?

If yes, shouldn't we expect an error or warning from ibischk3?


Best Regards,


Roy


 
From owner-ibis Fri Dec 29 11:46:31 2000
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                     IBIS Open Forum Meeting Agenda
                              for 1/5/01

                 Bridge Number    Reservation #   Passcode
                 (916) 356-9200   3-454694        8973669

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Ross/Fleming
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  LaBonte, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Ross/Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
          for Integrated Circuits (IMIC)                     Ross
     - IEC PWI 93-1 Models of Integrated Circuits for EMI 
       Behavioral Simulation (formerly designated as
       IEC 93/67/NP IBIS and EMC Simulation)                 Perrin/Ross
     - JEDEC JC-16 Modeling and Testing                      Sessions
    
     Librarian Selection                                     Ross

     DesignCon 2001 IBIS Summit Meeting                      Ross

     Date 2001 IBIS Summit Meeting                           Ross

     IBIS Model Review Committee                             Angulo

     New Administrative Issues                               All

8:45 Technical Discussion (some topics may be deferred)

     Connector Proposal Review                               Panella

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters

     BIRD65 - C_comp Refinements (Vote)                      Muranyi

     BIRD68 - Clarify that Rising and Falling Waveform       Lorang
              Tables Should be Correlated

     BIRD69 - Golden Waveforms                               Edlund

     ibischk3 Bug Tracking                                   Ross

     - BUG49 Warning Message for Unreferenced Models,        Ross/Mirmak
             Submodels - resolution
   
     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Ross

9:55 Sign Off
 
From owner-ibis Fri Dec 29 14:21:26 2000
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From: Al Davis <aldavis@ieee.org>
To: "Muranyi, Arpad" <arpad.muranyi@intel.com>,
   "'ibis@vhdl.org'" <ibis@vhdl.org>
Subject: Re: BIRD 65.1
Date: Fri, 29 Dec 2000 14:18:47 -0800
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I have some questions and reservations on this.  To summarize, although 
I agree that such a thing is needed, this proposal does not solve the 
problem adequately and has the potential for introducing problems that 
have not been considered.  Also, the problem it intends to solve 
becomes a non-issue once IBIS-X is completed.

The first question is how difficult it is to implement.  Ordinarily, I 
would say that it is necessary to prove it with a prototype.  Such a 
prototype can be done trivially in IBIS-X, so on the surface it seems 
that implementation is trivial.

Still, testing is a problem.  How do you measure it?  How do you 
validate that the measured data actually relates to reality?  Before 
approval of this bird, I would like to see a description of a procedure 
for measuring it, and a procedure for validating that the measured data 
is actually correct and useful.  These procedures should be tried on a 
prototype.

The purpose is stated to be information on how the capacitance is 
distributed over the 5 ground/power nodes.  Another way to look at it 
is how the current in the capacitance is distributed.  OK.  Now back 
up.  We have pullup/pulldown and the clamps for the DC conditions.  The 
proposed c_comp's are the dynamic parts.  Existing models usually do 
not model the split of these correctly.  The pullup and power clamp are 
sort of in parallel, so the measurement is usually to measure the 
clamps in input or tri-state mode, and the pullup/pulldown in driving 
mode, by measuring a total and subtracting off the clamps.  This often 
leads to the pullup/pulldown showing strange bahavior when it is masked 
by the clamps, because the subtraction magnifies the errors.  In any 
case, the current path is not necessarily as intended.  The standard 
provides the mechanism to properly model the current paths, but most 
models do not.  They arbitrarily mix them.

Given that most models do not get the DC split correct, what justifies 
even trying for the dynamic part?

The next issue is that this capacitance is strongly nonlinear.  
Measuring it in the various states produces very different results.  
Even then, there is no hint at what they do during the transition, 
other than that the wave tables include the effect.  The wave tables do 
not provide information on how that current is distributed to the 5 
power/ground nodes, and possibly also to other connection nodes 
including input and enable.

The nonlinear nature of this capacitance is significant in the 
development of the simulator algorithms.  Some actual models will only 
work accurately when the capacitance is treated as nonlinear.

Part of this capacitance is already in the standard as transit time.  
The [TT*] parameters are essentially equivalent to the C_comp_power and 
C_comp_ground parts, complete with the nonlinear component.  Thus, part 
of what this bird proposes is already available.  (OK -- the bird asks 
for the linear part.)  Do you have any examples of actual models that 
use these parameters?  with test data showing the quality of 
correlation to the real device?  How many simulators support it fully?  
It has been in the standard for a long time.

Considering the number of unanswered questions, and that this 
functionality and much more will be available in IBIS-X, I think it is 
best not to rush into this.

So, Arpad, you should prototype this in IBIS-X, and also prototype a 
measurement system for it in IBIS-X.  This will validate both this bird 
and IBIS-X.  The rest of us should wait for the answer.

Note to readers not familiar with IBIS-X:  This is a proposed future 
IBIS based on a macro language.  It is fully backward compatible with 
IBIS as we know it, and provides the capability to add extensions like 
this one easily.  Arpad and I are both on the sub-committee that is 
working on it.  A prototype implementation of IBIS-X is being built, 
and a partial one (incomplete work in progress) is available for review 
to the committee and to those interested.
 
