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Date: Tue, 03 Apr 2001 12:59:04 -0700
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DATE: 4/2/01

SUBJECT: 3/30/01 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal*
Agilent                        (Mark Chang)
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Balistreri
Avanti                         (Chen Hongyu)
Brocade Communications         Robert Badal
Cadence Design                 Ian Dodd, Patrick Dos Santos, Heiko Dudek
Cisco Systems                  Syed Huq, Lungfu Chen
Compaq                         Peter LaFlamme, Ron Bellomio, Quang Dam,
                               Bill Ham*
Cypress                        (Rajesh Manapat)
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
IBM                            Michael Cohen, Greg Edlund, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel*
Innoveda (& HyperLynx)         Guy de Burgh, John Angulo, Cary Mandel
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Dave Lorang,
                               Michael Mirmak, Qinglun Chen, Will Hobbs
LSI Logic                      Larry Barnes*
Mentor Graphics                Bob Ross*, Tom Dagostino, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet
Micron Technology              Randy Wolff, Yong Phan
Mitsubishi                     (Tam (Tom) Cao)
Molex Incorporated             Gus Panella, Brian O'Malley
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz*
Nortel Networks                Calvin Trowell
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe
Quantic EMC                    (Mike Ventham)
Robinson-Nugent, Inc.          (Alexander Barr)
Siemens (& Automotive) AG      Bernhard Unger, Helmut Katzier, Katja Koller,
                               Wolfram Meyer, Eckhard Lenski, Gerald Bannert,
                               Burkhard Muller, Christian Marot,
                               Manfred Maurer, Amir Motamedi,
                               Hans Pichlmaier
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
BMW                            Friedrich Hasinger
Cereva Networks                Bob Haller
EADS Airbus Industry           Claude Huet
  (Aerospatiale)
EFM                            Ekkehard Miersch, Horle Raines
EIA                            Cecilia Fleming*
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Huawei Technologies            Rachild Chen
Hyundai Electronics            Jongho Kang
Infineon Technologies          Christian Sporrer
Intrinsix Corporation          Steven Chin
National Institute of Applied  Etienne Sicard
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Sintecs                        Hans Klos
STMicroelectronics             Peter Hirt, Fabrice Boissieres
Sun                            Adrian Udenze
Xilinx                         Susan Wu
Independent, Consultant        Al Davis*

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  April 20, 2001      (916) 356-9200   2-524674         3881934

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum, and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS AND MEETING QUORUM
Bill Ham is an interconnect architect at Compaq.  He has a long term interest
in modeling and has been involved with the t10 committee on SCSI issues and
on the t11 committee on fiber channel issues.  Bill is interested in common
methodologies and in launch signals that vary with the data pattern.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross is expecting the final year 2000 financial report per a conversation
with Cecilia Fleming.  Also, Bob estimates that we have about 25 paid members
this year.  Cecilia plans to mail reminder invoices, and Bob will work with
her regarding some new addresses.


REVIEW OF MINUTES AND AR'S
The March 2, 2001 IBIS Minutes were approved without change.

The March 16, 2001 European IBIS Summit Meeting Minutes were approved with the
following corrections reported by Bob Ross:

The presentation title by Etienne Sicard was corrected to:

  EMC MODEL FOR PREDICTION OF PARASITIC EMISSION

and the co-author is corrected to Claude Huet for the presentation by Jean
Claude Perrin:

  INTEGRATED CIRCUITS MODELING, ICEM, INTEGRATED CIRCUITS ELECTROMAGNETIC
  MODEL, PROPOSAL: IEC62014-3

The corrected version of the minutes will be uploaded.

The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Bob Ross reported that IBIS and the IBIS Accuracy Report was mentioned in the
March 2001 issue of Printed Circuit Design, "Ensuring Signal Integrity in
Microprocessor Motherboards and Memory" by Dima Smolyansky, pp. 18 - 24.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Roy Leventhal reported that he updated the links of the IBIS Models page and
plans to do some more corrections.  Bob Ross stated that anyone who finds any
problems should notify Roy.


OPENS FOR NEW ISSUES
Bob Ross - BUG55 - Control-Z Can be Used as End-of-File


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 3.2) - Bob Ross reported that we are waiting for
vote on the FDIS (Final Draft International Standard).  It is expected to
close on April 13, 2001.  If the vote is successful, then IBIS Version 3.2 can
be published as an official international standard.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
(IMIC) - No report.

- IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) -  Jean Claude Perrin
  reported that IEC 62014-3, a technical report is expected to take two to
  three months for balloting.  In the mean time, the Committee is working on
  a Cookbook to provide measurement methods to get the necessary parameters if
  they are not provided by semiconductor manufacturers.  Jean Claude will send
  information by e-mail to Bob Ross.  Bob asked Jean Claude if it was OK to
  download the document under consideration by IEC and put it on the IBIS FTP
  site for review.  Jean Claude thought this would be all right.  Jean Claude
  also stated that he seeks more participation in the Committee.

- JEDEC JC-16 - Modeling and Testing - No report.

- T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the
  National Committee for Information Technology (NCITS)) - Larry Barnes
  reported that the next meeting will be held April 2-4, 2001 in Massachusetts,
  and the following meeting will be in June or July in Connecticut.  The SCSI
  Signal Modeling (SSM) Technical Report should be closed at that time.  A
  new version of the document will be uploaded by Monday, April 1, 2001 and
  can be found under:

  http://www.t10.org/ssm.htm

or directly at:

  ftp://ftp.t10.org/drafts/ssm/ssm-r03.pdf

It contains references to the IBIS Cookbook and credits Stephen Peters for his
work.  Bob Ross indicated that he has made some editorial comments.

Bill Ham initiated a technical discussion, which we conducted at this time
since Larry had to leave early.  Bill outlined the technical challenge that
the launch signal strengths depend on the data pattern.  Currently there are
two levels (strong and weak), but more levels could be generated.

Larry commented that the SCSI technology calls for differential current source
drivers.  Each side might be considered to have two drivers for full strength,
but the second driver switches from a source to a sink if a second successive
bit occurs.  A fallback mechanism would describe this effect.  The driver
switches direction rather than just turns off (as Bob had suggested in private
e-mail to Larry).  The [Driver Schedule] keyword could describe this, but the
SCSI Committee needs this description for typ, min and max conditions.

Al Davis suggested working with the IBIS Futures committee so that a proper
model type could be described.  Larry will do this.  Stephen Peters will
provide Larry with the meeting information.  Bob indicated that we should
still investigate this through the BIRD process and target it for an IBIS
Version 4.0 release.  The actual implementation might still be through the
macro language and a Version 4.0 template.


DATE 2001 EUROPEAN IBIS SUMMIT MEETING FEEDBACK
Bob Ross asked for comments.  Bob stated that we had a lot of presentations,
but we managed to get the key information presented and still have some
questions and discussions after each one.

Bob thanked Syed Huq for uploading Acrobat .pdf versions of the Power Point
presentations.

Arpad Muranyi commented that the presentations were high quality.  Some
interesting new ways to use the IBIS data files were given.  Arpad felt that
some advances need to be considered for IBIS-X implementation.


DESIGN AUTOMATION CONFERENCE 2001 IBIS SUMMIT MEETING PLANS
Bob Ross outlined the general plans for the next IBIS Summit Meeting.  The
annual meeting is held along with the Design Automation Conference (DAC).
This year it is in Las Vegas, Nevada.  The IBIS Summit Meeting will be held
in the Hilton Hotel adjacent to the Las Vegas Convention Center.  It is
scheduled for Thursday, June 21, 2001, the day after the trade show portion of
DAC.  This meeting is sponsored by the IBIS Open Forum through the dues, and
Bob will ask Guy de Burgh to coordinate the local arrangements.

Bob stated that we hold election of IBIS officers.  Elections are open to
anyone, and nominations will be accepted at the meeting.  However, Bob would
also like to find out who is interested in serving so we can announce the
candidates several meetings before the DAC IBIS Summit Meeting.

In addition, we will plan to have presentations and discussions.  We will
probably have sessions on:

  Connector Specification
  IBIS-X
  IBIS Version 4.0 Issues
  Possibly other topics such as enhanced buffer extraction

Roy Leventhal stated that he will probably give a presention at the IBIS
Summit Meeting in September in Massachusetts.


IBIS MODEL REVIEW COMMITTEE DISCUSSION
Bob Ross reported that IBIS models from AMD and UTMC have been sent out by
John Angulo for review.


CONNECTOR PROPOSAL REVIEW
Bob Ross stated that he had planned to start the Connector Specification
review at this meeting, but did not have time to prepare for it.  He plans to
have another Connector Working Group Meeting on April 3, 2001 to consider more
cleanup of the document.  The first review will now be planned for the next
meeting and expected to focus on the Header section.  It should be aligned
with the IBIS-X document header.

Al Davis has started to prototype the Specification, but has uncovered some
technical issues.  He will bring them up to the Connector Working Group.  Bob
asked for some details off line.  Al may discuss this at the Connector
Working Group meeting.


IBIS FUTURES (IBIS-X, API, BIRDxx)
Stephen Peters summarized the discussions of the March 20, 2001 Working Group
meeting.  The Working Group is ready to release to the Open Forum the top
level specification.  A component section similar to that in IBIS Verison 3.2
has been added, but with some editorial changes to fit better with the IBIS-X
structure.

Stephen reported that the formal documentation of the macro-language still
needs to be done.  Also, the library guide needs to be written.

The IBIS Futures Working Group wants to work with the Connector Working Group
to insure the documents are compatible.  The next IBIS Futures Working Group
meeting is scheduled for April 3, 2001 and every two weeks thereafter.


BIRD69.1 - GOLDEN WAVEFORMS
Bob Ross suggested withdrawing BIRD69.1 since BIRD70 was issued to cover the
same functions.  The BIRD69.1 author, Greg Edlund, favors moving forward with
BIRD70.  Bob called for a vote on BIRD69.1

BIRD69.1 was rejected by Unanimous Vote


BIRD70 - GOLDEN WAVEFORMS
Al Davis introduced BIRD70 since Greg Edlund could not attend this meeting.
BIRD70 contains some syntactical revisions to make it fit better with the
IBIS-X macro language.  It separates the testing portion of an IBIS model
from the existing model portion used for electrical characterization.  BIRD70
(and a future BIRD70.1) propose that the golden waveform information be located
under a [Test Data] and [Test Load] keyword, not under the [Model] keyword as
was proposed in BIRD69.1.

(In BIRD70, the waveforms are still under the [Rising Waveform] and [Falling
Wave] keywords.)  Al and Bob Ross commented on a few points and also stated
that some BIRD70.1 changes were already planned.  Bob wanted the detailed
discussions to be conducted after BIRD70.1 is issued.

Al commented that he did not like listing default [Test Load] values.  Bob
agreed.  If the sub-parameter is missing, the defaults should be automatically
set to open for shunt elements, and short for series elements.  Transmission
lines without the Td subparameter value would be assumed to be shorted.  The
default voltage might be an issue, but BIRD70.1 should provide a solution.

Bob stated that Greg Edlund plans to issue BIRD70.1.  Some editorial changes
might be given to Greg beforehand.  BIRD70.1 will add a subparameter to name
the Driver model.  It will describe the equivalent package model directly, if
used L, C, and R subparameters.

AR - Greg Edlund issue BIRD70.1 with planned revisions and other submitted
changes.


OTHER PENDING BIRDS
Bob Ross commented that the Fallback Submodel BIRD had been discussed earlier
as part of the SCSI t10 report.  There is still needed for this BIRD to
describe the dynamic output control functionality.

Two other BIRDs include one proposal for PCI thresholds, and one for
simultaneous Switched Outputs (SSO).


IBISCHK3 BUG TRACKING
Bob Ross stated that Matthew Flora provided fixes to BUG53 and BUG34.  The
fixes have been included in a new ibischk3 Version 3.2.7.  No other fixes were
done so that the new executable could be released soon.  Prior to the new
Version, ibischk3 incorrectly issued Warnings for correct *Open* IBIS models.

Matthew generated new source code and distributed it to the companies that
had purchased source code licenses.  Matthew also generated the Windows
executable.  Guy de Burgh generated executables for Unix systems.  Bob stated
that the new executables are uploaded:

  http://www.eda.org/pub/ibis/ibischk3/

The older Verison 3.2.5 and Version 3.2.6 executables are archived under this
directory.  Bob expects Syed Huq to generate and upload the new executables
for Linux.

- BUG54 - Corners with NA give Bad Test Load Warnings
  Because Michael Mirmak could not attend this meeting, and because Bob needed
  to consider how to implement BUG54, Bob decided to postpone the discussion
  on how to resolve BUG54 until the next meeting.  Bob commented that BIRD54
  had been modified in response to comments from the March 2, 2001 IBIS
  meeting.

- BUG55 - Control-Z Can be Used as End-of-File (new agenda item)
  Bob Ross introduced BUG55, authored by Matthew Flora.  BUG55 describes a
  situation that in older DOS and Windows based file, a control-Z can serve
  as an End-of-File character.  Sometimes these characters are incorrectly
  inserted within a file.  If they exist, further ibischk3 processing of the
  file is terminated.  The resolution is to set a flag to read Windows files in
  binary mode.  Then incorrect characters such as control-Z can be detected in
  in a file in the same manner that they are now detected in Unix operating
  systems.

  Al Davis had some questions.  Bob suggested reviewing BUG55 which is now
  uploaded under

    http://www.eda.org/pub/ibis/bugs/ibischk/

  to get a more precise description of the technical details.

  Bob classified BUG55 as Annoying, Low, Open.  The plan is to fix it, unless
  some technical concerns are uncovered.


NEXT MEETING:
The next teleconference meeting will be on Friday, April 20, 2001, from
8:00 AM to 10:00 AM.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            stephen.peters@intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            roy_leventhal@3com.com
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            jangulo@innoveda.com
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================


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From owner-ibis Wed Apr 11 07:25:14 2001
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Subject: A question for IBIS data
To: <ibis@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Wed, 11 Apr 2001 10:21:39 -0400
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Moo-yeul,

The voltages in the V-t waveforms represent the output voltages of the DUT.
The node these voltages are taken from is the output node.  The question is
what were the loading conditions in which the data was taken and did it
include package parasitics.  The sub-parameters:

L_fixture, R_fixture, V_fixture, C_fixture

specify the loading conditions in which the V-t data was taken.  The
sub-parameters:

L_dut, R_dut, C_dut

specify the package parasitics that are included in the V-t data taken.

If the above subparameters are not included in the IBIS datasheet then the
V-t data was taken at a node that does not include packaging or a load.
The effect of c_comp is included in the V-t data.

See pgs42-44 of the 3.2 spec.

Adam Tambone



 
From owner-ibis Thu Apr 12 17:39:52 2001
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		     IBIS Open Forum Meeting Agenda
			      for 4/20/01

		 Bridge Number    Reservation #   Passcode
		 (916) 356-9200   2-524674        3881934

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Ross

     - Intros of New IBIS Participants, Meeting Quorum       Ross
     - Membership Update and Treasurers Report               Ross/Fleming
     - Review of Previous Meeting's Minutes (and ARs)        Ross
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Ross/Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
	  for Integrated Circuits (IMIC)                     Ross
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Ross
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     DAC 2001 IBIS Summit Meeting Planning                   Ross

     IBIS Model Review Committee                             Angulo

     New Administrative Issues                               All

8:30 Technical Discussion (some topics may be deferred)

     Connector Proposal Review                               Panella/Ross

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters

     BIRD70 - Golden Waveforms                               Edlund

     Other Pending BIRDS                                     Ross

     ibischk3 Bug Tracking                                   Ross

     - BUG54 - Corners with NA Give Bad Test Load Warnings   Mirmak

     - BUG56 - Parser Fails to Detect Always Flowing Current Flora

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Ross

9:55 Sign Off
 

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Subject: Re: A question for IBIS data
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Hello Moo-yeul:

The waveform is taken at the junction of the _dut and _fixture
parameters if the _dut parameters exist. Otherwise, it is taken
at the output node directly.

Bob Ross
Mentor Graphics


ÃÖ¹«¿­ wrote:
> 
> Hello,
> 
>  My name is Moo-yeul Choi, the graduate student of Kyungpook National
> University, KOREA.
> I have studied the IBIS to SPICE modeling and have a question about rising and
> falling waveform. I know that the waveform parameter is time-voltage data but
> I don't understand where the voltages are measured. Specially, when the DUT
> parameter exist, I like to know the node measured.
>  I am looking foward to your reply, thank you.
> Have a nice day.
> 
> Best regards,
> Moo-yeul Choi
 
From owner-ibis Mon Apr 16 08:49:08 2001
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Subject: BIRD 70.1
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Here is BIRD 70.1 for discussion at Friday's Open Forum conference call.
After discussion with Bob Ross and Al Davis, I made some significant
changes that should make it upwardly compatible.  Please note that this
BIRD sets up the infrastructure for a future BIRD to facilitate non-RC
standard loads.  In fact, that BIRD becomes almost trivial.

I have two questions for readers:

1) Semiconductor vendors:  If your customers require you to supply Golden
Waveforms and IF a production-quality SPICE-to-IBIS modeling tool were
available to support them, would this BIRD enable you to do so?

2) EDA vendors:  If your customers asked you to support automated analysis
of Golden Waveforms and produce a correlation figure of merit table, would
this BIRD enable you to do so?

Thanks for your consideration everyone!

Greg

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


*******************************************************************************
*******************************************************************************

BIRD ID#:      70.1
ISSUE TITLE:   Golden Waveforms
REQUESTOR:     Greg Edlund, IBM

DATE SUBMITTED:                       April 16, 2001
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

*******************************************************************************
*******************************************************************************

STATEMENT OF THE ISSUE:

Golden Waveforms are a set of SPICE waveforms simulated using known ideal
test loads.  They are useful in verifying the accuracy of behavioral
simulation results for any given simulator.  They are not the same thing as
the traditional VT tables recommended in the "IBIS Cookbook."  The "I/O
Buffer
Accuracy Handbook" recommends a set of ideal test loads for classical
push-pull and open-drain drivers.

There is currently a problem with including Golden Waveforms in an IBIS
datasheet: the simulator tries to use these waveforms to construct its
stimulus waveform, and erroneous simulations result.

This BIRD proposes a new syntactical construct to tell the simulator
that a waveform is a Golden Waveform.  The simulator may then choose to
ignore the data or (better yet) run a set of simulations using the network
and circuit parameters provided and report the correlation between the
simulation results and the Golden Waveforms.  The mechanism for describing
a Golden Waveform involves two new keywords whose scope is global:
[Test Load] and [Test Data].  Under the [Test Data] keyword are two new
keywords whose scope is local:  [Rising Golden Waveform] and
[Falling Golden Waveform].

[Test Load] is a description of a test load network that may be referenced
by any Golden Waveform under the [Test Data] keyword.  [Test Data] is a
marker keyword that indicates the beginning of a group of Golden Waveforms.


*******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

|=============================================================================
|    Keywords:  [Test Data]
|    Required:  No
| Description:  Indicates the beginning of a pair of Golden Waveforms
|               and references the conditions under which they were
derived.
|               An IBIS file may contain any number of [Test Data] sections
|               representing different driver and load combinations.
|
|  Sub-Params:  Test_data_type, Driver_model, Test_load, Test_point,
|               T_period, T_meas, V_meas
|
| Usage Rules:  The name following the [Test Data] keyword is required.
|               It allows a tool to select which data to analyze.
|
|               The Test_data_type subparameter is required, and its value
|               must be either "single_ended" or "differential."
|
|               The Driver_model subparameter is required.  Its value
|               specifies the "device-under-test" and must be a valid
[Model]
|               name.
|
|               The Test_load subparameter is required and indicates which
|               [Test Load] was used to derive the Golden Waveforms. It
must
|               reference a valid [Test Load] name.
|
|               The Test_point subparameter is optional.  It indicates
which
|               node in the test load network the Golden Waveforms
represent.
|               The legal values for Test_point are "near" and "far."  If
|               Test_point is not specified, it defaults to "far."
|
|               The T_period subparameter is optional.  In the case that
the
|               Golden Waveforms represent more than one rising or falling
|               edge, the T_period subparameter tells the simulator the
|               period between rising or falling edges.  This subparameter
|               is useful when constructing a test load in which a
reflection
|               from the first edge hits the driver during the second edge.
|
|               The T_meas subparameter is optional.  It captures the time
|               at which the standard load crosses the threshold specified
|               in the component datasheet during a SPICE simulation.  This
|               subparameter is useful when correlating timing intervals
|               between SPICE and behavioral simulations.  It defines the
|               beginning of a timing interval.
|
|               The V_meas subparameter is optional and is also used to
|               perform timing interval correlation.  The end of a timing
|               interval is defined as the time when a Golden Waveform or
|               a behavioral waveform crosses V_meas.
|
|               A timing interval in a behavioral waveform begins when
|               the waveform crosses V_meas defined in the [Model] keyword
|               while driving C_ref and R_ref, i.e. the standard load
defined
|               in the component datasheet.  Note that there are two
|               DIFFERENT V_meas subparameters in IBIS:  one associated
with
|               [Model] and one associated with [Test Data].
|
|-----------------------------------------------------------------------------
[Test Data] Data1
Test_data_type single_ended
Driver_model Buffer1
Test_load Load1
Test_point far
T_period = 10ns
| variable      typ             min             max
T_meas          1.0ns           0.5ns           1.5ns
V_meas          0.75V           0.75V           0.75V
|
|=============================================================================
|    Keywords:  [Rising Golden Waveform], [Falling Golden Waveform]
|    Required:  Yes (within the scope of [Test Data])
| Description:  Describes the shape of the rising and falling Golden
|               Waveforms of a given driver and a given [Test Load].
|               A model developer may use the [Rising Golden Waveform] and
|               [Falling Golden Waveform] keywords to document Golden
|               Waveforms whose purpose is to facilitate the correlation of
|               SPICE and behavioral simulations.
|
|  Sub-Params:  None.
|
| Usage Rules:  The process, temperature, and voltage conditions under
which
|               the Golden Waveforms are generated must be identical to
those
|               used to generate the VI and VT tables. The Golden Waveforms
|               must be generated using unpackaged driver and receiver
models.
|               The simulator must NOT use the Golden Waveform tables in
the
|               construction of its internal stimulus function.
|
|-----------------------------------------------------------------------------
|
[Rising Golden Waveform]
| Time            V(typ)              V(min)              V(max)
   0.0000s       25.2100mV           15.2200mV           43.5700mV
   0.2000ns       2.3325mV           -8.5090mV           23.4150mV
   0.4000ns       0.1484V            15.9375mV            0.3944V
   0.6000ns       0.7799V             0.2673V             1.3400V
   0.8000ns       1.2960V             0.6042V             1.9490V
   1.0000ns       1.6603V             0.9256V             2.4233V
   1.2000ns       1.9460V             1.2050V             2.8130V
   1.4000ns       2.1285V             1.3725V             3.0095V
   1.6000ns       2.3415V             1.5560V             3.1265V
   1.8000ns       2.5135V             1.7015V             3.1600V
   2.0000ns       2.6460V             1.8085V             3.1695V
| ...
  10.0000ns       2.7780V             2.3600V             3.1670V
|
[Falling Golden Waveform]
| Time            V(typ)              V(min)              V(max)
   0.0000s        5.0000V             4.5000V             5.5000V
   0.2000ns       4.7470V             4.4695V             4.8815V
   0.4000ns       3.9030V             4.0955V             3.5355V
   0.6000ns       2.7313V             3.4533V             1.7770V
   0.8000ns       1.8150V             2.8570V             0.8629V
   1.0000ns       1.1697V             2.3270V             0.5364V
   1.2000ns       0.7539V             1.8470V             0.4524V
   1.4000ns       0.5905V             1.5430V             0.4368V
   1.6000ns       0.4923V             1.2290V             0.4266V
   1.8000ns       0.4639V             0.9906V             0.4207V
   2.0000ns       0.4489V             0.8349V             0.4169V
| ...
  10.0000ns       0.3950V             0.4935V             0.3841V
|
|=============================================================================
|    Keywords:  [Test Load]
|    Required:  No
| Description:  Defines a generic test load network and its associated
|               electrical parameters for reference by Golden Waveforms
|               under the [Test Data] keyword.  The Golden Waveform
|               tables access a given [Test Load] by the value of the
|               Test_load subparameter under the [Rising Golden Waveform]
|               and [Falling Golden Waveform] keywords.
|
|  Sub-Params:  Test_data_type, C1_near, Rs_near, Ls_near, C2_near,
Rp1_near,
|               Rp2_near, Td, Zo, Rp1_far, Rp2_far, C2_far, Ls_far, Rs_far,
|               C1_far, V_term1, V_term2, Receiver_model, R_diff_near,
|               R_diff_far.
|
| Usage Rules:  The value of the Test_data_type subparameter must be either
|               "single_ended" or "differential."
|
|               The subparameters specify the electrical parameters
|               associated with a fixed generic test load.  The diagram
|               below describes the single_ended test load.
|
|               All subparameters except Test_data_type are optional.
|               If omitted, series elements are shorted and shunt elements
|               are opened by default.
|
|
|                                    V_term1
|                                 o-----------o
|                                 |           |
|                                 \           \
receiver_model_name
|   ______                        /           /
______
|  |      |  NEAR        Rp1_near \           \ Rp1_far          FAR  |
|
|  | |\   |                       /           /                       | |\
|
|  | | \  |   Rs_near  Ls_near    |   _____   |     Ls_far  Rs_far    | | \
|
|  | |  >-|---o--/\/\--@@@@--o----o--O_____)--o----o--@@@@--/\/\--o---|-|
> |
|  | | /  |   |              |    |   Td      |    |              |   | | /
|
|  | |/   |   | C1_near      |    \   Zo      \    | C2_far       |   | |/
|
|  |______|  ===            ===   /           /   ===            ===
|______|
|             |      C2_near |    \           \    |       C1_far |
|             |              |    /           /    |              |
|             |              |    |  V_term2  |    |              |
|             o--------------o    o-----------o    o--------------o
|             |                Rp2_near    Rp2_far                |
|            GND                                                 GND
|
|
|               If the Td subparameter is present, then the Zo subparameter
|               must also be present.  If the Td subparameter is not
present,
|               then the simulator must remove the transmission line from
|               the network and short the two nodes to which it was
|               connected.
|
|               V_term1 defines the termination voltage for parallel
|               termination resistors Rp1_near and Rp1_far.  This voltage
|               is not related to the [voltage range] keyword.
|               V_term2 defines the termination voltage for parallel
|               termination resistors Rp2_near and Rp2_far.
|
|               Receiver_model is optional and indicates which, if any,
|               receiver is connected to the far end node. If not used, the
|               network defaults to no receiver.
|
|               If Test_load_type is differential, a the test load is a
|               pair of the above circuits.  If the R_diff_near
subparameter
|               is used, it is connected between the near nodes of the two
|               circuits.  If the R_diff_far subparameter is used, it is
|               connected between the near nodes of the two circuits.
|
|-----------------------------------------------------------------------------
|
[Test Load] Load1
Test_load_type single_ended
C1_near     = 1p
Rs_near     = 10
Ls_near     = 1n
C2_near     = 1p
Rp1_near    = 100
Rp2_near    = 100
Td          = 1ns
Zo          = 50
Rp1_far     = 100
Rp2_far     = 100
C2_far      = 1p
Ls_far      = 1n
Rs_far      = 10
C1_far      = 1p
R_diff      = 100
Receiver_model Input1
| variable      typ             min             max
Vterm1          1.5             1.4             1.6
Vterm2          0.0             0.0             0.0
|
| Example Transmission Line and Receiver test load from "I/O Buffer
Accuracy
| Handbook," section 3.4.4.
|
[Test Load] Tline_rcv
Td          = 1n
Zo          = 50
Receiver_model Input1
|-----------------------------------------------------------------------------

*******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Please refer to BIRD 69.1 for history.  BIRD 70 came about a result of an
attempt to make BIRD 69.1 upwardly compatible with IBIS-X.  BIRD 70 is
actually more compact and efficient because it allows multiple models to
access the same [Test Load].  Recommendations came from Bob Ross, Al Davis,
and the IBIS Open Forum, 3/2/01.

Changes between BIRD 69.1 and BIRD 70:

1. Scope of the "generic test load" is now global rather than being
   local to a particular model.  This is a big improvement.

2. Added one subparameter, Golden_test_load, to [Rising Waveform],
   [Falling Waveform] keywords.  Added text to describe new the
subparameter.
   The Golden_test_load subparameter calls a [Test Load].

3. Exported all the other code to the new [Test Load] keyword.

4. Removed T_ref subparameter. To do timing correlation, the simulator can
   pick a point on the 50 Ohm VT waveform as its "SPICE reference point"
and
   then simulate both the 50 Ohm load and the Golden_test_load to calculate
   a time difference.

5. Removed Pkg_pin parameter. It is too complicated. The user can model a
   simple single-pin lumped circuit using the parameters supplied.

6. Added Tline_present subparameter. If not used, the Tline should be
   removed from the simulation rather than assigned a very small delay
value.
   This prevents the simulator from taking ridiculously small time steps.

7. Replaced V_termxxx with tables similar to the dV/dt_x subparameters.
   This makes the BIRD more economical.

8. Got rid of the paragraph that read, "Using the Golden Waveform
tables..."
   This seemed to be redundant.

9. Specified which parameters are optional and which are required.


Changes between BIRD 70 and BIRD 70.1:

 1. Moved the Golden Waveforms OUT of the [Model] scope and under the
    scope of a new keyword, [Test Data].

 2. Changed [Rising Waveform] to [Rising Golden Waveform].
    Changed [Falling Waveform] to [Falling Golden Waveform].

 3. Added subparameter Driver_model under [Rising Golden Waveform] and
    [Falling Golden Waveform].  This is necessary because the waveforms
    are now outside the scope of the [Model].

 4. Changed the subparameter Golden_test_load to Test_load.

 5. Added the V_meas subparameter to indicate where timing correlation
    measurements should begin and end.

 6. Added subparameters Test_data_type and Test_load_type to facilitate
    upward compatibility with future versions of IBIS.

 7. Removed Tline_present subparameter in favor of language explaining
    that the simulator should remove the Tline if Td is not present.

 8. Moved Driver_model, Test_load, V_meas under the scope of [Test Data].

 9. Added T_meas subparameter to facilitate timing correlation.

10. R_diff became R_diff_near and R_diff_far.

11. Added T_period subparameter to allow multi-cycle correlation in the
    case where a reflection hits the driver while it is switching.

BIRD 70.1 adds 205 lines of code to IBIS, of which 162 are comments.

*******************************************************************************

ANY OTHER BACKGROUND INFORMATION:


See BIRD 69.1.

*******************************************************************************


 
From owner-ibis Mon Apr 16 10:15:40 2001
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From: "Reid, Chris" <chris_reid@mentorg.com>
To: "'ibis@vhdl.org'" <ibis@vhdl.org>
Subject: Reduced strength drivers and Driver Schedules
Date: Mon, 16 Apr 2001 10:13:58 -0700
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Hello,

At the IBIS summit meeting in January Larry Barnes indicated the need for
IBIS support
of the SCSI drivers which reduce their drive strength when the same bit
value is held for
more than one bit period.  This can be accomplished with the current driver
schedule,
and can be made a little more robust by adding a new (previously illegal)
schedule
with a change in the interpretation.  It is easiest to explain with an
example.

As I understand it the driver can be modeled as two stages.
Both stages are on for the first bit, then only one of them if the next bit
is the same as
the previous bit.  For example, if the bit pattern is:

0 1 1 1 0 1 0 0 0

Then the pattern for the two drivers should be:

0 1 1 1 0 1 0 0 0 (the primary driver has the same bit pattern as above.)
1 1 0 0 0 1 0 1 1 (the secondary driver helps only when the bit sense
changes.)

(here I'm assuming the initial bit value (0) has been held for at least one
previous bit period.)

For example, if the primary driver is 50 ohm and the secondary driver is 100
ohm
then the combined driver has four states:

Ls: Both pulling low: (1/(1/50 + 1/100)) = 33.333 ohms pulling low
Lw: 100 ohms high and 50 ohms low
Hw: 100 ohms low and 50 ohms high
Hs: Both pulling high

So the combined two drivers in the above case are in the states:

Lw Hs Hw Hw Ls Hs Ls Lw Lw
(0   1   1    1    0   1   0   0   0)

For simplicity assume the bit period is 5 ns (in actuality its 6.25 ns).
Then
a driver schedule as follows will produce the desired states:

MS1:
Driver      Rise-On  Rise-Off   Fall-On  Fall-Off
d50Ohm      0           NA           0          NA
d100Ohm    NA         5ns          NA        5ns

The initial state is obtained by assuming the driver has been in that state
for
a long time.  For example, suppose the simulation starts with the driver
low.
Then we assume that a long time ago there was a falling transition.  This
means that d50Ohm is in the low state and d100Ohm is in the high state
(because a "long time" is more than 5 ns.)

Remember, the Fall-Off delay is when the driver is supposed to make a
rising transition relative to the falling edge.  Similarly a Rise-Off delay
is
when the driver is supposed to make a falling transition relative to the
rising edge.  Thus the d100Ohm driver switches exactly opposite to the
d50Ohm driver but with a 5ns delay.

If each bit period is 5 ns then a little work will convince you that the
above
driver schedule will produce the sequence of states given above as the
desired sequence for the example bit pattern.

There is another way to accomplish almost the same thing, but with more
flexibility and some differences as will be explained below.  Consider the
driver schedule:

MS2:
Driver      Rise-On  Rise-Off   Fall-On  Fall-Off
d50Ohm      0           NA           0          NA
d100Ohm    0           5ns          0          5ns

This schedule is not legal in IBIS 3.2.  The reason is that it calls for a
falling
transition (fall-on delay equal to zero) when the driver may already be low
because of the 5ns rise-off delay!  However, there is a simple way to use
this
schedule.  If the schedule says to transition low when the device is already
low, just stay there.  Similarly, if it says to transition high when it is
already
high, just leave the device high.

With this understanding the second driver schedule (MS2) produces exactly
the
same result as the first one (MS1) in the case where every bit period is
5ns.  The
difference is that MS2 also allows other possibilities which may
be interesting for some devices.  It also behaves differently if some bits
are held
for less than 5ns.  For example, consider driving these two schedules with a
pulse train defined as:

Start Low (assume it has been low for a long time)
Then transition at the times: 0ns 4ns

Then MS1 produces the states:
Lw if t < 0
Hs if 0 <= t < 4ns
Lw if 4ns <= t < 5ns
Ls if 5ns <= t < 9ns
Lw if 9ns <= t

But MS2 produces the states:
Lw if t < 0
Hs if 0 <= t < 4ns
Ls if 4ns <= t <= 9ns
Lw if 9ns <= t

The difference is that MS1 is in state Lw from 4ns to 5ns while
MS2 is in state Ls for that time period (the low transition starts
at 4ns.)  The reason for this difference is the MS2 schedules d100Ohm
to transition low at time 5ns because of the master rising transition at
time 0.
It also schedules a falling transition at time 4ns because of the master
falling
transition at time 4ns.  Thus the transition occurs at 4ns and when the 5ns
transition is reached d100Ohm is already in the low state so there is
nothing to do.

Thus the MS2 version may be better than the MS1 version because:
1) It responds better to over clocking (the 4ns transition example.)
2) It is more flexible.

On the other hand, MS1 requires no change to IBIS so can be used now.  Note
that the change to make MS2 usable would not involve a new syntax, just a
new
way to use the driver schedule when all four transitions are specified.

Interested parties please respond.  We need a BIRD if people think MS2 is
a good way to go.  Otherwise, MS1 shows that these drivers can already be
simulated with IBIS (assuming your simulation vendor supports full driver
schedules.)

Thanks,

Chris Reid



 
From owner-ibis Mon Apr 16 10:47:42 2001
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From: "Hassan Ali" <hali@nortelnetworks.com>
To: ibis <ibis@eda.org>
Subject: SpecctraQuest/HSPICE IBIS implementation
Date: Mon, 16 Apr 2001 13:46:29 -0400
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I have created an IBIS model of a differential driver from its HSPICE model.
When I use the IBIS model in a SpecctraQuest simulation, the results match
those I obtain from an HSPICE simulation using the HSPICE model. However,
when I use the IBIS model in an HSPICE simulation, I obtain different
results. The output waveform seems to be scaled somehow as shown in the
attached JPEG file. The yellow curve is the correct output; the blue curve
is the incorrect one. Does anybody know what gives rise to that apparent
scaling? (BTW: I obtain same results in HSPICE 99.2 and 2000.4).

Thanks.

Hassan.

 <<sq_hspice_waveforms.jpg>> 



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------_=_NextPart_000_01C0C69D.2AF81380--
 
From owner-ibis Mon Apr 16 12:23:19 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Gregory R Edlund'" <gedlund@us.ibm.com>, ibis@vhdl.org
Subject: RE: BIRD 70.1
Date: Mon, 16 Apr 2001 12:22:31 -0700
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Hi Greg:

  A question and comment.

1. The [Test Data] keyword includes a Driver_model subparameter to specify a
driver model.  Should there also be a Receiver_model subparameter to specify
the receiver?

2. The [Rising Golden Waveform]/[Falling Golden Waveform] keywords are
"Required: Yes (within the scope of [Test Data]".  I think I understand what
you are trying to say -- if [Test Data] is present then the golden waveforms
must also be present -- but both [Test Data] and the golden waveform
keywords belong in the global scope.  I'd make the requirement read
"Required: Yes, if [Test Data] is present."

  Regards,
  Stephen


-----Original Message-----
From: Gregory R Edlund [mailto:gedlund@us.ibm.com]
Sent: Monday, April 16, 2001 8:48 AM
To: ibis@vhdl.org
Subject: BIRD 70.1


Here is BIRD 70.1 for discussion at Friday's Open Forum conference call.
After discussion with Bob Ross and Al Davis, I made some significant
changes that should make it upwardly compatible.  Please note that this
BIRD sets up the infrastructure for a future BIRD to facilitate non-RC
standard loads.  In fact, that BIRD becomes almost trivial.

I have two questions for readers:

1) Semiconductor vendors:  If your customers require you to supply Golden
Waveforms and IF a production-quality SPICE-to-IBIS modeling tool were
available to support them, would this BIRD enable you to do so?

2) EDA vendors:  If your customers asked you to support automated analysis
of Golden Waveforms and produce a correlation figure of merit table, would
this BIRD enable you to do so?

Thanks for your consideration everyone!

Greg

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


****************************************************************************
***
****************************************************************************
***

BIRD ID#:      70.1
ISSUE TITLE:   Golden Waveforms
REQUESTOR:     Greg Edlund, IBM

DATE SUBMITTED:                       April 16, 2001
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

****************************************************************************
***
****************************************************************************
***

STATEMENT OF THE ISSUE:

Golden Waveforms are a set of SPICE waveforms simulated using known ideal
test loads.  They are useful in verifying the accuracy of behavioral
simulation results for any given simulator.  They are not the same thing as
the traditional VT tables recommended in the "IBIS Cookbook."  The "I/O
Buffer
Accuracy Handbook" recommends a set of ideal test loads for classical
push-pull and open-drain drivers.

There is currently a problem with including Golden Waveforms in an IBIS
datasheet: the simulator tries to use these waveforms to construct its
stimulus waveform, and erroneous simulations result.

This BIRD proposes a new syntactical construct to tell the simulator
that a waveform is a Golden Waveform.  The simulator may then choose to
ignore the data or (better yet) run a set of simulations using the network
and circuit parameters provided and report the correlation between the
simulation results and the Golden Waveforms.  The mechanism for describing
a Golden Waveform involves two new keywords whose scope is global:
[Test Load] and [Test Data].  Under the [Test Data] keyword are two new
keywords whose scope is local:  [Rising Golden Waveform] and
[Falling Golden Waveform].

[Test Load] is a description of a test load network that may be referenced
by any Golden Waveform under the [Test Data] keyword.  [Test Data] is a
marker keyword that indicates the beginning of a group of Golden Waveforms.


****************************************************************************
***

STATEMENT OF THE RESOLVED SPECIFICATIONS:

|===========================================================================
==
|    Keywords:  [Test Data]
|    Required:  No
| Description:  Indicates the beginning of a pair of Golden Waveforms
|               and references the conditions under which they were
derived.
|               An IBIS file may contain any number of [Test Data] sections
|               representing different driver and load combinations.
|
|  Sub-Params:  Test_data_type, Driver_model, Test_load, Test_point,
|               T_period, T_meas, V_meas
|
| Usage Rules:  The name following the [Test Data] keyword is required.
|               It allows a tool to select which data to analyze.
|
|               The Test_data_type subparameter is required, and its value
|               must be either "single_ended" or "differential."
|
|               The Driver_model subparameter is required.  Its value
|               specifies the "device-under-test" and must be a valid
[Model]
|               name.
|
|               The Test_load subparameter is required and indicates which
|               [Test Load] was used to derive the Golden Waveforms. It
must
|               reference a valid [Test Load] name.
|
|               The Test_point subparameter is optional.  It indicates
which
|               node in the test load network the Golden Waveforms
represent.
|               The legal values for Test_point are "near" and "far."  If
|               Test_point is not specified, it defaults to "far."
|
|               The T_period subparameter is optional.  In the case that
the
|               Golden Waveforms represent more than one rising or falling
|               edge, the T_period subparameter tells the simulator the
|               period between rising or falling edges.  This subparameter
|               is useful when constructing a test load in which a
reflection
|               from the first edge hits the driver during the second edge.
|
|               The T_meas subparameter is optional.  It captures the time
|               at which the standard load crosses the threshold specified
|               in the component datasheet during a SPICE simulation.  This
|               subparameter is useful when correlating timing intervals
|               between SPICE and behavioral simulations.  It defines the
|               beginning of a timing interval.
|
|               The V_meas subparameter is optional and is also used to
|               perform timing interval correlation.  The end of a timing
|               interval is defined as the time when a Golden Waveform or
|               a behavioral waveform crosses V_meas.
|
|               A timing interval in a behavioral waveform begins when
|               the waveform crosses V_meas defined in the [Model] keyword
|               while driving C_ref and R_ref, i.e. the standard load
defined
|               in the component datasheet.  Note that there are two
|               DIFFERENT V_meas subparameters in IBIS:  one associated
with
|               [Model] and one associated with [Test Data].
|
|---------------------------------------------------------------------------
--
[Test Data] Data1
Test_data_type single_ended
Driver_model Buffer1
Test_load Load1
Test_point far
T_period = 10ns
| variable      typ             min             max
T_meas          1.0ns           0.5ns           1.5ns
V_meas          0.75V           0.75V           0.75V
|
|===========================================================================
==
|    Keywords:  [Rising Golden Waveform], [Falling Golden Waveform]
|    Required:  Yes (within the scope of [Test Data])
| Description:  Describes the shape of the rising and falling Golden
|               Waveforms of a given driver and a given [Test Load].
|               A model developer may use the [Rising Golden Waveform] and
|               [Falling Golden Waveform] keywords to document Golden
|               Waveforms whose purpose is to facilitate the correlation of
|               SPICE and behavioral simulations.
|
|  Sub-Params:  None.
|
| Usage Rules:  The process, temperature, and voltage conditions under
which
|               the Golden Waveforms are generated must be identical to
those
|               used to generate the VI and VT tables. The Golden Waveforms
|               must be generated using unpackaged driver and receiver
models.
|               The simulator must NOT use the Golden Waveform tables in
the
|               construction of its internal stimulus function.
|
|---------------------------------------------------------------------------
--
|
[Rising Golden Waveform]
| Time            V(typ)              V(min)              V(max)
   0.0000s       25.2100mV           15.2200mV           43.5700mV
   0.2000ns       2.3325mV           -8.5090mV           23.4150mV
   0.4000ns       0.1484V            15.9375mV            0.3944V
   0.6000ns       0.7799V             0.2673V             1.3400V
   0.8000ns       1.2960V             0.6042V             1.9490V
   1.0000ns       1.6603V             0.9256V             2.4233V
   1.2000ns       1.9460V             1.2050V             2.8130V
   1.4000ns       2.1285V             1.3725V             3.0095V
   1.6000ns       2.3415V             1.5560V             3.1265V
   1.8000ns       2.5135V             1.7015V             3.1600V
   2.0000ns       2.6460V             1.8085V             3.1695V
| ...
  10.0000ns       2.7780V             2.3600V             3.1670V
|
[Falling Golden Waveform]
| Time            V(typ)              V(min)              V(max)
   0.0000s        5.0000V             4.5000V             5.5000V
   0.2000ns       4.7470V             4.4695V             4.8815V
   0.4000ns       3.9030V             4.0955V             3.5355V
   0.6000ns       2.7313V             3.4533V             1.7770V
   0.8000ns       1.8150V             2.8570V             0.8629V
   1.0000ns       1.1697V             2.3270V             0.5364V
   1.2000ns       0.7539V             1.8470V             0.4524V
   1.4000ns       0.5905V             1.5430V             0.4368V
   1.6000ns       0.4923V             1.2290V             0.4266V
   1.8000ns       0.4639V             0.9906V             0.4207V
   2.0000ns       0.4489V             0.8349V             0.4169V
| ...
  10.0000ns       0.3950V             0.4935V             0.3841V
|
|===========================================================================
==
|    Keywords:  [Test Load]
|    Required:  No
| Description:  Defines a generic test load network and its associated
|               electrical parameters for reference by Golden Waveforms
|               under the [Test Data] keyword.  The Golden Waveform
|               tables access a given [Test Load] by the value of the
|               Test_load subparameter under the [Rising Golden Waveform]
|               and [Falling Golden Waveform] keywords.
|
|  Sub-Params:  Test_data_type, C1_near, Rs_near, Ls_near, C2_near,
Rp1_near,
|               Rp2_near, Td, Zo, Rp1_far, Rp2_far, C2_far, Ls_far, Rs_far,
|               C1_far, V_term1, V_term2, Receiver_model, R_diff_near,
|               R_diff_far.
|
| Usage Rules:  The value of the Test_data_type subparameter must be either
|               "single_ended" or "differential."
|
|               The subparameters specify the electrical parameters
|               associated with a fixed generic test load.  The diagram
|               below describes the single_ended test load.
|
|               All subparameters except Test_data_type are optional.
|               If omitted, series elements are shorted and shunt elements
|               are opened by default.
|
|
|                                    V_term1
|                                 o-----------o
|                                 |           |
|                                 \           \
receiver_model_name
|   ______                        /           /
______
|  |      |  NEAR        Rp1_near \           \ Rp1_far          FAR  |
|
|  | |\   |                       /           /                       | |\
|
|  | | \  |   Rs_near  Ls_near    |   _____   |     Ls_far  Rs_far    | | \
|
|  | |  >-|---o--/\/\--@@@@--o----o--O_____)--o----o--@@@@--/\/\--o---|-|
> |
|  | | /  |   |              |    |   Td      |    |              |   | | /
|
|  | |/   |   | C1_near      |    \   Zo      \    | C2_far       |   | |/
|
|  |______|  ===            ===   /           /   ===            ===
|______|
|             |      C2_near |    \           \    |       C1_far |
|             |              |    /           /    |              |
|             |              |    |  V_term2  |    |              |
|             o--------------o    o-----------o    o--------------o
|             |                Rp2_near    Rp2_far                |
|            GND                                                 GND
|
|
|               If the Td subparameter is present, then the Zo subparameter
|               must also be present.  If the Td subparameter is not
present,
|               then the simulator must remove the transmission line from
|               the network and short the two nodes to which it was
|               connected.
|
|               V_term1 defines the termination voltage for parallel
|               termination resistors Rp1_near and Rp1_far.  This voltage
|               is not related to the [voltage range] keyword.
|               V_term2 defines the termination voltage for parallel
|               termination resistors Rp2_near and Rp2_far.
|
|               Receiver_model is optional and indicates which, if any,
|               receiver is connected to the far end node. If not used, the
|               network defaults to no receiver.
|
|               If Test_load_type is differential, a the test load is a
|               pair of the above circuits.  If the R_diff_near
subparameter
|               is used, it is connected between the near nodes of the two
|               circuits.  If the R_diff_far subparameter is used, it is
|               connected between the near nodes of the two circuits.
|
|---------------------------------------------------------------------------
--
|
[Test Load] Load1
Test_load_type single_ended
C1_near     = 1p
Rs_near     = 10
Ls_near     = 1n
C2_near     = 1p
Rp1_near    = 100
Rp2_near    = 100
Td          = 1ns
Zo          = 50
Rp1_far     = 100
Rp2_far     = 100
C2_far      = 1p
Ls_far      = 1n
Rs_far      = 10
C1_far      = 1p
R_diff      = 100
Receiver_model Input1
| variable      typ             min             max
Vterm1          1.5             1.4             1.6
Vterm2          0.0             0.0             0.0
|
| Example Transmission Line and Receiver test load from "I/O Buffer
Accuracy
| Handbook," section 3.4.4.
|
[Test Load] Tline_rcv
Td          = 1n
Zo          = 50
Receiver_model Input1
|---------------------------------------------------------------------------
--

****************************************************************************
***

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Please refer to BIRD 69.1 for history.  BIRD 70 came about a result of an
attempt to make BIRD 69.1 upwardly compatible with IBIS-X.  BIRD 70 is
actually more compact and efficient because it allows multiple models to
access the same [Test Load].  Recommendations came from Bob Ross, Al Davis,
and the IBIS Open Forum, 3/2/01.

Changes between BIRD 69.1 and BIRD 70:

1. Scope of the "generic test load" is now global rather than being
   local to a particular model.  This is a big improvement.

2. Added one subparameter, Golden_test_load, to [Rising Waveform],
   [Falling Waveform] keywords.  Added text to describe new the
subparameter.
   The Golden_test_load subparameter calls a [Test Load].

3. Exported all the other code to the new [Test Load] keyword.

4. Removed T_ref subparameter. To do timing correlation, the simulator can
   pick a point on the 50 Ohm VT waveform as its "SPICE reference point"
and
   then simulate both the 50 Ohm load and the Golden_test_load to calculate
   a time difference.

5. Removed Pkg_pin parameter. It is too complicated. The user can model a
   simple single-pin lumped circuit using the parameters supplied.

6. Added Tline_present subparameter. If not used, the Tline should be
   removed from the simulation rather than assigned a very small delay
value.
   This prevents the simulator from taking ridiculously small time steps.

7. Replaced V_termxxx with tables similar to the dV/dt_x subparameters.
   This makes the BIRD more economical.

8. Got rid of the paragraph that read, "Using the Golden Waveform
tables..."
   This seemed to be redundant.

9. Specified which parameters are optional and which are required.


Changes between BIRD 70 and BIRD 70.1:

 1. Moved the Golden Waveforms OUT of the [Model] scope and under the
    scope of a new keyword, [Test Data].

 2. Changed [Rising Waveform] to [Rising Golden Waveform].
    Changed [Falling Waveform] to [Falling Golden Waveform].

 3. Added subparameter Driver_model under [Rising Golden Waveform] and
    [Falling Golden Waveform].  This is necessary because the waveforms
    are now outside the scope of the [Model].

 4. Changed the subparameter Golden_test_load to Test_load.

 5. Added the V_meas subparameter to indicate where timing correlation
    measurements should begin and end.

 6. Added subparameters Test_data_type and Test_load_type to facilitate
    upward compatibility with future versions of IBIS.

 7. Removed Tline_present subparameter in favor of language explaining
    that the simulator should remove the Tline if Td is not present.

 8. Moved Driver_model, Test_load, V_meas under the scope of [Test Data].

 9. Added T_meas subparameter to facilitate timing correlation.

10. R_diff became R_diff_near and R_diff_far.

11. Added T_period subparameter to allow multi-cycle correlation in the
    case where a reflection hits the driver while it is switching.

BIRD 70.1 adds 205 lines of code to IBIS, of which 162 are comments.

****************************************************************************
***

ANY OTHER BACKGROUND INFORMATION:


See BIRD 69.1.

****************************************************************************
***



 
From owner-ibis Tue Apr 17 07:45:30 2001
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From: Ramesh.Reddy@smartm.com
To: ibis@vhdl.org
Message-ID: <88256A31.00540FF6.00@smtphost.smartm.com>
Date: Tue, 17 Apr 2001 20:02:24 +0500
Subject: question on Tflight
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Hi all
i have a question on Tflight
when i am measuring Tflight  b/n  processor and 440bx both for fast and slow
corner,
i  am getting Tflight_min (fastcorner) value more than Tflight_max (slowcorner).
I am  measuring Tflight as per guide lines.
can i get like that ?
or  i am going wrong.

regards
ramesh


 
From owner-ibis Tue Apr 17 08:20:34 2001
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From: "Kern, Frank" <frank.kern@intel.com>
To: "'Ramesh.Reddy@smartm.com'" <Ramesh.Reddy@smartm.com>
Cc: ibis@vhdl.org
Subject: RE: question on Tflight
Date: Tue, 17 Apr 2001 08:19:53 -0700
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Hi Ramesh,

I have seen this for some designs.  Upon investigation, we found a simple
explanation. The minimum threshold voltage for the slow corner is lower than
the value for the fast corner.  Also the starting low voltage level, Vol,
for the slow corner is higher than the fast corner value.  As a consequence,
the slow case has to transition through a lesser amount of voltage compared
to the fast case, which can result in a slow corner flight time appearing
faster than the fast case.

Kern
Intel Corporation

-----Original Message-----
From: Ramesh.Reddy@smartm.com [mailto:Ramesh.Reddy@smartm.com]
Sent: Tuesday, April 17, 2001 8:02 AM
To: ibis@vhdl.org
Subject: question on Tflight




Hi all
i have a question on Tflight
when i am measuring Tflight  b/n  processor and 440bx both for fast and slow
corner,
i  am getting Tflight_min (fastcorner) value more than Tflight_max
(slowcorner).
I am  measuring Tflight as per guide lines.
can i get like that ?
or  i am going wrong.

regards
ramesh



 
From owner-ibis Tue Apr 17 08:41:56 2001
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'Ramesh.Reddy@smartm.com'" <Ramesh.Reddy@smartm.com>
Cc: ibis@vhdl.org
Subject: RE: question on Tflight
Date: Tue, 17 Apr 2001 11:40:43 -0400
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> i have a question on Tflight
> when i am measuring Tflight  b/n  processor and 440bx both for fast and
> slow
> corner,
> i  am getting Tflight_min (fastcorner) value more than Tflight_max
> (slowcorner).
> I am  measuring Tflight as per guide lines.
> can i get like that ?
 
I am not sure if this is relevant to your question; I don't know whose
"guidelines" you are using; etc.

But if you define Tflight as the difference between the signal at the far
end of your actual trace, and the transmitted signal with a standard test
load, this can happen, especially if the test load is capacitive.  (Doing it
this way makes it easier to add the driver's datasheet delay to Tflight, and
the result is the total delay to the receiver's input.)

In the slow corner case, the driving device's delay into the standard test
load is more, so it is a larger number that you subtract from the total
delay to get Tflight.  If the test load is highly capacitive, it can
exaggerate this effect, causing the delay with the test load to become
larger at a faster rate than that with your real load.  You can even get
negative "wire" delays this way, especially in the slow corner case.

Regards,
Andy

 
From owner-ibis Tue Apr 17 10:22:17 2001
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From: "Todd Westerhoff" <twester@hhnetwk.com>
To: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>, <Ramesh.Reddy@smartm.com>
Cc: <ibis@vhdl.org>
Subject: RE: question on Tflight
Date: Tue, 17 Apr 2001 13:22:02 -0400
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Andy is absolutely right ... and capacitive test loads make the problems
worse.

Moral of the story:

When using a fast driver, look only at the min flight times (ignore the max
ones)
When using a slow driver, look only at the max flight times (ignore the min
ones)

If you want to perform an intersting "sanity check" of your SI models, find
the output delay into the test load for the fast and slow driver cases
(variously called "Buffer Delay", "TIME_TO_VM" and others), and then
subtract those numbers from the datasheet values for Tcomin and Tcomax,
respectively.

The number you get represents what I think of as the "internal delay" of the
part - the time between when the clock input triggers and time "0" of the SI
simulation.  This isn't a real delay, because of the different ways the
output can be modeled, but it's an interesting "figure of merit" exercise.
In some of the devices we've worked with recently, this exercise led to the
conclusion that the output stage could be triggered up to 1ns _before_ the
device received its input clock.  This wasn't the actual case - but it
provided us with some valuable insight about just how much the part's timing
numbers were being guard-banded.

Todd.

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Tuesday, April 17, 2001 11:41 AM
To: 'Ramesh.Reddy@smartm.com'
Cc: ibis@vhdl.org
Subject: RE: question on Tflight


> i have a question on Tflight
> when i am measuring Tflight  b/n  processor and 440bx both for fast and
> slow
> corner,
> i  am getting Tflight_min (fastcorner) value more than Tflight_max
> (slowcorner).
> I am  measuring Tflight as per guide lines.
> can i get like that ?

I am not sure if this is relevant to your question; I don't know whose
"guidelines" you are using; etc.

But if you define Tflight as the difference between the signal at the far
end of your actual trace, and the transmitted signal with a standard test
load, this can happen, especially if the test load is capacitive.  (Doing it
this way makes it easier to add the driver's datasheet delay to Tflight, and
the result is the total delay to the receiver's input.)

In the slow corner case, the driving device's delay into the standard test
load is more, so it is a larger number that you subtract from the total
delay to get Tflight.  If the test load is highly capacitive, it can
exaggerate this effect, causing the delay with the test load to become
larger at a faster rate than that with your real load.  You can even get
negative "wire" delays this way, especially in the slow corner case.

Regards,
Andy

 
From owner-ibis Tue Apr 17 12:33:56 2001
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From: "Todd Westerhoff" <twester@hhnetwk.com>
To: "Todd Westerhoff" <twester@hhnetwk.com>,
   "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>, <Ramesh.Reddy@smartm.com>
Cc: <ibis@vhdl.org>
Subject: RE: question on Tflight
Date: Tue, 17 Apr 2001 15:33:35 -0400
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A clarification to my earlier post --

Please note that the statements:

When using a fast driver, look only at the min flight times (ignore the max
ones)
When using a slow driver, look only at the max flight times (ignore the min
ones)

are meant only for the case where the output delay in spec'd into a large
(~50pF) capacitive load.

Sorry for any confusion ...

Todd.
-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Tuesday, April 17, 2001 1:22 PM
To: Ingraham, Andrew; Ramesh.Reddy@smartm.com
Cc: ibis@vhdl.org
Subject: RE: question on Tflight


Andy is absolutely right ... and capacitive test loads make the problems
worse.

Moral of the story:

When using a fast driver, look only at the min flight times (ignore the max
ones)
When using a slow driver, look only at the max flight times (ignore the min
ones)

If you want to perform an intersting "sanity check" of your SI models, find
the output delay into the test load for the fast and slow driver cases
(variously called "Buffer Delay", "TIME_TO_VM" and others), and then
subtract those numbers from the datasheet values for Tcomin and Tcomax,
respectively.

The number you get represents what I think of as the "internal delay" of the
part - the time between when the clock input triggers and time "0" of the SI
simulation.  This isn't a real delay, because of the different ways the
output can be modeled, but it's an interesting "figure of merit" exercise.
In some of the devices we've worked with recently, this exercise led to the
conclusion that the output stage could be triggered up to 1ns _before_ the
device received its input clock.  This wasn't the actual case - but it
provided us with some valuable insight about just how much the part's timing
numbers were being guard-banded.

Todd.

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Tuesday, April 17, 2001 11:41 AM
To: 'Ramesh.Reddy@smartm.com'
Cc: ibis@vhdl.org
Subject: RE: question on Tflight


> i have a question on Tflight
> when i am measuring Tflight  b/n  processor and 440bx both for fast and
> slow
> corner,
> i  am getting Tflight_min (fastcorner) value more than Tflight_max
> (slowcorner).
> I am  measuring Tflight as per guide lines.
> can i get like that ?

I am not sure if this is relevant to your question; I don't know whose
"guidelines" you are using; etc.

But if you define Tflight as the difference between the signal at the far
end of your actual trace, and the transmitted signal with a standard test
load, this can happen, especially if the test load is capacitive.  (Doing it
this way makes it easier to add the driver's datasheet delay to Tflight, and
the result is the total delay to the receiver's input.)

In the slow corner case, the driving device's delay into the standard test
load is more, so it is a larger number that you subtract from the total
delay to get Tflight.  If the test load is highly capacitive, it can
exaggerate this effect, causing the delay with the test load to become
larger at a faster rate than that with your real load.  You can even get
negative "wire" delays this way, especially in the slow corner case.

Regards,
Andy

 
From owner-ibis Wed Apr 18 11:38:10 2001
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Subject: BIRD 70.1 - take 2
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As a result of yesterday's IBIS Futures conference call, I have made a few
changes to BIRD 70.1.  I removed the "Test_point" subparameter and replaced
it by a near/far qualifier to the [Rising/Falling Waveform] keywords.

As I understood the conversation yesterday, the two remaining points of
discussion are:

1) Do we need additional Test_load_types to cover all differential test
loads allowable by IBIS today?  Bob Ross says yes.

2) Is the Tmeas subparameter necessary?

I have added some ASCII art to the BIRD in hopes of clarifying item 2.

Hopefully this BIRD is close to completion!

Greg


*******************************************************************************
*******************************************************************************

BIRD ID#:      70.1
ISSUE TITLE:   Golden Waveforms
REQUESTOR:     Greg Edlund, IBM

DATE SUBMITTED:                       March 16, 2001; April 18, 2001
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

*******************************************************************************
*******************************************************************************

STATEMENT OF THE ISSUE:

Golden Waveforms are a set of SPICE waveforms simulated using known ideal
test loads.  They are useful in verifying the accuracy of behavioral
simulation results for any given simulator.  They are not the same thing as
the traditional VT tables recommended in the "IBIS Cookbook."  The "I/O
Buffer
Accuracy Handbook" recommends a set of ideal test loads for classical
push-pull and open-drain drivers.

There is currently a problem with including Golden Waveforms in an IBIS
datasheet: the simulator tries to use these waveforms to construct its
stimulus waveform, and erroneous simulations result.

This BIRD proposes a new syntactical construct to tell the simulator
that a waveform is a Golden Waveform.  The simulator may then choose to
ignore the data or (better yet) run a set of simulations using the network
and circuit parameters provided and report the correlation between the
simulation results and the Golden Waveforms.  The mechanism for describing
a Golden Waveform involves two new keywords whose scope is global:
[Test Load] and [Test Data].  Under the [Test Data] keyword are four new
keywords whose scope is local:  [Rising Waveform Near],
[Falling Waveform Near], [Rising Waveform Far], [Falling Waveform Far].

[Test Load] is a description of a test load network that may be referenced
by any Golden Waveform under the [Test Data] keyword.  [Test Data] is a
marker keyword that indicates the beginning of a group of Golden Waveforms.


*******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

|=============================================================================
|    Keywords:  [Test Data]
|    Required:  No
| Description:  Indicates the beginning of a set of Golden Waveforms
|               and references the conditions under which they were
derived.
|               An IBIS file may contain any number of [Test Data] sections
|               representing different driver and load combinations.
|
|  Sub-Params:  Test_data_type, Driver_model, Test_load,
|               Tmeas_rise, Tmeas_fall, Vx_rise, Vx_fall
|
| Usage Rules:  The name following the [Test Data] keyword is required.
|               It allows a tool to select which data to analyze.
|
|               The Test_data_type subparameter is required, and its value
|               must be either "Single_ended" or "Differential."
|
|               The Driver_model subparameter is required.  Its value
|               specifies the "device-under-test" and must be a valid
[Model]
|               name.
|
|               The Test_load subparameter is required and indicates which
|               [Test Load] was used to derive the Golden Waveforms. It
must
|               reference a valid [Test Load] name.
|
|               The Tmeas_rise, Tmeas_fall, Vx_rise, and Vx_fall
subparameters
|               are all optional.  They work in concert with the standard
load
|               parameters under the [Model] keyword (Cref, Rref, Vref,
Vmeas)
|               to define two timing intervals for timing correlation.
|               Tmeas_rise is the time at which the SPICE standard load
|               rises through Vmeas with the SAME driver input that was
|               used to derive the Golden Waveform tables.
|
|               SPICE simulation of standard load (not captured in IBIS
file)
|                      ________________
|                     /                \
|                    /--- Vmeas         \
|               ____/                    \______________
|                    + Tmeas_rise
|
|               SPICE simulation of Test_load (captured in [Test Data])
|                                ________________
|                               /                \
|                              /--- Vx_rise       \
|               ______________/                    \______________
|                              +
|                    |<------->| Timing Interval 1
|
|
|               Behavioral simulation of standard load
|                      ________________
|                     /                \
|                    /--- Vmeas         \
|               ____/                    \______________
|                    +
|
|               Behavioral simulation of Test_load
|                                ________________
|                               /                \
|                              /--- Vx_rise       \
|               ______________/                    \______________
|                              +
|                    |<------->| Timing Interval 2
|
|-----------------------------------------------------------------------------
[Test Data] Data1
Test_data_type Single_ended
Driver_model Buffer1
Test_load Load1
| variable      typ             min             max
Tmeas_rise      1.0ns           0.5ns           1.5ns
Tmeas_fall      1.0ns           0.5ns           1.5ns
Vx_rise         0.75V           0.75V           0.75V
Vx_fall         0.75V           0.75V           0.75V
|
|=============================================================================
|    Keywords:  [Rising Waveform Near], [Falling Waveform Near],
|               [Rising Waveform Far], [Falling Waveform Far]
|    Required:  At least one Rising/Falling waveform pair is required under
|               the scope of the [Test Data] keyword.  Two pairs are
allowed.
| Description:  Describes the shape of the rising and falling Golden
|               Waveforms of a given driver and a given [Test Load].
|               A model developer may use the [Rising Waveform Near/Far]
and
|               [Falling Waveform Near/Far] keywords to document Golden
|               Waveforms whose purpose is to facilitate the correlation of
|               SPICE and behavioral simulations.
|
|  Sub-Params:  None.
|
| Usage Rules:  The process, temperature, and voltage conditions under
which
|               the Golden Waveforms are generated must be identical to
those
|               used to generate the VI and VT tables. The Golden Waveforms
|               must be generated using unpackaged driver and receiver
models.
|               The simulator must NOT use the Golden Waveform tables in
the
|               construction of its internal stimulus function.
|
|-----------------------------------------------------------------------------
|
[Rising Waveform Far]
| Time            V(typ)              V(min)              V(max)
   0.0000s       25.2100mV           15.2200mV           43.5700mV
   0.2000ns       2.3325mV           -8.5090mV           23.4150mV
   0.4000ns       0.1484V            15.9375mV            0.3944V
   0.6000ns       0.7799V             0.2673V             1.3400V
   0.8000ns       1.2960V             0.6042V             1.9490V
   1.0000ns       1.6603V             0.9256V             2.4233V
   1.2000ns       1.9460V             1.2050V             2.8130V
   1.4000ns       2.1285V             1.3725V             3.0095V
   1.6000ns       2.3415V             1.5560V             3.1265V
   1.8000ns       2.5135V             1.7015V             3.1600V
   2.0000ns       2.6460V             1.8085V             3.1695V
| ...
  10.0000ns       2.7780V             2.3600V             3.1670V
|
[Falling Waveform Far]
| Time            V(typ)              V(min)              V(max)
   0.0000s        5.0000V             4.5000V             5.5000V
   0.2000ns       4.7470V             4.4695V             4.8815V
   0.4000ns       3.9030V             4.0955V             3.5355V
   0.6000ns       2.7313V             3.4533V             1.7770V
   0.8000ns       1.8150V             2.8570V             0.8629V
   1.0000ns       1.1697V             2.3270V             0.5364V
   1.2000ns       0.7539V             1.8470V             0.4524V
   1.4000ns       0.5905V             1.5430V             0.4368V
   1.6000ns       0.4923V             1.2290V             0.4266V
   1.8000ns       0.4639V             0.9906V             0.4207V
   2.0000ns       0.4489V             0.8349V             0.4169V
| ...
  10.0000ns       0.3950V             0.4935V             0.3841V
|
|=============================================================================
|    Keywords:  [Test Load]
|    Required:  No
| Description:  Defines a generic test load network and its associated
|               electrical parameters for reference by Golden Waveforms
|               under the [Test Data] keyword.  The Golden Waveform
|               tables correspond to a given [Test Load] which is specified
|               by the Test_load subparameter under the [Test Data]
keyword.
|
|  Sub-Params:  Test_data_type, C1_near, Rs_near, Ls_near, C2_near,
Rp1_near,
|               Rp2_near, Td, Zo, Rp1_far, Rp2_far, C2_far, Ls_far, Rs_far,
|               C1_far, V_term1, V_term2, Receiver_model, R_diff_near,
|               R_diff_far.
|
| Usage Rules:  The value of the Test_data_type subparameter must be either
|               "Single_ended" or "Differential."
|
|               The subparameters specify the electrical parameters
|               associated with a fixed generic test load.  The diagram
|               below describes the single_ended test load.
|
|               All subparameters except Test_data_type are optional.
|               If omitted, series elements are shorted and shunt elements
|               are opened by default.
|
|
|                                    V_term1
|                                 o-----------o
|                                 |           |
|                                 \           \
receiver_model_name
|   ______                        /           /
______
|  |      |  NEAR        Rp1_near \           \ Rp1_far          FAR  |
|
|  | |\   |                       /           /                       | |\
|
|  | | \  |   Rs_near  Ls_near    |   _____   |     Ls_far  Rs_far    | | \
|
|  | |  >-|---o--/\/\--@@@@--o----o--O_____)--o----o--@@@@--/\/\--o---|-|
> |
|  | | /  |   |              |    |   Td      |    |              |   | | /
|
|  | |/   |   | C1_near      |    \   Zo      \    | C2_far       |   | |/
|
|  |______|  ===            ===   /           /   ===            ===
|______|
|             |      C2_near |    \           \    |       C1_far |
|             |              |    /           /    |              |
|             |              |    |  V_term2  |    |              |
|             o--------------o    o-----------o    o--------------o
|             |                Rp2_near    Rp2_far                |
|            GND                                                 GND
|
|
|               If the Td subparameter is present, then the Zo subparameter
|               must also be present.  If the Td subparameter is not
present,
|               then the simulator must remove the transmission line from
|               the network and short the two nodes to which it was
|               connected.
|
|               V_term1 defines the termination voltage for parallel
|               termination resistors Rp1_near and Rp1_far.  This voltage
|               is not related to the [voltage range] keyword.
|               V_term2 defines the termination voltage for parallel
|               termination resistors Rp2_near and Rp2_far.
|
|               Receiver_model is optional and indicates which, if any,
|               receiver is connected to the far end node. If not used, the
|               network defaults to no receiver.
|
|               If Test_load_type is differential, a the test load is a
|               pair of the above circuits.  If the R_diff_near
subparameter
|               is used, it is connected between the near nodes of the two
|               circuits.  If the R_diff_far subparameter is used, it is
|               connected between the near nodes of the two circuits.
|
|-----------------------------------------------------------------------------
|
[Test Load] Load1
Test_load_type Single_ended
C1_near     = 1p
Rs_near     = 10
Ls_near     = 1n
C2_near     = 1p
Rp1_near    = 100
Rp2_near    = 100
Td          = 1ns
Zo          = 50
Rp1_far     = 100
Rp2_far     = 100
C2_far      = 1p
Ls_far      = 1n
Rs_far      = 10
C1_far      = 1p
R_diff      = 100
Receiver_model Input1
| variable      typ             min             max
Vterm1          1.5             1.4             1.6
Vterm2          0.0             0.0             0.0
|
| Example Transmission Line and Receiver test load from "I/O Buffer
Accuracy
| Handbook," section 3.4.4.
|
[Test Load] Tline_rcv
Td          = 1n
Zo          = 50
Receiver_model Input1
|-----------------------------------------------------------------------------

*******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Please refer to BIRD 69.1 for history.  BIRD 70 came about a result of an
attempt to make BIRD 69.1 upwardly compatible with IBIS-X.  BIRD 70 is
actually more compact and efficient because it allows multiple models to
access the same [Test Load].  Recommendations came from Bob Ross, Al Davis,
and the IBIS Open Forum, 3/2/01.

Changes between BIRD 69.1 and BIRD 70:

1. Scope of the "generic test load" is now global rather than being
   local to a particular model.  This is a big improvement.

2. Added one subparameter, Golden_test_load, to [Rising Waveform],
   [Falling Waveform] keywords.  Added text to describe new the
subparameter.
   The Golden_test_load subparameter calls a [Test Load].

3. Exported all the other code to the new [Test Load] keyword.

4. Removed T_ref subparameter. To do timing correlation, the simulator can
   pick a point on the 50 Ohm VT waveform as its "SPICE reference point"
and
   then simulate both the 50 Ohm load and the Golden_test_load to calculate
   a time difference.

5. Removed Pkg_pin parameter. It is too complicated. The user can model a
   simple single-pin lumped circuit using the parameters supplied.

6. Added Tline_present subparameter. If not used, the Tline should be
   removed from the simulation rather than assigned a very small delay
value.
   This prevents the simulator from taking ridiculously small time steps.

7. Replaced V_termxxx with tables similar to the dV/dt_x subparameters.
   This makes the BIRD more economical.

8. Got rid of the paragraph that read, "Using the Golden Waveform
tables..."
   This seemed to be redundant.

9. Specified which parameters are optional and which are required.


Changes between BIRD 70 and BIRD 70.1:

 1. Moved the Golden Waveforms OUT of the [Model] scope and under the
    scope of a new keyword, [Test Data].

 2. Changed [Rising Waveform] to [Rising Waveform Near/Far].
    Changed [Falling Waveform] to [Falling Waveform Near/Far].

 3. Added subparameter Driver_model under [Rising Golden Waveform] and
    [Falling Golden Waveform].  This is necessary because the waveforms
    are now outside the scope of the [Model].

 4. Changed the subparameter Golden_test_load to Test_load.

 5. Added the Vx_rise/fall subparameters to indicate the end of a timing
    interval for timing correlation.

 6. Added Tmeas_rise/fall to facilitate timing correlation.

 7. Added subparameters Test_data_type and Test_load_type to facilitate
    upward compatibility with future versions of IBIS.

 8. Removed Tline_present subparameter in favor of language explaining
    that the simulator should remove the Tline if Td is not present.

 9. Moved Driver_model and Test_load under the scope of [Test Data].

10. R_diff became R_diff_near and R_diff_far.

BIRD 70.1 adds 230 lines of code to IBIS, of which 172 are comments.

*******************************************************************************

ANY OTHER BACKGROUND INFORMATION:


See BIRD 69.1.

*******************************************************************************


Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

 
From owner-ibis Wed Apr 18 10:17:56 2001
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To All:

Cecilia Fleming of EIA reports that IBIS Version 3.2 has
been approved for release as an international standard
under IEC.  The vote link is below.

It should be published by IEC in about a month.

Bob Ross
Mentor Graphics
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Bob:

It looks like it was approved go to:

http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=3DE&wwwprog=3Dv=
ote2.p&wcom=3D93&wclass=3D&wdoc=3D129&wsup=3D

Cece

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From owner-ibis Wed Apr 18 14:57:53 2001
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From: Bob Ross <bob_ross@mentorg.com>
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To All:

We will be discussing a work in progress Connector
Specification at the meeting.  At the next meeting
we will cover sections 1-6 (Header Section), pages 1-10.
The purpose is to present/educate the IBIS Open Forum
about proposed details and to get the next level of
input before presenting the document for a committee
vote.

The latest version is under the Connector Info
link of:

  http://www.eda.org/pub/ibis/connector/

I expect this to be updated regularly as we make
changes and gain further understanding.  Some of the
changes will be editorial to be in alignment with
the work done by the IBIS Futures Working Group.

The current version for review is 0.961B, under
ICM_961B.PDF.

Bob Ross
Mentor Graphics
 
From owner-ibis Thu Apr 19 11:13:37 2001
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To All:

Version 0.962 of the Connector Specification is now
uploaded for review under:

  http://www.eda.org/pub/ibis/connector/ICM0962.PDF

Bob Ross
Mentor Graphics


apanella@molex.com wrote:
> 
> <<File: icm0962.pdf>>Bob...
> 
> 0.962 attached
> 
> _gus
> 
> -----Original Message-----
> From: Bob Ross <bob_ross@mentorg.com>
> Sent: Wednesday, April 18, 2001 4:57 PM
> To: ibis@eda.org
> Subject: IBIS Meeting Friday 4/20/01 Connector Spec. Review
> 
> To All:
> 
> We will be discussing a work in progress Connector
> Specification at the meeting.  At the next meeting
> we will cover sections 1-6 (Header Section), pages 1-10.
> The purpose is to present/educate the IBIS Open Forum
> about proposed details and to get the next level of
> input before presenting the document for a committee
> vote.
> 
> The latest version is under the Connector Info
> link of:
> 
>   http://www.eda.org/pub/ibis/connector/
> 
> I expect this to be updated regularly as we make
> changes and gain further understanding.  Some of the
> changes will be editorial to be in alignment with
> the work done by the IBIS Futures Working Group.
> 
> The current version for review is 0.961B, under
> ICM_961B.PDF.
> 
> Bob Ross
> Mentor Graphics
> 
>   --------------------------------------------------------------------------------
>                          Name: ICM0962.PDF
>    ICM0962.PDF           Type: Portable Document Format (application/pdf)
>                      Encoding: base64
>               Download Status: Not downloaded with message
 
From owner-ibis Thu Apr 19 16:33:25 2001
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To All:

Greg Edlund recently issued IBIS BIRD70.2 for Golden Waveforms.

It was issued as a revised BIRD70.1, but it is uploaded
as BIRD70.2 under:

  http://www/eda/org/pub/ibis/birds/

My general comment (that has been shared privately already
with Greg) is that BIRD70.2 should be extended to cover
differential Golden Waveforms in a more robust and useful
manner.  The overall criteria should be: Does it support
all of the commonly used technologies today (SSTL-*, LVDS,
etc.)?  Also, BIRD70.2 should support some cases where the
inverting driver or the inverting receiver can be different
than the non-inverting driver or receiver.

BIRD70.2 already proposes a fairly useful and general
test configuration for Single-ended loads and tests.  I 
believe only a few additions are need to make it useful
for general Differential tests.

Under [Test Load], I would make these changes:

  Add   Receiver_model_Inverting   | Optional

Under [Test Load]

  Add   Driver_model_Inverting     | Optional
 
Add a section for

  [Differntial Waveform Near]
  [Differntial Waveform Far]

There may be some other parameters needed related to
some of the threshold and timing details, but I need to
study this further.

Bob Ross
Mentor Graphics
 
From owner-ibis Mon Apr 23 17:57:08 2001
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To: ibis@eda.org
Subject: EIA IBIS Open Forum Meeting Minutes


DATE: 4/23/01

SUBJECT: 4/20/01 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal*
Agilent                        (Mark Chang)
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Balistreri
Avanti                         (Chen Hongyu)
Brocade Communications         Robert Badal
Cadence Design                 Ian Dodd, Patrick Dos Santos, Heiko Dudek
Cisco Systems                  Syed Huq, Lungfu Chen
Compaq                         Peter LaFlamme, Ron Bellomio, Quang Dam,
                               Bill Ham
Cypress                        (Rajesh Manapat)
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
IBM                            Michael Cohen, Greg Edlund*, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx)         Guy de Burgh*, John Angulo*, Cary Mandel, 
                               Matthew Flora*
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Dave Lorang,
                               Michael Mirmak*, Qinglun Chen, Will Hobbs
LSI Logic                      Larry Barnes*
Mentor Graphics                Bob Ross*, Tom Dagostino, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet
Micron Technology              Randy Wolff, Yong Phan
Mitsubishi                     (Tam (Tom) Cao)
Molex Incorporated             Gus Panella, Brian O'Malley
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz*
Nortel Networks                Calvin Trowell
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe
Quantic EMC                    (Mike Ventham)
Robinson-Nugent, Inc.          (Alexander Barr)
Siemens (& Automotive) AG      Bernhard Unger, Helmut Katzier, Katja Koller,
                               Wolfram Meyer, Eckhard Lenski, Gerald Bannert,
                               Burkhard Muller, Christian Marot,
                               Manfred Maurer, Amir Motamedi,
                               Hans Pichlmaier
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
BMW                            Friedrich Hasinger
Cereva Networks                Bob Haller
EADS Airbus Industry           Claude Huet
  (Aerospatiale)
EFM                            Ekkehard Miersch, Horle Raines
EIA                            Cecilia Fleming
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Huawei Technologies            Rachild Chen
Hyundai Electronics            Jongho Kang
Infineon Technologies          Christian Sporrer
Intrinsix Corporation          Steven Chin
National Institute of Applied  Etienne Sicard
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Sintecs                        Hans Klos
STMicroelectronics             Peter Hirt, Fabrice Boissieres
Sun                            Adrian Udenze
Xilinx                         Susan Wu
Independent, Consultant        Al Davis*

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  May 11              (916) 356-2663   2                0210511
  June 1              (916) 356-2663   2                6352088
  Thursday June 21, 2001 IBIS Summit Meeting, No Phone Bridge

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum, and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS AND MEETING QUORUM
Long time IBIS participant Matthew Flora from Innoveda joined us for the first
time this year.  His main IBIS involvement is with ibischk3 development and
issues (bugs).


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross gave a final year 2000 financial report based on the latest
adjustments.  A synopsis is below:

                       Budget       Actual

  Income:              22,500.00    23,545.50
  Parser:                   0        6,252.00
  Royalties:            1,000.00     4,335.77
                       ---------    ---------
  Total Income:        23,500.00    34,133.27

  Total Expenses:      15,710.00    13,050.16
  Total Allocations:    6,370.00     6,632.84
                       ---------    ---------
  Total Payments:      22,080.00    19,683.00

                       =========    =========

  Net Income:          $1,420.00   $14,550.27

Some of the income is already targeted for ibischk3 parser development work.
All of the income is carried over to this year and available for projects.
Bob stated that our budget for this year is about the same, except that the
EIA expenses have been increased by $3,000 for administrative support.  Our
membership income may be less this year due to current economic conditions.
Bob also stated the Cecilia Fleming sent invoices again to companies that have
not paid.  We currently have about 25 paid members.  Bob expects about 30
this year, down from 34.  So we expect a break-even year.


REVIEW OF MINUTES AND AR'S
The March 30, 2001 IBIS Minutes were approved without change.

The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Bob Ross reported IBIS references in two articles in the April 2001 issue of
Printed Circuit Design: "Signal Integrity Fundamentals" by Lynne Green,
pp. 16 - 18, and "People to Know, Howard W. Johnson, The Wizard of Black
Magic", by Andy Shaughnessy, pp 34 - 35, 43.

Also IBIS is mentioned in the March 2001 issue of High Density Interconnect
Magazine, "TDR for Characterization and Modeling of Electronic Packaging,
Part 1" by Dima Smolyansky.

Bob reported that Syed updated the Upcoming Events Link.  Also a new IBIS
Futures Working Group link is added and another logo has been added to the
Poster link.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Roy Leventhal announced that the IBIS Models page has been updated.  A few
company names have been changed.  Roy is currently in maintenance mode and may
add some internal hyper-links for easier access within the page.

Bob Ross reported that Galileo Technology now has an IBIS model at:

  http://www.galileot.com/products/internetworking/horizon/96100A.IBS

Bob stated he was glad that Roy is now maintaining the IBIS models page and
keeping it up to date.  Report any new models to Roy.


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 3.2) - Bob Ross reported that the vote closed on 
  April 13, 2001, and IEC 62014-1 was approved 7 Yes, 0 No and 5 Abstaining.
  Bob expects that IBIS Version 3.2 will be published by IEC in about a month
  as an international standard.  The link showing the country voting results
  is (split into two lines):

  http://www.iec.ch/cgi-bin/procgi.pl/www/
    iecwww.p?wwwlang=E&wwwprog=vote2.p&wcom=93&wclass=&wdoc=129&wsup=

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - No report.

- IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) -  Jean Claude Perrin 
  reported that the working draft of the document has been received by IEC.
  Jean Claude will send Bob Ross a copy of the document for uploading on the
  IBIS page on Monday, April 23, 2001.  The official document needs to be
  re-formatted according to IEC guidelines before it is approved.  This should
  take about a month.  Jean Claude will contact Bob concerning how to proceed
  next.

  Bob stated that he has created a subdirectory for EMC data on:

    http://www.eda.org/pub/ibis/emc/

  He has an older presentation under it and plans to put the European IBIS
  Summit presentations related to EMC under this link as well [Done].

- JEDEC JC-16 - Modeling and Testing - No report.

- T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the
  National Committee for Information Technology (NCITS)) - Larry Barnes
  commented that he reviewed IBIS reflector e-mail sent by Chris Reid on 
  "Reduced Strength Drivers and Driver Schedules" with his designers.  They
  generally liked the approach and also Chris' possible improvement.  However,
  they added that the clock signal frequency was "negotiatable".  In the
  future, Larry would like a solution that uses the clock signal.  Currently,
  multiple driver schedules would be needed.  Chris' improvement might help
  here.

  Bob Ross concluded that IBIS Version 3.2 currently solves the problem to a
  satisfactory level, and Larry stated that this takes care of some proposed
  SCSI advances for the next few years.


DESIGN AUTOMATION CONFERENCE 2001 IBIS SUMMIT MEETING PLANS
Bob Ross gave the general plans for the next IBIS Summit Meeting.  The
annual meeting is conducted along with the Design Automation Conference (DAC),
held this year in Las Vegas, Nevada.  The IBIS Summit Meeting will be in the
Hilton Hotel adjacent to the Las Vegas Convention Center.  The meeting date
is Thursday, June 21, 2001, the day following the trade show portion of DAC.
This meeting is sponsored by the IBIS Open Forum through the dues.  Guy de
Burgh will coordinate the signups, presentations and other local logistics.
EIA and Cecilia Fleming will help with the meeting site and luncheon
logistics.

Bob stated that the first announcement should be sent out at the end of April
or beginning of May.   Bob estimated about 10 are attending so far based on
responses at this meeting and on other contacts.  Typically about 25 people
attend.

Larry Barnes asked if there would be a teleconference phone line since travel
is more restricted.  Bob stated that they are quite expensive (hundreds of
dollars) and he would prefer not to have one.  Bob asked Guy to investigate
bringing an LCD projector since Hotel rental prices are usually quite high.
Bob also stated that he prefers overhead foils for better meeting flow and
interaction.

Bob noted that the annual election of IBIS officers occurs at that meeting.
Nominations are open to anyone, but the Chair and Vice-chair must be from EIA
IBIS Open Forum member companies.  Nominations will be accepted at the
meeting.

Bob stated that the existing slate of officers are willing to serve again in
their current positions.  The only difference is that Bob and Stephen Peters
are planning to switch Chair and Vice-Chair roles.  Even so, all positions are
open, and other candidates are welcome.

Bob outlined other meeting topics and possible presentations:

  Connector Specification
  IBIS-X
  IBIS Version 4.0 Issues
  Possibly other topics such as enhanced buffer extraction and driver schedule
    modeling.

The meeting is scheduled for all day, but it will probably end early.  We
typically have fewer presentations for this meeting than at other Summit
meetings.


IBIS MODEL REVIEW COMMITTEE DISCUSSION
John Angulo stated that no new models have been received.  Bob Ross knows of
one that may be submitted.  

John also mentioned that the number of companies reviewing models has dropped
to two.  He needs a representative from another company and will pursue this
off-line.


CONNECTOR PROPOSAL REVIEW
Bob Ross reported on a meeting with Bob, Stephen Peters and Gus Panella held
on April 17, 2001 to discuss alignment issues with the IBIS-X draft and the
Connector Specification.  The IBIS Futures Working Group had used some of the
Connector Specification ideas for the IBIS-X document.  As a result they are
similar, but some differences have emerged.  The group agreed on a number of
details and Gus issued Version 9.62 for review.

Connector Working Group meetings will be scheduled every second Tuesday one
hour before the IBIS Futures Group meeting, with the next one occurring on
May 1, 2001.  Bob indicated that the Connector Working Group meeting
teleconference numbers will be sent to the IBIS Reflector to open up the
participation to anyone who is interested.  Larry Barnes stated that he might
attend since the SCSI Committee also is interested in connector issues.

Bob gave several reasons for the introductory review.  We now want to get the
document into a state where we can vote on it.  We want to educate the IBIS
community on what is in it and on how to read it.  And we want to examine more
closely some decisions we have made since they will also apply to the IBIS-X
documents.  Bob noted that the Connector Specification will still need to be
cleaned up editorially, and this will be going on while we are reviewing the
technical content.  So a number of upgrade releases should be issued.

For reference, Bob compared the IBIS Connector Specification with both the
IBIS Version 3.2 document and a Version 0.23 draft of the IBIS-X document.
Ideally we should have identical descriptions for identical items.  However,
different groups worked on similar sections and injected some different ideas.
We now need review the differences and decide on what to make a standard.

The organization of the Connector Specification is similar to that of the
IBIS-X document.  The Table for Contents shows the keywords.  Bob noted that
the location of [Manufacturer] needs to be discussed since it differs from
IBIS Version 3.2.

Sections 1 (General Introduction) and Section 2 (Statement of Intent) contain  
text that will probably be revised when the document is finalized.  However,
Section 2 gives a good start and needs to be reviewed.

Section 3 (Revision History) currently contains entries to show changes while
the document is evolving, but these will be removed upon release of the
official Version 1.0.

Bob noted some issues and observations in Secton 4 (General Syntax Rules and
Guidelines):

  The file name paragraph is missing and should be added.  The information was
    purposely moved in the Connector Specification document to the [File Name]
    keyword.

  Guideline 11 refers to some sample models.  The samples are obsolete, and
    Bob feels that this section is not necessary or appropriate.

  Guidelines 12 and 13 give some addition numerical recommendations.  This
    should be reviewed.

  A general Begin Header Guideline that is in the IBIS-X document is missing.
    (Adding Begin Header was done as a recent revision.)   The statement in
    in IBIS-X allows for any text before [Begin Header] rather than just the
    default comment character.  This was done to allow HTML tags to be used
    for Web formatting.

Section 5 (Keyword Tree Diagram) is very helpful is probably necessary when
reading the Connector Specification as a roadmap to show how keywords relate
to each other.  The tree itself reveals some issues.  [Manufacturer] is listed
twice.  [Disclaimer] and [Copyright] are listed together.  Bob showed how
significant sections are now blocked by [Begin ..] [End ..] keywords.

Stephen Peters stated that IBIS-X should also have a tree diagram section.

Bob then covered Section 6 (Keywords).  Section 6 should be called IBIS File
Header and another section is needed for Global Keywords (such as the
[Comment Char] keyword), similar to IBIS-X.  Bob briefly pointed out some
issues and observations in Section 6.

  The format for each keyword is similar to IBIS Version 3.2, except an
    Argument: line is added.

  Bob asked if [Notes] is global.  Stephen thought is was just a Header
    keyword.  Bob suggested checking with ibischk3.  [Bob checked and it is
    just a header keyword that cannot be placed randomly in the file.]

  Due to merging of some text, a number of Header keywords need some extra
    text removed.  The [IBIS Cn Model Ver] keyword is no longer the first
    keyword.  It appears directly after the [Begin Header] keyword.

  As previously mentioned, [Disclaimer] and [Copyright] should be documented
    as two keywords in both the Connector Specification and the IBIS-X 
    document.

  Some of the line and file length conditions are different.  Both new
    documents have a common 120 character limit on each line.  

  There are a number of editorial errors and incorrect entries (such as Text
    Block instead of Test String for Arguments) that can be handled off-line.
    This is revealed by direct comparison of the IBIS-X and Connector
    Specification documents.

  The [Notes] text needs to be changed since the new keyword [Redistribution
    Text] was added in case the new required keyword [Redistribution] is
    listed as "Specific".  Bob pointed out that required [Redistribution]
    keyword allows EDA tools to automatically detect if a file can be sent
    anywhere ("Yes") or if it was provided by the vendor with restrictions
    (designated by "No" or "Specific").

This short review revealed that a more detailed examination is needed.  Also
some editorial changes can be identified.  Bob and Stephen will work with Gus
Panella to resolve and correct some of the differences noted so far.


IBIS FUTURES (IBIS-X, API, BIRDxx)
Stephen Peters reported on the IBIS Futures Working Group Meetings of April 3,
2001 and April 17, 2001.  The Working Group meets bi-weekly, and the next
meeting is scheduled on May 1, 2001.

As previously mentioned, the IBIS Futures Working Group is interested in 
alignment with the IBIS Connector Specification.

Stephen indicated that the Working Group needs to document what has been done.
Anyone interested in technical writing is welcome to join and help out.  The
following documents are being written:

   IBIS-X Header Specification
   Macro Language Document
   Library Document for the IBIS Model section in IBIS-X format

Bob Ross noted that a top level link has been added to the EIA IBIS Open Forum
home page to the IBIS Futures Working Group documents.  So far it contains
minutes of meetings and a few older documents.  Some more recent documents
need to be uploaded.


BIRD70.2 - GOLDEN WAVEFORMS
Greg Edlund introduced the changes leading to BIRD70.2.  Top-level keywords
[Test Data] and [Test Load] were introduced.  The [Test Data] section contains
[Rising Waveform Near], [Rising Waveform Far], [Falling Waveform Near] and
[Falling Waveform Far].  Greg added the Test_data_type and Test_load_type
subparameters which have "Single-ended" or "Differential" arguments.  He also
expanded the differential load to include R_diff_near and R_diff_far.  Larry
Barnes asked where these were attached, and Greg responded that they attach to
the nodes at each end of the transmission line.  Greg also revised and added
detail on timing correlation portion of BIRD70.2. 

Bob Ross commented that it was important to provide for differential golden
waveforms in a very robust manner consistent with current technologies.  This
would take only a few additions to the base that has been established.  The
additions would include [Test Data] keywords and [Test Load] subparameters for
the case of different inverting and non-inverting drivers and receivers:

  [Differential Waveform Near]
  [Differential Waveform Far]
  Driver_model_inverting
  Receiver_model_inverting

Bob did not have time to study the timing parameters introduced in BIRD70.2.
Issues still exist in this area.  Also, other parameters might be needed
for differential operation.  Futhermore, all of the cases of Differential and
Single-ended loads and data need to be examined for consistency.

Greg stated that he wanted private feedback from EDA and semiconductor vendors
concerning if there are any difficulties with providing the data or
implementing the specified tests described in BIRD70.2.  Roy Leventhal
supported getting the input.


IBISCHK3 BUG TRACKING (Other Pending BIRDs was moved to the end)
Bob Ross reported that he contacted Atul Agarwal for a quote on the work
he has done and will do to fix Bugs up through pending BUG56.  The estimate
was $3126.  Bob thought this was reasonable and we should expect to pay Atul
this year, upon completion.

Bob stated Syed is still planning to upload the Linux executable for ibischk3
Version 3.2.7. 

- BUG54 - Corners with NA give Bad Test Load Warnings
  Bob Ross commented that he finally studied the test case given for BUG54 and
  the nature of BUG54.  It documents that a Warning is properly not issued if
  [Pullup] table with 0 A entries is included.  The Warning is incorrectly
  issued if this table is (correctly) omitted.  Michael Mirmak confirmed that
  this is the case.  There are other concerns regarding the interpretation of
  NA in min and max tables, but Michael wanted to simplify the issue to deal
  with the [Pullup] table problem.  Bob concurred and felt that we should not
  try to deal with an any more general problem.

  The consensus was to fix BUG54 to eliminate the Warning message dependency
  on the [Pullup] table.

- BUG56 Parser Fails to Detect Always Flowing Current
  Matthew Flora introduced BUG56 indicating that he has seen IBIS models with
  clamp tables documenting that currents are always flowing.  Matthew feels 
  that this is not what IBIS intended, nor does it represent how physical
  devices normally operate.

  Bob Ross stated that current sources were syntactically legal in IBIS and
  there was no reason to restrict them.  However, Matthew's concerns were valid
  since in most devices the current does shut down or change direction at
  some point in an I-V table.  It is most likely to be a model error if this
  is not the case.  Larry Barnes indicated that current sources could exist
  in terminators.

  Bob proposed that a Warning could be issued if the current in an I-V table
  did not cross zero or did not approach zero to within some reasonably low
  (noise) value.

  Al Davis stated that [Gnd Clamp] tables and [Power Clamp] tables should
  cross 0 A at a common point and that current sources were not proper.

  Since we were running out of time, we did not reach closure on how to
  resolve BUG56.  This discussion will be continued at the next meeting.


OTHER PENDING BIRDS (moved to the end)
Bob Ross outlined very briefly some of the needed BIRDs.  We need a possible
fallback submodel BIRD that is decoupled from another one discussed previously
for [Driver Schedule] improvement for SCSI operation is needed.  We also need
the PCI BIRD and the SSO BIRD.


NEXT MEETING:
The next teleconference meeting will be on Friday, May 11, 2001, from
8:00 AM to 10:00 AM.  Stephen Peters will chair this meeting.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            stephen.peters@intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            roy_leventhal@3com.com
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            jangulo@innoveda.com
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================

 
From owner-ibis Tue Apr 24 08:42:55 2001
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From: guy@camarillo.innoveda.com (Guy de Burgh)
Message-Id: <200104241542.IAA03101@f22.innoveda.com>
To: ibis@eda.org
Subject: DAC 2001 IBIS Meeting Announcement


             D A C   2 0 0 1   I B I S   S U M M I T   M E E T I N G
                       F I R S T   A N N O U N C E M E N T

DATE:      Thursday, June 21, 2001
TIME:      8:30 AM - 5:00 PM

CITY:      Las Vegas, Nevada

LOCATION:  Las Vegas Hilton Hotel (adjacent to the Convention Center)

ROOM:      To be Announced

LUNCH:     Free Refreshments and Lunch will be provided.

AGENDA:    The agenda is being planned.  Some planned items are:

             Election of Officers for 2001 - 2002

             Connector Specification

             IBIS-X

             IBIS Version 4.0 Issues

             Possibly other topics such as enhanced buffer extraction
             and driver schedule modeling.

           We welcome presentations and discussions on IBIS topics.


DAC 2001:  DAC is scheduled Monday - Friday, June 18 - 22, 2001.
           The exhibitor portion is open from Monday - Wednesday.
           For more information on DAC 2001 activities, housing, etc.,
           visit the DAC URL:

DAC URL:   http://www.dac.com/


CALL FOR PRESENTATIONS:

           We are also open to technical presentations (usually 30 minutes
           or less) related to any current IBIS activity and to future IBIS
           needs.
 
           Contact Guy de Burgh regarding your presentation:

              Presenter:
              Title:
              Estimated Time:

           Please plan to use regular overhead slides for the presentation.
           It is possible that an LCD projector will be available, but do
           not assume this to be so at this time.

           We would like you to provide handouts for the meeting (about 25)
           and also an electronic copy for archiving.
          

CALL FOR ATTENDEES:

           Please let Guy de Burgh know if you are planning to attend so
           we have an estimate on food requirements. 


CONTACT:   Guy de Burgh
           IBIS Secretary
           gdeburgh@innoveda.com
           (805) 988-8250 ext. 6823

 
From owner-ibis Wed Apr 25 16:55:26 2001
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Date: Wed, 25 Apr 2001 16:54:43 -0700
From: Bob Ross <bob_ross@mentorg.com>
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To All:

For your information and reference, an unofficial draft
of a document being developed for EMC modeling has been
uploaded for review under

  http://www.eda.org/pub/ibis/emc/

The document is ICEMmodel.doc.  Some other related
material has also been uploaded.

This official document will contain editorial
revisions per some IEC Guidelines and will be issued
later.

Comments are welcome.

Bob Ross
Mentor Graphics.
 
From owner-ibis Fri Apr 27 01:40:14 2001
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From: "=?iso-8859-1?Q?Enrique_Mart=EDn_Adalid?=" <eadalid@crisa.es>
To: <ibis@eda.org>
Subject: Looking for IBIS models
Date: Fri, 27 Apr 2001 10:43:20 +0200
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I´m looking for IBIS models -whose manufacturers don´t appear in your
excellent page (eigroup.org)-. Exactly:

- Temic (or Atmel) MG2T technology
- White Electronics Design WMS512K8 and WS512K38

Any Suggestion?

Best Regards,

E. Martin Adalid
eadalid@crisa.es

 
From owner-ibis Mon Apr 30 15:20:36 2001
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Subject: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support PCI & PCI-X
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To IBIS Committee:

Stephen Peters is submitting BIRD71 for consideration in IBIS Version 4.0.

Bob Ross
Mentor Graphics


******************************************************************************
******************************************************************************

BIRD ID#:       71
ISSUE TITLE:    Timing Test Loads in [Model Spec] to Support PCI & PCI-X
REQUESTER:      Stephen Peters, Intel Corp.
DATE SUBMITTED:  April 30, 2001
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

    The IBIS specification lacks a way to specify minimum and maximum values 
for timing test load parameters.  In addition, the current set of timing test 
load parameters (Cref, Rref) are applied to both edges of an output waveform,
thus making them inadequate for describing the timing tests loads used by 
the PCI-X bus specification.   

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following additional subparameters are added to the [Model Spec] keyword:
Cref, Rref, Vref_rising, Vref_falling, Cref_rising, Cref_falling, Rref_rising, 
Rref_falling, Vmeas_rising, Vmeas_falling.

Changes and additions to the [Model Spec] keyword are shown by the |* lines

|=============================================================================
|     Keyword:  [Model Spec]
|    Required:  No
|  Sub-Params:  Vinh, Vinl, Vinh+, Vinh-, Vinl+, Vinl-, S_overshoot_high,
|               S_overshoot_low, D_overshoot_high, D_overshoot_low,
|               D_overshoot_time, Pulse_high, Pulse_low, Pulse_time, Vmeas
|*              Vref, Cref, Rref, Cref_rising, Cref_falling, Rref_rising,
|*              Rref_falling, Vref_rising, Vref_falling, Vmeas_rising, 
|*              Vmeas_falling.
| Description:  The [Model Spec] keyword defines four columns under which
|               specification subparameters are defined.
|
|               The following subparameters are defined:
|               Vinh               Input voltage threshold high
|               Vinl               Input voltage threshold low
|               Vinh+              Hysteresis threshold high max Vt+
|               Vinh-              Hysteresis threshold high min Vt+
|               Vinl+              Hysteresis threshold low max Vt-
|               Vinl-              Hysteresis threshold low min Vt-
|               S_overshoot_high   Static overshoot high voltage
|               S_overshoot_low    Static overshoot low voltage
|               D_overshoot_high   Dynamic overshoot high voltage
|               D_overshoot_low    Dynamic overshoot low voltage
|               D_overshoot_time   Dynamic overshoot time
|               Pulse_high         Pulse immunity high voltage
|               Pulse_low          Pulse immunity low voltage
|               Pulse_time         Pulse immunity time
|
|       Vmeas              Measurement voltage for timing measurements
|       Vref               Timing specification test load voltage
|*       Cref               Timing specification capacitive load
|*       Rref               Timing specification resistance load
|*       Cref_rising        Timing spec capacitive load for rising edges
|*       Cref_falling       Timing spec capacitive load for falling edges
|*       Rref_rising        Timing spec resistance load for rising edges
|*       Rref_falling       Timing spec resistance load for falling edges
|*       Vref_rising        Timing spec test load voltage for rising edges
|*       Vref_falling       Timing spec test load voltage for falling edges
|*       Vmeas_rising       Measurement voltage for rising edge timing
|*                             measurements
|*       Vmeas_falling      Measurement voltage for falling edge timing
|*                             measurements
|
| Usage Rules:  [Model Spec] must follow all other subparameters under the
|               [Model] keyword.
|
|               For each subparameter contained in the first column, the
|               remaining three hold its typical, minimum and maximum values.
|               The entries of typical, minimum and maximum be must be placed
|               on a single line and must be separated by at least one white
|               space or tab character.  All four columns are required under
|               the [Model Spec] keyword.  However, data is required only in
|               the typical column.  If minimum and/or maximum values are not
|               available, the reserved word "NA" must be used indicating the
|               typical value by default.
|
|               The minimum and maximum values are used for specifications
|               subparameter values that may track the min and max operation
|               conditions of the [Model].  Usually it is related to the
|               Voltage Range settings.
|
|               Unless noted below, each subparameter does not require having
|               any other subparameter.
|
|               Vinh, Vinl rules:
|
|               The threshold subparameter lines provide additional min and
|               max column values, if needed.  The typ column values are still
|               required and would be expected to override the Vinh and Vinl
|               subparameter values specified elsewhere.  Note: the syntax
|               rule that require inserting Vinh and Vinl under models remains
|               unchanged even if the values are defined under the [Model
|               Spec] keyword.
|
|               To mimic a hysteresis effect, the values of Vinh and Vinl may
|               be interchanged such that the Vinl value is larger than the
|               Vinh value.  However, simulators may process this information
|               differently or report an error.
|
|               Vinh+, Vinh-, Vinl+, Vinl- rules:
|
|               The four hysteresis subparmeters must all be defined before
|               the hysteresis threshold rules become effective.  Otherwise
|               the standard threshold subparameters remain in effect.  The
|               hysteresis thresholds shall be at the Vinh+ and Vinh- values
|               for a low-to-high transition, and at the Vinl+ and Vinl-
|               values for a high-to-low transition.
|
|               S_overshoot_high, S_overshoot_low rules:
|
|               The static overshoot subparameters provide the voltage values
|               for which the model is no longer guaranteed to function
|               correctly.
|
|               D_overshoot_high, D_overshoot_low, D_overshoot_time rules:
|
|               The dynamic overshoot values provide a time window during
|               which the overshoot may exceed the static overshoot limits
|               but be below the dynamic overshoot limits.  D_overshoot_time
|               is required for dynamic overshoot testing.  In addition, if
|               D_overshoot_high is specified, then S_overshoot_high is
|               necessary for testing beyond the static limit.  Similarly, if
|               D_overshoot_low is specified, then S_overshoot_low is
|               necessary for testing beyond the static limit.
|
|               Pulse_high, Pulse_low, Pulse_time rules:
|
|               The pulse immunity values provide a time window during which
|               a rising pulse may exceed the nearest threshold value but
|               be below the pulse voltage value and still not cause the
|               input to switch.  Pulse_time is required for pulse immunity
|               testing.  A rising response is tested only if Pulse_high is
|               specified.  Similarly, a falling response is tested only if
|               Pulse_low is specified.  The rising response may exceed the
|               Vinl value, but remain below the Pulse_high value.
|               Similarly, the falling response may drop below the Vinh value,
|               but remain above the Pulse_low value.  In either case the
|               input is regarded as immune to switching if the responses
|               are within these extended windows.  If the hysteresis
|               thresholds are defined, then the rising response shall use
|               Vinh- as the reference voltage, and the falling response shall
|               use Vinl+ as the reference voltage.
|
|*             Vmeas, Vref, Cref, Rref rules:
|*
|*             The Vmeas, Vref, Cref and Rref values under the [Model Spec]
|*             keyword override their respective values entered elsewhere.
|*             Note that a Vmeas, Vref, Cref or Rref subparameters may not be
|*             used if its edge specific version (*_rising or *_falling) is
|*             used.
|*
|*             Cref_rising, Cref_falling, Rref_rising, Rref_falling,
|*             Vref_rising, Vref_falling, Vmeas_rising, Vmeas_falling rules:
|*
|*             Use these subparameters when specifying separate timing test
|*             loads and voltages for rising and falling edges.  If one
|*             'rising' or 'falling' subparameter is used, then the
|*             corresponding 'rising' or 'falling' subparameter must be
|*             present.  The values listed in these subparameters override any
|*             corresponding Cref, Vref, Rref or Vmeas values entered
|*             elsewhere.

|-----------------------------------------------------------------------------
[Model Spec]
|   Subparameter          typ        min        max
|
| Thresholds
|
Vinh                      3.5        3.15       3.85    | 70% of Vcc
Vinl                      1.5        1.35       1.65    | 30% of Vcc
|
| Vinh                    3.835       3.335     4.335   | Offset from Vcc
| Vinl                    3.525       3.025     4.025   | for PECL
|
| Hysteresis
|
Vinh+                     2.0        NA         NA      | Overrides the
Vinh-                     1.6        NA         NA      | thresholds
Vinl+                     1.1        NA         NA
Vinl-                     0.6        NA         NA      | All 4 are required
|
| Overshoot
|
S_overshoot_high          5.5        5.0        6.0     | Static overshoot
S_overshoot_low          -0.5        NA         NA
D_overshoot_high          6.0        5.5        6.5     | Dynamic overshoot
D_overshoot_low          -1.0       -1.0       -1.0     | requires
|                                                       | D_overshoot_time
D_overshoot_time          20n        20n        20n     | & static overshoot
|
| Pulse Immunity
|
Pulse_high                3V         NA         NA      | Pulse immunity
Pulse_low                 0          NA         NA      | requires
Pulse_time                3n         NA         NA      | Pulse_time
|
| Timing Thresholds
|
Vmeas                     3.68       3.18       4.68    | A 5 volt PECL
|                                                       | example
|
| Timing test load voltage reference example
|
Vref                      1.25       1.15       1.35    |  An SSTL-2 example
|
|*  BEGIN ADDED EXAMPLE
|*
|*  rising and falling timing test load example (values from PCI-X spec)
|*
Cref_falling              10p        10p         10p
Cref_rising               10p        10p         10p
Rref_rising               25         500         25  | typ value not specified
Rref_falling              25         500         25  | typ value not specified
Vref_rising               0          1.5         0     
Vref_falling              3.3        1.5         3.6   
Vmeas_rising              0.941      0.885       1.026 | vmeas = 0.285(vcc)
Vmeas_falling             2.0295     1.845       2.214 | vmeas = 0.615(vcc)
|*
|*   
|*   END ADDED EXAMPLE
|=============================================================================


******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

BIRDxx is issued because of a long standing problem with specifying PCI
compliant drivers.  In PCI 2.2, minimum timing values are specified into
a 0pF load, while maximum timing parameters are specified into a 50pF
load.  There was no way to specify this cleanly in IBIS.

In addition, the PCI-X specification goes even further in specifying separate
timing test loads for maximum rising and falling edges, and a single test
load for the minimum case.  In order to satisy the PCI-X spec all eight
variations of Cref, Vref, Rref and Vmeas has to be included.  Note that the
PCI-X minimum test load is represented by it's Thevinen equivalent.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:


******************************************************************************
 
