From owner-ibis Fri Jun 1 10:07:37 2001 Received: from e1.ny.us.ibm.com ([32.97.182.101]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f51H7Y7n002410 for ; Fri, 1 Jun 2001 10:07:36 -0700 (PDT) Received: from northrelay02.pok.ibm.com (northrelay02.pok.ibm.com [9.117.200.22]) by e1.ny.us.ibm.com (8.9.3/8.9.3) with ESMTP id NAA99062 for ; Fri, 1 Jun 2001 13:04:31 -0400 Received: from d27ml104.rchland.ibm.com (d27ml104.rchland.ibm.com [9.5.39.61]) by northrelay02.pok.ibm.com (8.8.8m3/NCO v4.96) with ESMTP id NAA85800 for ; Fri, 1 Jun 2001 13:00:36 -0400 Importance: Normal Subject: BIRD 70.3 open issues To: ibis@vhdl.org X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000 Message-ID: From: "Gregory R Edlund" Date: Fri, 1 Jun 2001 12:05:52 -0500 X-MIMETrack: Serialize by Router on d27ml104/27/M/IBM(Release 5.0.7 |March 21, 2001) at 06/01/2001 12:05:54 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii As we discussed in the Open Forum call this morning, there are two unresolved issues related to BIRD 70.3. I would like to clarify the issues in this note and propose a resolution to them so we can move on to a vote. Issue 1: Different inverting and non-inverting drivers This is a legal scenario within IBIS and should be covered by BIRD 70.3. I propose we add a new subparameter Driver_model_inv under [Test Data]. This subparameter is only legal when Test_data_type is differential. I think this is a pretty straight-forward solution to the issue. Any discussion? Issue 2: Legal combinations of Test_data_type and Test_load_type Here are the possible combinations: Case 1: Test_data_type = Single_ended, Test_load_type = Single_ended Case 2: Test_data_type = Single_ended, Test_load_type = Differential Case 3: Test_data_type = Differential, Test_load_type = Single_ended Case 4: Test_data_type = Differential, Test_load_type = Differential Cases 1, 2 and 4 are clear. Cases 1 and 4 are clearly allowed, and Case 2 is clearly NOT allowed. In my opinion, Case 3 should be illegal. If one wanted to capture singled-ended waveforms for a differential driver, one could use Case 1 and just specify the differential driver. I don't see any differences between Case 1 and Case 3. Are there any? Incidentally, this also implies that [Rising Waveform] (and its companions) is legal only for Test_data_type = Single_ended and [Diff Rising Waveform] is legal only for Test_data_type = Differential. I like this solution. It's simple, and it covers the space defined by IBIS. Al Davis proposed a new keyword, [Common Mode Rising Waveform Near], but my gut reaction to this is negative. First, I want to close the BIRD since it's been on the table a long time and is holding up IBIS 4.0. Second, it seems somewhat verbose. I propose that Cases 1 and 4 be legal but Cases 2 and 3 be illegal. Any objections? Greg Edlund Electrical Packaging IBM Server Technology Development 3605 Hwy. 52 N, Dept. HDC Rochester, MN 55901 gedlund@us.ibm.com On Fri, 04 May 2001, Gregory R Edlund wrote: > BIRD 70.3 has four new keywords for differential waveforms. > > I removed the "timing-related" subparameters in favor of using an > extra set of Golden Waveforms that > specify the standard (timing) test load. > > There is still one outstanding issue: what are the legal > combinations of test_data_type and test_load_type? That's easy. Just say they need to be the same. It needs clarification of the meaning of the various waveforms, and which can be used with which type. Something like: Diff waveforms are only used with type differential, and are measured differentially. The other waveforms may be used with either single_ended or differential types. When used with the differential type, they represent the common mode waveforms, measured from one side to ground. It would probably be an improvement to explicitly say they are common-mode, as in [Common Mode Rising Waveform Near], so the Diff or Common forms are used with type differential, and the plain is used with single-ended. Reason: the plain one will be interpreted as the most significant, but in differential mode the differential one really is. From owner-ibis Fri Jun 1 16:58:47 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f51Nwj7n003337 for ; Fri, 1 Jun 2001 16:58:46 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id TAA15863 for ; Fri, 1 Jun 2001 19:57:57 -0400 (EDT) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id TAA29760 for ; Fri, 1 Jun 2001 19:57:56 -0400 (EDT) Received: from f22.innoveda.com (f22.camarillo.innoveda.com [139.181.194.48]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id QAA18184 for ; Fri, 1 Jun 2001 16:57:51 -0700 (PDT) Received: by f22.innoveda.com (SMI-8.6/SMI-SVR4) id QAA02783; Fri, 1 Jun 2001 16:57:53 -0700 Date: Fri, 1 Jun 2001 16:57:53 -0700 From: guy@camarillo.innoveda.com (Guy de Burgh) Message-Id: <200106012357.QAA02783@f22.innoveda.com> To: ibis@eda.org Subject: Third DAC 2001 IBIS Meeting Announcement D A C 2 0 0 1 I B I S S U M M I T M E E T I N G T H I R D A N N O U N C E M E N T DATE: Thursday, June 21, 2001 TIME: 8:30 AM - 5:00 PM CITY: Las Vegas, Nevada LOCATION: Las Vegas Hilton Hotel (adjacent to the Convention Center) ROOM: Announced on the day at the hotel. LUNCH: Free Refreshments and Lunch will be provided. AGENDA: Some Planned Agenda Topics: IBIS Status Bob Ross, Mentor Graphics Election of Officers for 2001 - 2002 Enhanced Buffer Extraction Hazem Hegazy, Mentor Graphics SCSI, Fibre Channel IBIS Modeling Overview Larry Barnes, LSI Logic Driver Schedule Modeling for SCSI Chris Reid, Mentor Graphics Making Behavioral Models for Frequency Domain Analysis Arpad Muranyi, Intel IBIS Version 4.0 Discussion Bob Ross, Mentor Graphics Connector Specification Discussion Bob Ross, Mentor Graphics IBIS-X Stephen Peters, Intel IBIS Macro Language Stephen Peters, Intel Applying the IBIS Macro Language to New Keywords Al Davis, Consultant EMC Parameters for IBIS Guy de Burgh, Innoveda We welcome presentations and discussions on IBIS topics. DAC 2001: DAC is scheduled Monday - Friday, June 18 - 22, 2001. The exhibitor portion is open from Monday - Wednesday. For more information on DAC 2001 activities, housing, etc., visit the DAC URL: DAC URL: http://www.dac.com/ CALL FOR ATTENDEES: Please let Guy de Burgh (gdeburgh@innoveda.com) know if you are planning to attend so we have an estimate on food requirements. --- # --- From owner-ibis Sun Jun 3 18:17:56 2001 Received: from mailhost.avanticorp.com (mailhost.avanticorp.com [63.167.1.13]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f541Hs7n006738 for ; Sun, 3 Jun 2001 18:17:55 -0700 (PDT) Received: from mailhost.avanticorp.com (localhost [127.0.0.1]) by mailhost.avanticorp.com (8.10.1/8.10.1) with ESMTP id f541H5525841 for ; Sun, 3 Jun 2001 18:17:05 -0700 (PDT) Received: from ally.china.avanticorp.com (ally.china.avanticorp.com [192.168.71.10]) by mailhost.avanticorp.com (8.10.1/8.10.1) with ESMTP id f541Gxr25822; Sun, 3 Jun 2001 18:17:03 -0700 (PDT) Received: from avanticorp.com (batty.china.avanticorp.com [172.21.18.49]) by ally.china.avanticorp.com (8.9.1b+Sun/8.9.3) with ESMTP id JAA07073; Mon, 4 Jun 2001 09:16:53 +0800 (CST) Sender: hlwang@avanticorp.com Message-ID: <3B1AE18E.C636A1E@avanticorp.com> Date: Mon, 04 Jun 2001 09:17:02 +0800 From: Hailong Wang X-Mailer: Mozilla 4.75 [en] (X11; U; SunOS 5.7 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Guy de Burgh CC: ibis@eda.org Subject: Re: Third DAC 2001 IBIS Meeting Announcement References: <200106012357.QAA02783@f22.innoveda.com> Content-Type: multipart/alternative; boundary="------------48884C7F32CC297FCE199220" --------------48884C7F32CC297FCE199220 Content-Type: text/plain; charset=gb2312 Content-Transfer-Encoding: 7bit Hi, All, Could you tell me the relation between .ebd and .sp(netlist for HSpice) file, and how to simulate the .ebd file. Thanks! Guy de Burgh wrote: > D A C 2 0 0 1 I B I S S U M M I T M E E T I N G > T H I R D A N N O U N C E M E N T > > DATE: Thursday, June 21, 2001 > TIME: 8:30 AM - 5:00 PM > > CITY: Las Vegas, Nevada > > LOCATION: Las Vegas Hilton Hotel (adjacent to the Convention Center) > > ROOM: Announced on the day at the hotel. > > LUNCH: Free Refreshments and Lunch will be provided. > > AGENDA: Some Planned Agenda Topics: > > IBIS Status > Bob Ross, Mentor Graphics > Election of Officers for 2001 - 2002 > Enhanced Buffer Extraction > Hazem Hegazy, Mentor Graphics > SCSI, Fibre Channel IBIS Modeling Overview > Larry Barnes, LSI Logic > Driver Schedule Modeling for SCSI > Chris Reid, Mentor Graphics > Making Behavioral Models for Frequency Domain Analysis > Arpad Muranyi, Intel > IBIS Version 4.0 Discussion > Bob Ross, Mentor Graphics > Connector Specification Discussion > Bob Ross, Mentor Graphics > IBIS-X > Stephen Peters, Intel > IBIS Macro Language > Stephen Peters, Intel > Applying the IBIS Macro Language to New Keywords > Al Davis, Consultant > EMC Parameters for IBIS > Guy de Burgh, Innoveda > > We welcome presentations and discussions on IBIS topics. > > DAC 2001: DAC is scheduled Monday - Friday, June 18 - 22, 2001. > The exhibitor portion is open from Monday - Wednesday. > For more information on DAC 2001 activities, housing, etc., > visit the DAC URL: > > DAC URL: http://www.dac.com/ > > CALL FOR ATTENDEES: > > Please let Guy de Burgh (gdeburgh@innoveda.com) know if you are > planning to attend so we have an estimate on food requirements. > > --- # --- -- Best Regards. Hai-long Wang Tel:021-62837026x228 Avant! Shanghai R&D Center, 16th Floor, SunTong InfoPort Plaza No.55, West Huaihai Road, Shanghai, 200030, P.R.China --------------48884C7F32CC297FCE199220 Content-Type: text/html; charset=gb2312 Content-Transfer-Encoding: 7bit Hi, All,
     Could you tell me the relation between .ebd and .sp(netlist for HSpice) file, and how to simulate the .ebd file. Thanks!
 

Guy de Burgh wrote:

             D A C   2 0 0 1   I B I S   S U M M I T   M E E T I N G
                       T H I R D   A N N O U N C E M E N T

DATE:      Thursday, June 21, 2001
TIME:      8:30 AM - 5:00 PM

CITY:      Las Vegas, Nevada

LOCATION:  Las Vegas Hilton Hotel (adjacent to the Convention Center)

ROOM:      Announced on the day at the hotel.

LUNCH:     Free Refreshments and Lunch will be provided.

AGENDA:    Some Planned Agenda Topics:

             IBIS Status
               Bob Ross, Mentor Graphics
             Election of Officers for 2001 - 2002
             Enhanced Buffer Extraction
               Hazem Hegazy, Mentor Graphics
             SCSI, Fibre Channel IBIS Modeling Overview
               Larry Barnes, LSI Logic
             Driver Schedule Modeling for SCSI
               Chris Reid, Mentor Graphics
             Making Behavioral Models for Frequency Domain Analysis
               Arpad Muranyi, Intel
             IBIS Version 4.0 Discussion
               Bob Ross, Mentor Graphics
             Connector Specification Discussion
               Bob Ross, Mentor Graphics
             IBIS-X
               Stephen Peters, Intel
             IBIS Macro Language
               Stephen Peters, Intel
             Applying the IBIS Macro Language to New Keywords
               Al Davis, Consultant
             EMC Parameters for IBIS
               Guy de Burgh, Innoveda

           We welcome presentations and discussions on IBIS topics.

DAC 2001:  DAC is scheduled Monday - Friday, June 18 - 22, 2001.
           The exhibitor portion is open from Monday - Wednesday.
           For more information on DAC 2001 activities, housing, etc.,
           visit the DAC URL:

DAC URL:   http://www.dac.com/

CALL FOR ATTENDEES:

           Please let Guy de Burgh (gdeburgh@innoveda.com) know if you are
           planning to attend so we have an estimate on food requirements.

                                  --- # ---

-- 
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China
  --------------48884C7F32CC297FCE199220-- From owner-ibis Mon Jun 4 10:55:02 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f54Ht07n008695 for ; Mon, 4 Jun 2001 10:55:01 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id NAA23663 for ; Mon, 4 Jun 2001 13:54:10 -0400 (EDT) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id NAA26385 for ; Mon, 4 Jun 2001 13:54:09 -0400 (EDT) Received: from innoveda.com (lap-gdeburgh.camarillo.innoveda.com [139.181.194.159]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with ESMTP id KAA03502 for ; Mon, 4 Jun 2001 10:54:05 -0700 (PDT) Message-ID: <3B1BCAF8.EE19EDE3@innoveda.com> Date: Mon, 04 Jun 2001 10:52:56 -0700 From: Guy de Burgh Organization: Innoveda X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 To: ibis@eda.org Subject: EIA IBIS Open Forum Minutes (6/1/01) Content-Type: multipart/mixed; boundary="------------37D025A2C2C12BA76AF64739" This is a multi-part message in MIME format. --------------37D025A2C2C12BA76AF64739 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------37D025A2C2C12BA76AF64739 Content-Type: text/plain; charset=us-ascii; name="ibis.mins_01jun01" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ibis.mins_01jun01" DATE: 6/4/01 SUBJECT: 6/1/01 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS AND 2001 PARTICIPANTS LIST: 3Com (& CommWorks) Roy Leventhal* Ansoft Corporation (Eric Bracken) Apple Computer John Figueroa Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Balistreri Avanti (Chen Hongyu) Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek Lynne Green*, Lance Wang* Cisco Systems Syed Huq, Lungfu Chen EMC Corporation Brian Arsenault, Jinhua Chen Fairchild Semiconductor Adam Tambone Huawei Technologies Rachild Chen IBM Michael Cohen, Greg Edlund*, Wes Martin, Yeon-Chang Hahm, Bill DeVey, Pravin Patel* Innoveda (& HyperLynx) Guy de Burgh*, John Angulo*, Cary Mandel, Matthew Flora Intel Corporation Stephen Peters*, Arpad Muranyi*, Dave Lorang, Michael Mirmak, Qinglun Chen, Will Hobbs LSI Logic Larry Barnes Mentor Graphics Bob Ross*, Tom Dagostino, Chris Reid, Mike Donnelly, Hazem Hegazy, Tony Dunbar, Griff Derryberry, Dan Lake, Sherif Hammad, Mohammed Korany, Weston Beal, Chris Swaim, Ali Samii, Eric Ronger, Karine Loudet Micron Technology Randy Wolff*, Yong Phan* Mitsubishi (Tam (Tom) Cao) Molex Incorporated Gus Panella, Brian O'Malley Motorola (Rick Kingen) National Semiconductor Milt Schwartz* North East Systems Associates Edward Sayre Philips Semiconductor Zack Ciccone, Rob Mataheroe Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz SiQual Scott McMorrow, Rob Hinz, Bernard Voss, Chris Brewster Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar, Jean Claude Perrin, Moshiul Haque* Time Domain Analysis Systems Dima Smolyansky, Steve Corey Tyco Electronics (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) John Berrie OTHER PARTICIPANTS IN 2001: Actel Corporation Silvia Montoya Acuson Kim Helliwell AMCC Jeff Smith ASIS Ltd David Wright Brocade Communications Robert Badal BMW Friedrich Hasinger Cereva Networks Bob Haller Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam, Bill Ham Cypress (Rajesh Manapat) EADS Airbus Industry Claude Huet (Aerospatiale) EFM Ekkehard Miersch, Horle Raines EIA Cecilia Fleming* FCI Sercu Stefaan Foundary Networks Bertram Chan Framatom Conectors Danny Morlion Fraunhofer Institute Mariusz Faferko, Peter Kralicek Reliability and Integration Fujitsu Ltd Tadashi Arai, Takeshi Murakami Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt Hyundai Electronics Jongho Kang Infineon Technologies Christian Sporrer Intrinsix Corporation Steven Chin National Institute of Applied Etienne Sicard Science (INSA) Nokia Tapani von Ravner, Mika Castren, Janne Uusitalo Nortel Networks Calvin Trowell Oak Technology Darmin Jin Plexus Technology Group Joseph Socha Quantic EMC (Mike Ventham) Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier, Katja Koller, Wolfram Meyer, Eckhard Lenski, Gerald Bannert, Burkhard Muller, Christian Marot, Manfred Maurer, Amir Motamedi, Hans Pichlmaier Sintecs Hans Klos STMicroelectronics Peter Hirt, Fabrice Boissieres Sun Adrian Udenze Xilinx Susan Wu Independent, Consultant Al Davis In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode Thursday June 21, 2001 IBIS Summit Meeting, No Phone Bridge July 20 (888) 316-5901 none 8744603 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum, and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM Lynne Green, who attended the May 11, 2001 IBIS Meeting, from Cadence replaces Ian Dodd and is interested in IBIS-X, the IBIS Connector Specification and other activities. Moshiul Haque from Texas Instruments is an Application Engineer in charge of an IBIS Modeling Team and is interested in bus hold, and future IBIS activities. MEMBERSHIP UPDATE AND TREASURER'S REPORT Bob Ross reported that Huawei Technologies located in China is now an official EIA IBIS Open Forum member and listed as a voting member. Several voting members who have not paid and have not been responsive have been moved to the Other Participants list or have been deleted. We are still contacting several others regarding payment issues. Currently we are up to 29 paid members and are on or ahead of our budget. REVIEW OF MINUTES AND AR'S The May 11, 2001 IBIS Minutes were approved without change. The ARs will be discussed during the meeting. MISCELLANY/ANNOUNCEMENTS Bob Ross asked the officers for dates they might be out during the Summer. Bob reported June 22 through July 17, Stephen Peters reported July 9 through July 20, and Guy de Burgh reported July 13 through July 27. PRESS AND WEB PAGE UPDATES Bob Ross reported that Syed Huq did more updates to the Roster link on the IBIS home page and added a Poster entry. Greg Edlund announced that a suggested checklist.txt has been added to the Accuracy Link of the IBIS home page for checking IBIS models. NEW MODELS AVAILABLE, LIBRARY UPDATE Bob Ross reported some new model links can be found on the Models link page that Roy Leventhal maintains under the IBIS home page: Agilent Technologies models can be found through a search on IBIS and then select Download IBIS Models. Also there is a writeup on IBIS Modeling of their Fiber Optic transceivers. http://www.semiconductor.agilent.com/ Search on IBIS for ServerWorks models: http://www.serverworks.com/ Also, Bob reported that Agere Systems (formerly Lucent Technologies) has an Ambassador IBIS Model: http://www.lucent.com/micro/access/ambassador/ctidoc.cgi A number of other links have changed. Mitel Semiconductor is now Zarlink Semiconductor. You can currently find one model by searching under http://www.zarlink.com/index.html OPENS FOR NEW ISSUES Bob Ross - A Pending ibischk3 BUG INTERNATIONAL/EXTERNAL PROGRESS - IEC 62014-1 (IBIS Version 3.2) - Cecilia reported that the document is listed as being in the prepublication status. - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) - Bob Ross stated that the EIAJ has merged with another group, and he cannot find the link to the IMIC document. - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Bob Ross reported that Etienne Sicard will probably present the work at the September IBIS Summit meeting instead of the DAC IBIS Summit meeting. Bob repeated from the last meeting that there is a subdirectory for EMC data on: http://www.eda.org/pub/ibis/emc/ - JEDEC JC-16 - Modeling and Testing - Bob Ross stated that a discussion on a possible joint meeting is planned later in the agenda. - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the National Committee for Information Technology (NCITS)) - No report since Larry Barnes could not attend this meeting. DESIGN AUTOMATION CONFERENCE 2001 IBIS SUMMIT MEETING PLANS Bob Ross repeated for the minutes the general plans for the next IBIS Summit Meeting. The annual meeting is conducted along with the Design Automation Conference (DAC), held this year in Las Vegas, Nevada. The IBIS Summit Meeting will be in the Hilton Hotel adjacent to the Las Vegas Convention Center. The meeting date is Thursday, June 21, 2001, the day following the trade show portion of DAC. This meeting is sponsored by the IBIS Open Forum through the dues. Guy de Burgh is coordinating the signups, presentations and other local logistics. EIA and Cecilia Fleming is handling the meeting site and luncheon logistics. Bob stated that about 19 people indicated they are attending. Bob estimates that we will have the normal turnout of 20 to 30 people. Current company travel restrictions are having some impact on attendance. Guy de Burgh stated that he is having trouble reserving an LCD projector and suggested asking everyone to bring foil overheads. Bob stated that he prefers foils for better interaction and meeting flow. However, he asked Cecilia Fleming to bring and LCD projector and she agreed. (After the meeting Cecilia indicated that all of her projectors are checked out.) Bob Review the tentative program under development: Administrative Issues - Election of IBIS Officers for 2001 - 2002 Connector Specification Discussion - Bob Ross, Mentor Graphics IBIS-X Discussion - Stephen Peters (2 hours) IBIS-X Document - Stephen Peters, Intel Corporation IBIS Macro Language - Stephen Peters, Intel Corporation Applying IBIS Macro Language to New Keywords - Al Davis, Consultant IBIS Version 4.0 Issues - Bob Ross, Mentor Graphics Enhanced Buffer Extraction - Hazem Hegazy, Mentor Graphics Driver Schedule Modeling - Chris Reid, Mentor Graphics Behavioral Frequency Domain Modeling - Arpad Muranyi, Intel Corp. SCSI and Fiber Channel Overview, Larry Barnes, LSI Logic Guy de Burgh stated that at the end of the meeting that he might have some material on IBIS Modeling for EMC Bob noted that the IBIS Verison 4.0 and Connector Modeling discussion might be brief for this meeting. Bob discussed that for the Election of IBIS Officers, the existing officers (at the end of these Minutes) are all nominated and available for their current positions, except that Stephen Peters, and Bob are planning to switch roles. Stephen is a candidate for Chair and Bob a candidate for Vice-Chair. Other nominations can be sent to Guy de Burgh, and also will be accepted at the meeting. Greg Edlund asked if absentee votes can be cast. Bob responded that we will accept absentee votes. They can be sent to Guy. Bob asked Guy to send out another notice. We have enough topics on the program to fill most of the day, so we do not need to ask for any more. In fact one or two might be proposed at the last minute. Bob will work with Guy to put in the tentative agenda topics in the next announcement. Bob will also issue the actual Agenda one week before the meeting. The meeting is still planned to start at 8:30 AM. People can arrive earlier for refreshments before the meeting. FUTURE IBIS MEETINGS Bob Ross introduced that EIA is planning a multiple organization meeting week next year from September 9 - 13, 2002 in Vancouver, Canada. The IBIS Open Forum is invited to also plan a Summit Meeting there. The organizations include various JEDEC JC4X.Y groups for memories, JC-16 for Modeling and Testing, the Compact Modeling Council for Spice device model standardization, and others. Cecilia Fleming added that a component group will also join. So the purpose of the joint, co-located meeting is to allow individuals from one organization to attend meetings of another organization that may be of related interest. Bob noted that we normally plan the meeting on the East Coast associated with the PCB Conference East in September. So we would have to decide which one to hold. Lynne Green commented that maybe both meetings could be held, and the West Coast joint meeting would appeal to those who normally would not travel to the East Coast meeting. Bob commented that some groups require non-members to be invited. However, Cecilia stated that according to EIA rules, it is permissible for non-members to attend two successive meetings as an observer. Bob concluded that this choice will need to be considered some time next year. IBIS MODEL REVIEW COMMITTEE DISCUSSION John Angulo reported that he received two models. One is ready to be sent out. John asked for more participation as a reviewer, and Lynne Green volunteered. Bob Ross discussed some of the activities and indicated that the reviewers consist of EDA vendors representatives who have access to IBIS Model processing tools. They can actually check the operation of the IBIS Model and report back privately their comments to the semiconductor vendor model provider. Roy Leventhal suggested that Model Review committee also ask if any semiconductor vendor has links to IBIS models on their Web sites. CONNECTOR PROPOSAL REVIEW Bob Ross mentioned that meetings were held on May 15, 2001 and May 29, 2001. The Working Group now consists has several members from the IBIS Futures Work Group. Meetings will be held every week until the week before the IBIS Summit Meeting. the next meeting will be to continue to review the keywords in Chapter 8. Most of the technical content exists in this section and will also be reviewed. The latest document (Version 0.966) uploaded under the Connector link of the IBIS home page. Bob stated that he originally planned to do the review at the IBIS meetings. The technical concerns are probably too difficult to discuss with the whole group at this time. Stephen Peters added that the scope of the meeting are to bring the Connector Specification and the IBIS-X documents into editorial and format alignment. Bob added that two different Working Groups had adopted some different conventions for similar functions, and the differences now need to be resolved. IBIS FUTURES (IBIS-X, API, BIRDxx) Stephen Peters reported that weekly meetings were held on May 15, 2001, May 22, 2001 and May 29, 2001. The meetings follow the Connector Working Group Meetings. The next meetings for both groups are scheduled on June 5, 2001 and June 12, 2001. The top level IBIS-X document Version 0.5 document has been uploaded in the Futures Group link of the IBIS Home page for public review. The Working Group is now writing the outline to produce the IBIS Macro Language document. The past meetings have focused on data structure issues. The above material will be introduced at the IBIS Summit Meeting. Bob Ross thanked Stephen for taking a leading role in both the Connector Specification and IBIS Futures Working Group and in authoring the Working Group documents. BIRD70.3 - GOLDEN WAVEFORMS Greg Edlund stated that the only remaining issue on BIRD70.3 is how the [Test Data] subparameter Test_data_type and [Test Load] subparameter Test_data_type interact. Both subparameters can have "Single-ended" or "Differential" as arguments. The allowable combinations and related restrictions need to be documented. Bob Ross added that another issue is how to deal with the possibility of unsymmetrical differential drivers. Some more subparameters may need to be added. For example, the Driver_model subparameter may also need an optional Driver_model_inv subparameter to document a different inverting driver. These topics were discussed. Lynne Green asked if timing offset can be included in differential golden waveforms. Milt Schwartz commented that most differential applications (such as for LVDS) want the offset time minimized. There are even specifications for common mode variation at a mid point of a differential terminator (AC Coupled to ground). Greg Edlund stated that the intent of the Golden Waveforms was to cross-correlate normal performance with golden performance. Bob concluded that we do not need to add the capability of dealing with differential, skewed Golden Waveforms. During the discussion, Stephen Peters asked what is needed to bring closure. Bob commented that these issues need to be raised and discussed on the IBIS reflector. Greg could issue BIRD70.4, etc. to capture any resolution. One proposal was to allow only both "Differential" or both "Single-ended" choices. However, other combinations and their restrictions still need to be resolved. Greg stated that he will raise the issue on the IBIS reflector and issue BIRD70.4 as we reach agreement. BIRD71 - TIMING TEST LOADS IN [Model Spec] TO SUPPORT PCI & PCI-X Stephen Peters commented that BIRD71 has not been changed since it was introduced at the last meeting. Stephen commented that Arpad Muranyi asked on the IBIS reflector if a more general set of timing test loads were needed. Stephen responded that his intent was to complete the timing specification choices under [Model Spec] to their logical conclusion. In doing so, he checked the PCI specifications to see that all cases were covered. Bob Ross stated that the additions were to document min and max Cref and Rref values and to document all cases where the Cref, Rref, Vref, and Vmeas values can be different for the rising and falling edges. Bob commented that BIRD71 seemed to do this well. His only concern was how the EDA tools were to work with this data. There are two points of view. One is to used the timing subparameters along with the corner conditions to document a worse case load for one of the timing corners. Such corners are documented in some specifications. The second point of view is to use the timing load as a calibration factor for data sheet Tco delays. The IBIS model (for example, a model with [Ramp] based time response) does not capture any Tco delay. Stephen agreed to look at this and perhaps provide some clarification statements in an updated BIRD71.1. Bob stated that he expects BIRD71 to be voted on soon. OTHER PENDING BIRDS Stephen Peters asked what is needed to close out IBIS Version 4.0. Bob Ross stated that completion of BIRD70.3 and BIRD71 are needed. Bob is also considering a fallback submodel additions to capture an effect that the Bus_hold submodel cannot handle for some dynamic output impedance control type operations (where the impedance increases during a transition). Bob believes that the existing [Driver Schedule] keyword will be satisfactory for handling the SCSI second bit strength reduction simulation. So no further work is needed for this. We are still want to consider the simple additions for SSO improvement that Dr. Unger originally proposed a while ago. However, there might be issues with this, or it might be limited to certain topologies. In all cases, BIRDs are needed. Bob stated that he did not have time to follow through on these because of other activities. However, we should expect that all of the related BIRDs will be resolved by around September. We may decide not to include some of the extra features. IBISCHK3 BUG TRACKING - BUG56 Parser Fails to Detect Always Flowing Current Bob Ross stated that the decision to Fix BUG56 was made at the May 11, 2001 meeting. The [Pullup], [Pulldown], [Gnd Clamp] and [Power Clamp] tables would all be checked to see that they cross or reach 0 Volts. Bob needed to know what tolerance to set is there is noise and 0 Volts is not reached exactly. There are several technologies such as ECL where this could occur. Bob stated that he and Matthew Flora and discussed this off-line and Matthew had suggested 1 uV. The group agreed that 1 uV should be the limit. Bob will add this information to BIRD56. - A Pending ibischk3 BUG (New agenda item) Bob Ross stated that normally there is a problem related to the recent BUG53 and BUG34 fixes that introduced both Error and Warning messages based on the degree of waveform mismatch. A greater than 10 percent difference produces an error. One problem is that the mismatch check itself may not work properly if there are legal non-monotonic points in the output table in, for example the clamping region. The ibischk3 testing algorithm appears to start searching for converge at the end rather than at the middle. The consequence is that a legal IBIS model with no mismatch may be rejected by an Error message. This issue is whether to fix the algorithm, or to change the Error back to a Warning. A second problem is in some cases some percentages for Warning messages are wrong. Normally Bob would actually issue the BUG report before discussing a BUG, but he wanted to alert the committee of a pending BUG and its choices. END OF MEETING TOPIC Pravin Patel asked about some work Guy de Burgh might have presented regarding EMC modeling in IBIS. Guy responded that he has some ideas on parameters that are needed and might discuss this at the IBIS Summit Meeting in June, 2001. (Note, this is added to the possible list of topics on the Agenda.) NEXT MEETING: The next meeting will be the DAC2001 IBIS Summit Meeting in Las Vegas, Nevada, scheduled all day on June 21, 2001. No teleconference connection is planned. The next teleconference meeting will be on Friday, July 20, 2001, from 8:00 AM to 10:00 AM. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 stephen.peters@intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799 roy_leventhal@3com.com Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary) 1800 W. Central Rd. Mt. Prospect, IL 60056-2293 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 jangulo@innoveda.com Development Engineer, Innoveda 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== --------------37D025A2C2C12BA76AF64739-- From owner-ibis Wed Jun 6 10:16:10 2001 Received: from jester.ti.com (jester.ti.com [192.94.94.1]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f56HG77n016810 for ; Wed, 6 Jun 2001 10:16:09 -0700 (PDT) Received: from dlep7.itg.ti.com ([157.170.134.103]) by jester.ti.com (8.11.1/8.11.1) with ESMTP id f56HFGL26393 for ; Wed, 6 Jun 2001 12:15:16 -0500 (CDT) Received: from dlep7.itg.ti.com (localhost [127.0.0.1]) by dlep7.itg.ti.com (8.9.3/8.9.3) with ESMTP id MAA23183 for ; Wed, 6 Jun 2001 12:15:15 -0500 (CDT) Received: from dlee71.itg.ti.com (dlee71.itg.ti.com [157.170.135.149]) by dlep7.itg.ti.com (8.9.3/8.9.3) with ESMTP id MAA23166 for ; Wed, 6 Jun 2001 12:15:15 -0500 (CDT) Received: by dlee71.itg.ti.com with Internet Mail Service (5.5.2650.21) id ; Wed, 6 Jun 2001 12:15:14 -0500 Message-ID: From: "Haque, Moshiul" To: "Ibis (E-mail)" Subject: FET Switch IBIS Model Date: Wed, 6 Jun 2001 12:15:05 -0500 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2650.21) Content-Type: text/plain; charset="windows-1252" Hi, Anybody have an idea on which EDA tools support FET switch IBIS model? Thanks. Moshiul Haque Applications Engineer Texas Instruments From owner-ibis Thu Jun 7 13:16:44 2001 Received: from mailgate2.Cadence.COM (mailgate2.Cadence.COM [158.140.2.31]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f57KGe7n021323 for ; Thu, 7 Jun 2001 13:16:42 -0700 (PDT) Received: from gda.Cadence.COM (gda.Cadence.COM [158.140.106.10]) by mailgate2.Cadence.COM (8.9.3/8.9.3) with ESMTP id NAA09350; Thu, 7 Jun 2001 13:14:46 -0700 (PDT) Received: from pc-lgreen.cadence.com ([158.140.154.202]) by gda.Cadence.COM (8.10.1/8.8.5) with ESMTP id f57KEfB04024; Thu, 7 Jun 2001 16:14:41 -0400 (EDT) Message-Id: <5.0.2.1.2.20010607131150.00ac8498@gda.cadence.com> X-Sender: lgreen@gda.cadence.com X-Mailer: QUALCOMM Windows Eudora Version 5.0.2 Date: Thu, 07 Jun 2001 13:14:43 -0700 To: mhaque@ti.com From: Lynne Green Subject: Re: FET Switch IBIS Model Cc: ibis@eda.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; format=flowed X-Received: By mailgate2.Cadence.COM as NAA09350 at Thu Jun 7 13:14:46 2001 In reply to your request: SpecctraQuest (Cadence Designs Systems, Inc) supports the IBIS switch model. - Lynne > >----- Original Message ----- > >From: "Haque, Moshiul" > >To: "Ibis (E-mail)" > >Sent: Wednesday, June 06, 2001 1:15 PM > >Subject: FET Switch IBIS Model > > > > > > Hi, > > Anybody have an idea on which EDA tools support FET switch IBIS model? > > > > Thanks. > > Moshiul Haque > > Applications Engineer > > Texas Instruments > > From owner-ibis Tue Jun 12 10:53:07 2001 Received: from mtvwca1-smrly1.gtei.net (mtvwca1-smrly1.gtei.net [128.11.176.196]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CHr57n007562 for ; Tue, 12 Jun 2001 10:53:07 -0700 (PDT) Received: from fairchild3-cp-fc.fairchildsemi.com (smtp2-fc.fairchildsemi.com [192.233.132.91]) by mtvwca1-smrly1.gtei.net (Postfix) with SMTP id 6F1223BA6 for ; Tue, 12 Jun 2001 17:52:11 +0000 (GMT) Received: FROM dnsbak.fairchildsemi.com BY hqnttest01.fairchildsemi.com ; Tue Jun 12 13:50:25 2001 -0400 Received: from notes.fairchildsemi.com (fsce16.fairchildsemi.com [172.21.18.66]) by dnsbak.fairchildsemi.com (8.9.3+Sun/8.9.3) with ESMTP id NAA02921 for ; Tue, 12 Jun 2001 13:51:28 -0400 (EDT) Subject: BIRD 68.1 To: ibis@eda.org From: Adam.Tambone@fairchildsemi.com Date: Tue, 12 Jun 2001 13:50:51 -0400 Message-ID: X-MIMETrack: Serialize by Router on SPNOTES01/Corporate/FSC(Release 5.0.6a |January 17, 2001) at 06/12/2001 01:50:52 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii Hello All, I have question regarding BIRD 68.1. Does the BIRD state that if the recommendations within it are followed ( i.e. if the v-t tables for rising and falling begin at the same time as the rising and falling edges of the input stimulus, and additional delay is introduced to account for delay not within the buffers ) then undistorted duty cycles will be represented in simulation? Thanks, Adam Tambone From owner-ibis Tue Jun 12 11:00:40 2001 Received: from mailgate.Cadence.COM (mailgate.Cadence.COM [158.140.2.1]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CI0b7n007585 for ; Tue, 12 Jun 2001 11:00:39 -0700 (PDT) Received: from sbsun5a.Cadence.COM (sbsun5a.Cadence.COM [139.99.82.1]) by mailgate.Cadence.COM (8.9.3/8.9.3) with ESMTP id KAA17265 for ; Tue, 12 Jun 2001 10:59:42 -0700 (PDT) Received: from pc-aholmes (d1399982177.Cadence.COM [139.99.82.177]) by sbsun5a.Cadence.COM (8.8.5/8.8.5) with SMTP id KAA04104 for ; Tue, 12 Jun 2001 10:59:41 -0700 (PDT) Message-Id: <3.0.5.32.20010612110241.00919350@sbsun5a.cadence.com> X-Sender: aholmes@sbsun5a.cadence.com X-Mailer: QUALCOMM Windows Eudora Pro Version 3.0.5 (32) Date: Tue, 12 Jun 2001 11:02:41 -0700 To: ibis@eda.org From: Andrew Holmes Subject: RE: IBIS 3.2 model error Mime-Version: 1.0 Content-Type: text/enriched; charset="us-ascii" X-Received: By mailgate.Cadence.COM as KAA17265 at Tue Jun 12 10:59:42 2001 I am getting the following error on an IBIS 3.2 LVDS input model when I run a check. The error is: Courierchecking lvdsiflv33c.ibs for IBIS 3.2 Compatibility... ERROR - Component 'lvdsiflv33c': [Series Pin Mapping] Pin2 '2': model type cannot be Series or Series_switch. Errors : 1 File Failed Not sure how I should interpret this. The Series model defined looks correct and so does the Series Pin Mapping as defined by the 3.2 spec. Any feedback would be appreciated. Thanks, Andy Andy Holmes Tality (formerly Cadence Design Systems) 6950 Hollister Avenue, Suite 200 Santa Barbara, CA 93117 PH# 805-571-1206 FAX 805-571-1300 aholmes@tality.com From owner-ibis Tue Jun 12 12:12:20 2001 Received: from mailgate.Cadence.COM (mailgate.Cadence.COM [158.140.2.1]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CJC77n007772 for ; Tue, 12 Jun 2001 12:12:12 -0700 (PDT) Received: from kenny.Cadence.COM (kenny.Cadence.COM [158.140.103.100]) by mailgate.Cadence.COM (8.9.3/8.9.3) with ESMTP id MAA05515; Tue, 12 Jun 2001 12:11:06 -0700 (PDT) Received: from pclang2 (d158140106195 [158.140.106.195]) by kenny.Cadence.COM (8.9.3/8.8.5) with SMTP id PAA03204; Tue, 12 Jun 2001 15:10:51 -0400 (EDT) Message-ID: <011c01c0f373$65454140$c36a8c9e@cadence.com> From: "Lance Wang" To: "Andrew Holmes" Cc: References: <3.0.5.32.20010612110241.00919350@sbsun5a.cadence.com> Subject: Re: IBIS 3.2 model error Date: Tue, 12 Jun 2001 15:10:50 -0400 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0119_01C0F351.DE0BF500" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 X-Received: By mailgate.Cadence.COM as MAA05515 at Tue Jun 12 12:11:06 2001 This is a multi-part message in MIME format. ------=_NextPart_000_0119_01C0F351.DE0BF500 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, Andrew,=20 I met the same problem before. This is because, in the [Series Pin = Mapping] section. You have the model name called series_switch or = series. It is not a good idea to use them as a model name. But it is = legal! You can live with it in Cadence tools. Try to rename it and see what happens. I think this is bug of IBIS GOLDEN PARSER. At least it didn't tell you = which problem you met. -Lance Liqun Wang (Lance) Cadence Design Systems, Inc. PSD High Speed Development PH:978-446-6685 FAX:978-446-6363 ----- Original Message -----=20 From: Andrew Holmes=20 To: ibis@eda.org=20 Sent: Tuesday, June 12, 2001 2:02 PM Subject: RE: IBIS 3.2 model error I am getting the following error on an IBIS 3.2 LVDS input model when = I run a check. The error is: checking lvdsiflv33c.ibs for IBIS 3.2 = Compatibility... ERROR - Component 'lvdsiflv33c': [Series Pin = Mapping] Pin2 '2': model type cannot be Series or Series_switch. Errors : 1 File Failed Not sure how I should interpret this. The Series model defined looks = correct and so does the Series Pin Mapping as defined by the 3.2 spec.=20 Any feedback would be appreciated. Thanks, Andy Andy Holmes Tality (formerly Cadence Design Systems) 6950 Hollister Avenue, Suite 200 Santa Barbara, CA 93117 PH# 805-571-1206 FAX 805-571-1300 aholmes@tality.com=20 ------=_NextPart_000_0119_01C0F351.DE0BF500 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hi, Andrew,
I met the same problem before. This is = because,=20  in the [Series Pin Mapping] section. You have the model name = called=20 series_switch or series. It is not a good idea to use them as a model = name. But=20 it is legal! You can live with it in Cadence tools.
 
Try to rename it and see what = happens.
 
I  think this is bug of IBIS = GOLDEN PARSER. At=20 least it didn't tell you which problem you met.
 
-Lance
 
Liqun Wang (Lance)
Cadence Design = Systems,=20 Inc.
PSD High Speed=20 Development
PH:978-446-6685
FAX:978-446-6363
----- Original Message -----
From:=20 Andrew Holmes=20
Sent: Tuesday, June 12, 2001 = 2:02=20 PM
Subject: RE: IBIS 3.2 model = error

I am getting the following error on an IBIS 3.2 LVDS = input=20 model when I run a check. The error is:

checking=20 lvdsiflv33c.ibs for IBIS 3.2 = Compatibility...

ERROR -=20 Component 'lvdsiflv33c': [Series Pin Mapping] Pin2 = '2':=20 model type cannot be Series or = Series_switch.

Errors=20 : 1

File=20 = Failed

Not=20 sure how I should interpret this. The Series model defined looks = correct and=20 so does the Series Pin Mapping as defined by the 3.2 spec.

Any = feedback would be appreciated.

Thanks,

Andy
Andy=20 Holmes
Tality (formerly Cadence Design Systems)
6950 Hollister = Avenue,=20 Suite 200
Santa Barbara, CA 93117
PH# 805-571-1206
FAX=20 805-571-1300
aholmes@tality.com
------=_NextPart_000_0119_01C0F351.DE0BF500-- From owner-ibis Tue Jun 12 13:28:07 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CKS27n007949 for ; Tue, 12 Jun 2001 13:28:06 -0700 (PDT) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id NAA19200; Tue, 12 Jun 2001 13:26:44 -0700 (PDT) Received: from mentor.com (bob.wv.mentorg.com [147.34.70.103]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id MXC41YTR; Tue, 12 Jun 2001 13:27:28 -0700 Sender: bobr@relay1.mentorg.com Message-ID: <3B267B02.B1B3CA55@mentor.com> Date: Tue, 12 Jun 2001 13:26:42 -0700 From: Bob Ross X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Andrew Holmes CC: ibis@eda.org Subject: Re: IBIS 3.2 model error References: <3.0.5.32.20010612110241.00919350@sbsun5a.cadence.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Andy: There was a bug in ibischk3 Version 3.2.6 and below regarding not allowing the series or series switch elements to be attached to I/O buffers (a late specification change). This is documented as bug40 under http://www.eda.org/pub/ibis/bugs/ibischk/ Try ibischk3 Version 3.2.7 found under http://www.eda.org/pub/ibis/ibischk3/ Bob Ross Mentor Graphics > Andrew Holmes wrote: > > I am getting the following error on an IBIS 3.2 LVDS input model when I run a > check. The error is: > > checking lvdsiflv33c.ibs for IBIS 3.2 Compatibility... > > ERROR - Component 'lvdsiflv33c': [Series Pin Mapping] Pin2 '2': model type > cannot be Series or Series_switch. > > Errors : 1 > > File Failed > > Not sure how I should interpret this. The Series model defined looks correct > and so does the Series Pin Mapping as defined by the 3.2 spec. > > Any feedback would be appreciated. > > Thanks, > > Andy > > Andy Holmes > > Tality (formerly Cadence Design Systems) > > 6950 Hollister Avenue, Suite 200 > > Santa Barbara, CA 93117 > > PH# 805-571-1206 > > FAX 805-571-1300 > > aholmes@tality.com From owner-ibis Tue Jun 12 14:09:49 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CL9k7n008083 for ; Tue, 12 Jun 2001 14:09:48 -0700 (PDT) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id OAA29109; Tue, 12 Jun 2001 14:08:52 -0700 (PDT) Received: from mentor.com (bob.wv.mentorg.com [147.34.70.103]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id MXC41Y7N; Tue, 12 Jun 2001 14:09:37 -0700 Sender: bobr@relay1.mentorg.com Message-ID: <3B2684E2.8073829D@mentor.com> Date: Tue, 12 Jun 2001 14:08:50 -0700 From: Bob Ross X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Adam.Tambone@fairchildsemi.com CC: ibis@eda.org Subject: Re: BIRD 68.1 References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Adam: The rising and falling V-T tables do not have to start at the same time as the input stimulus, but they have to be offset by the same amount of time. Then the buffers should simulate in an undistorted manner - provided that the pulse width is wide enough to capture the whole rising and falling waveforms. The pulse width can be reduced if a leading edge delay time removal algorithm is used to remove equal delays in both rising and falling waveform sets. Bob Ross Mentor Graphics > Adam.Tambone@fairchildsemi.com wrote: > > Hello All, > > I have question regarding BIRD 68.1. Does the BIRD state that if the > recommendations within it are followed ( i.e. if the v-t tables for rising > and falling begin at the same time as the rising and falling edges of the > input stimulus, and additional delay is introduced to account for delay not > within the buffers ) then undistorted duty cycles will be represented in > simulation? > > Thanks, > Adam Tambone From owner-ibis Tue Jun 12 16:40:41 2001 Received: from ganymede.or.intel.com (jffdns01.or.intel.com [134.134.248.3]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5CNed7n008441 for ; Tue, 12 Jun 2001 16:40:40 -0700 (PDT) Received: from SMTP (orsmsxvs02-1.jf.intel.com [192.168.65.201]) by ganymede.or.intel.com (8.9.1a+p1/8.9.1/d: relay.m4,v 1.40 2001/06/06 21:14:49 root Exp $) with SMTP id XAA28358; Tue, 12 Jun 2001 23:39:45 GMT Received: from orsmsx28.jf.intel.com ([192.168.70.28]) by 192.168.70.201 (Norton AntiVirus for Internet Email Gateways 1.0) ; Tue, 12 Jun 2001 23:39:44 0000 (GMT) Received: by orsmsx28.jf.intel.com with Internet Mail Service (5.5.2653.19) id ; Tue, 12 Jun 2001 16:39:43 -0700 Message-ID: From: "Lorang, David D" To: "'Adam.Tambone@fairchildsemi.com'" , ibis@eda.org Subject: RE: BIRD 68.1 Date: Tue, 12 Jun 2001 14:17:22 -0700 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" Hi Adam, Well, you are pretty close. The Bird clarifies IBIS in hope that--if everytning is done correctly--you will not see duty cycle distortion in simulation. Hence, as you say, the V-T tables should begin at the same time with respect to some edge stimulus inside the device you are modeling. Any difference in delay between rising a falling edges should be represented by where the actual edge occurs in the respective tables. You should not need to manually add any additional delay; the data from your transistor level simulator should do that for you if it is modeling the differences in internal delays already. If you are taking bench data on real silicon, then you will need to build the tables to show the differences in delays. Your digital scope might do that for you if you are triggering from a common clock, for example. But in addition to all of the above, the simulator you are using must also handle the waveforms correctly, in order to avoid the duty cycle distortion. Some may, others may not. It is always a good idea to run some correlation simulations to compare with the bench test data or transistor level simulator to make sure it is all working the way it should be. Best regards, David Lorang -----Original Message----- From: Adam.Tambone@fairchildsemi.com [mailto:Adam.Tambone@fairchildsemi.com] Sent: Tuesday, June 12, 2001 10:51 AM To: ibis@eda.org Subject: BIRD 68.1 Hello All, I have question regarding BIRD 68.1. Does the BIRD state that if the recommendations within it are followed ( i.e. if the v-t tables for rising and falling begin at the same time as the rising and falling edges of the input stimulus, and additional delay is introduced to account for delay not within the buffers ) then undistorted duty cycles will be represented in simulation? Thanks, Adam Tambone From owner-ibis Wed Jun 13 05:43:07 2001 Received: from topaz.3com.com (topaz.3com.com [192.156.136.158]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DCh57n011641 for ; Wed, 13 Jun 2001 05:43:07 -0700 (PDT) Received: from opal.3com.com (opal.3com.com [139.87.50.117]) by topaz.3com.com (Switch-2.1.1/Switch-2.1.0) with ESMTP id f5DCeDp26847; Wed, 13 Jun 2001 05:40:13 -0700 (PDT) Received: from hqoutbound.ops.3com.com (hqoutbound.ops.3com.com [139.87.48.104]) by opal.3com.com (Switch-2.1.1/Switch-2.1.0) with SMTP id f5DCgCI18660; Wed, 13 Jun 2001 05:42:12 -0700 (PDT) Received: by hqoutbound.ops.3com.com(Lotus SMTP MTA v4.6.7 (934.1 12-30-1999)) id 88256A6A.0045C417 ; Wed, 13 Jun 2001 05:42:01 -0700 X-Lotus-FromDomain: 3COM From: Roy_Leventhal@3com.com To: Andrew Holmes cc: ibis@eda.org Message-ID: <88256A6A.0045C394.00@hqoutbound.ops.3com.com> Date: Wed, 13 Jun 2001 07:42:22 -0500 Subject: RE: IBIS 3.2 model error Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Andy, What are you using to run checks with? Regards, Roy From owner-ibis Wed Jun 13 08:14:13 2001 Received: from mtvwca1-smrly1.gtei.net (mtvwca1-smrly1.gtei.net [128.11.176.196]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DFEC7n012102 for ; Wed, 13 Jun 2001 08:14:12 -0700 (PDT) Received: from fairchild3-cp-fc.fairchildsemi.com (smtp2-fc.fairchildsemi.com [192.233.132.91]) by mtvwca1-smrly1.gtei.net (Postfix) with SMTP id 3E0513AFB for ; Wed, 13 Jun 2001 15:13:18 +0000 (GMT) Received: FROM dnsbak.fairchildsemi.com BY hqnttest01.fairchildsemi.com ; Wed Jun 13 11:11:33 2001 -0400 Received: from notes.fairchildsemi.com (fsce16.fairchildsemi.com [172.21.18.66]) by dnsbak.fairchildsemi.com (8.9.3+Sun/8.9.3) with ESMTP id LAA06935 for ; Wed, 13 Jun 2001 11:12:35 -0400 (EDT) Subject: BIRD 68.1 To: ibis@eda.org From: Adam.Tambone@fairchildsemi.com Date: Wed, 13 Jun 2001 11:11:58 -0400 Message-ID: X-MIMETrack: Serialize by Router on SPNOTES01/Corporate/FSC(Release 5.0.6a |January 17, 2001) at 06/13/2001 11:12:00 AM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii Bob and David, Thank you both for your responses. They have led me to more questions, please excuse their simplicity. Bob, I am not clear about your statement, "they have to be offset by the same amount of time". Can you provide more description? David, The netlists we use in S2I translation include only the buffers ( we are currently considering using netlists that include full data paths instead ) and so my question is, should additional delay be added to the rising and falling waveforms to account for the delay through circuitry not included in these netlists? Another question. Since the rising and falling edges represented in the rising and falling waveforms were gained with an input stimulus with a specific trise and tfall, is it necessary for the simulations to be run with the same trise and tfall on the input stimulus? In other words, if simulations are run with an input stimulus that has different trise and tfall then that of the input stimulus used to produce the rising and falling waveforms will not the edge rates in simulation be invalid? Thank You Again, Adam Tambone Adam: The rising and falling V-T tables do not have to start at the same time as the input stimulus, but they have to be offset by the same amount of time. Then the buffers should simulate in an undistorted manner - provided that the pulse width is wide enough to capture the whole rising and falling waveforms. The pulse width can be reduced if a leading edge delay time removal algorithm is used to remove equal delays in both rising and falling waveform sets. Bob Ross Mentor Graphics Hi Adam, Well, you are pretty close. The Bird clarifies IBIS in hope that--if everytning is done correctly--you will not see duty cycle distortion in simulation. Hence, as you say, the V-T tables should begin at the same time with respect to some edge stimulus inside the device you are modeling. Any difference in delay between rising a falling edges should be represented by where the actual edge occurs in the respective tables. You should not need to manually add any additional delay; the data from your transistor level simulator should do that for you if it is modeling the differences in internal delays already. If you are taking bench data on real silicon, then you will need to build the tables to show the differences in delays. Your digital scope might do that for you if you are triggering from a common clock, for example. But in addition to all of the above, the simulator you are using must also handle the waveforms correctly, in order to avoid the duty cycle distortion. Some may, others may not. It is always a good idea to run some correlation simulations to compare with the bench test data or transistor level simulator to make sure it is all working the way it should be. Best regards, David Lorang > Adam.Tambone@fairchildsemi.com wrote: > > Hello All, > > I have question regarding BIRD 68.1. Does the BIRD state that if the > recommendations within it are followed ( i.e. if the v-t tables for rising > and falling begin at the same time as the rising and falling edges of the > input stimulus, and additional delay is introduced to account for delay not > within the buffers ) then undistorted duty cycles will be represented in > simulation? > > Thanks, > Adam Tambone From owner-ibis Wed Jun 13 09:24:42 2001 Received: from mtvwca1-smrly1.gtei.net (mtvwca1-smrly1.gtei.net [128.11.176.196]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DGOe7n012278 for ; Wed, 13 Jun 2001 09:24:41 -0700 (PDT) Received: from fairchild-cp-fc.fairchildsemi.com (smtp1-fc.fairchildsemi.com [192.233.132.90]) by mtvwca1-smrly1.gtei.net (Postfix) with SMTP id 2EEF34C98 for ; Wed, 13 Jun 2001 16:23:47 +0000 (GMT) Received: FROM dnsbak.fairchildsemi.com BY hqnttest01.fairchildsemi.com ; Wed Jun 13 12:22:01 2001 -0400 Received: from notes.fairchildsemi.com (fsce16.fairchildsemi.com [172.21.18.66]) by dnsbak.fairchildsemi.com (8.9.3+Sun/8.9.3) with ESMTP id MAA15373 for ; Wed, 13 Jun 2001 12:23:02 -0400 (EDT) Subject: Re: BIRD 68.1 To: ibis@eda.org From: Adam.Tambone@fairchildsemi.com Date: Wed, 13 Jun 2001 12:22:26 -0400 Message-ID: X-MIMETrack: Serialize by Router on SPNOTES01/Corporate/FSC(Release 5.0.6a |January 17, 2001) at 06/13/2001 12:22:27 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii I want to clarify that when I said 'simulations' I meant simulations using IBIS models. Adam Adam Tambone/SouthPortland/Fairchild@Fairchild on 06/13/2001 11:11:58 AM To: ibis@eda.org cc: Subject: BIRD 68.1 Bob and David, Thank you both for your responses. They have led me to more questions, please excuse their simplicity. Bob, I am not clear about your statement, "they have to be offset by the same amount of time". Can you provide more description? David, The netlists we use in S2I translation include only the buffers ( we are currently considering using netlists that include full data paths instead ) and so my question is, should additional delay be added to the rising and falling waveforms to account for the delay through circuitry not included in these netlists? Another question. Since the rising and falling edges represented in the rising and falling waveforms were gained with an input stimulus with a specific trise and tfall, is it necessary for the simulations to be run with the same trise and tfall on the input stimulus? In other words, if simulations are run with an input stimulus that has different trise and tfall then that of the input stimulus used to produce the rising and falling waveforms will not the edge rates in simulation be invalid? Thank You Again, Adam Tambone Adam: The rising and falling V-T tables do not have to start at the same time as the input stimulus, but they have to be offset by the same amount of time. Then the buffers should simulate in an undistorted manner - provided that the pulse width is wide enough to capture the whole rising and falling waveforms. The pulse width can be reduced if a leading edge delay time removal algorithm is used to remove equal delays in both rising and falling waveform sets. Bob Ross Mentor Graphics Hi Adam, Well, you are pretty close. The Bird clarifies IBIS in hope that--if everytning is done correctly--you will not see duty cycle distortion in simulation. Hence, as you say, the V-T tables should begin at the same time with respect to some edge stimulus inside the device you are modeling. Any difference in delay between rising a falling edges should be represented by where the actual edge occurs in the respective tables. You should not need to manually add any additional delay; the data from your transistor level simulator should do that for you if it is modeling the differences in internal delays already. If you are taking bench data on real silicon, then you will need to build the tables to show the differences in delays. Your digital scope might do that for you if you are triggering from a common clock, for example. But in addition to all of the above, the simulator you are using must also handle the waveforms correctly, in order to avoid the duty cycle distortion. Some may, others may not. It is always a good idea to run some correlation simulations to compare with the bench test data or transistor level simulator to make sure it is all working the way it should be. Best regards, David Lorang > Adam.Tambone@fairchildsemi.com wrote: > > Hello All, > > I have question regarding BIRD 68.1. Does the BIRD state that if the > recommendations within it are followed ( i.e. if the v-t tables for rising > and falling begin at the same time as the rising and falling edges of the > input stimulus, and additional delay is introduced to account for delay not > within the buffers ) then undistorted duty cycles will be represented in > simulation? > > Thanks, > Adam Tambone From owner-ibis Wed Jun 13 12:18:32 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DJIU7n012815 for ; Wed, 13 Jun 2001 12:18:31 -0700 (PDT) Received: from [147.34.96.11] (svr-orw-exc-02.wv.mentorg.com) by relay1.wv.mentorg.com (8.8.8/CF5.40F) id MAA09788; Wed, 13 Jun 2001 12:16:49 -0700 (PDT) Received: from mentor.com (bob.wv.mentorg.com [147.34.70.103]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id MXC416DZ; Wed, 13 Jun 2001 12:17:34 -0700 Sender: bobr@relay1.mentorg.com Message-ID: <3B27BC20.5638D6C5@mentor.com> Date: Wed, 13 Jun 2001 12:16:48 -0700 From: Bob Ross X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Adam.Tambone@fairchildsemi.com CC: ibis@eda.org Subject: Re: BIRD 68.1 References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Adam: Some responses are in your text. Bob Ross Mentor Graphics > Adam.Tambone@fairchildsemi.com wrote: > > Bob and David, > > Thank you both for your responses. They have led me to more questions, > please excuse their simplicity. > > Bob, I am not clear about your statement, "they have to be offset by the > same amount of time". > > Can you provide more description? > I actually met that the captured waveforms must be delayed relative to the same reference input or clock. Suppose the rising waveform and falling waveforms are both exact 1 ns ramps into the same test load, which also happens to be the actual load. However, both of these ramps start at 1 ns after the clock edge. So the actual waveforms that are stored in the IBIS model cover 2 ns. The maximum pulse width and clock frequency are 2 ns and 250 MHz without causing distorted simulation results. However the real device can operate at a higher frequency. The model developer might choose to truncate the leading edge delay. An equal amount of delay should be removed from both the rising and falling waveform tables. (The EDA tool may also do this.) Then the pulse width and clock frequency can be set to 1 ns and 500 MHz without distortion. > David, The netlists we use in S2I translation include only the buffers ( > we are currently considering using netlists that include full data paths > instead ) and so my question is, should additional delay be added to the > rising and falling waveforms to account for the delay through circuitry not > included in these netlists? > > Another question. > > Since the rising and falling edges represented in the rising and falling > waveforms were gained with an input stimulus with a specific trise and > tfall, is it necessary for the simulations to be run with the same trise > and tfall on the input stimulus? In other words, if simulations are run > with an input stimulus that has different trise and tfall then that of the > input stimulus used to produce the rising and falling waveforms will not > the edge rates in simulation be invalid? > I would recommend the same trise and tfall for input stimulus. Using an input that corresponds to an actual input is probably a good strategy. The effect of using a different edge rate is probably to change the simulation delay. > Thank You Again, > Adam Tambone > > Adam: > > The rising and falling V-T tables do not have to > start at the same time as the input stimulus, but > they have to be offset by the same amount of time. > > Then the buffers should simulate in an undistorted > manner - provided that the pulse width is wide > enough to capture the whole rising and falling > waveforms. The pulse width can be reduced if > a leading edge delay time removal algorithm is > used to remove equal delays in both rising and > falling waveform sets. > > Bob Ross > Mentor Graphics > > Hi Adam, > > Well, you are pretty close. The Bird clarifies IBIS in hope that--if > everytning is done correctly--you will not see duty cycle distortion in > simulation. Hence, as you say, the V-T tables should begin at the same > time > with respect to some edge stimulus inside the device you are modeling. Any > difference in delay between rising a falling edges should be represented by > where the actual edge occurs in the respective tables. You should not need > to manually add any additional delay; the data from your transistor level > simulator should do that for you if it is modeling the differences in > internal delays already. > > If you are taking bench data on real silicon, then you will need to build > the tables to show the differences in delays. Your digital scope might do > that for you if you are triggering from a common clock, for example. > > But in addition to all of the above, the simulator you are using must also > handle the waveforms correctly, in order to avoid the duty cycle > distortion. > Some may, others may not. It is always a good idea to run some correlation > simulations to compare with the bench test data or transistor level > simulator to make sure it is all working the way it should be. > > Best regards, > David Lorang > > > Adam.Tambone@fairchildsemi.com wrote: > > > > Hello All, > > > > I have question regarding BIRD 68.1. Does the BIRD state that if the > > recommendations within it are followed ( i.e. if the v-t tables for > rising > > and falling begin at the same time as the rising and falling edges of > the > > input stimulus, and additional delay is introduced to account for delay > not > > within the buffers ) then undistorted duty cycles will be represented in > > simulation? > > > > Thanks, > > Adam Tambone From owner-ibis Wed Jun 13 12:31:01 2001 Received: from camcolo2-smrly1.gtei.net (camcolo2-smrly1.gtei.net [128.11.173.4]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DJUv7n012850 for ; Wed, 13 Jun 2001 12:31:00 -0700 (PDT) Received: from fairchild3-cp-fc.fairchildsemi.com (smtp2-fc.fairchildsemi.com [192.233.132.91]) by camcolo2-smrly1.gtei.net (Postfix) with SMTP id 879E73C6D for ; Wed, 13 Jun 2001 19:30:03 +0000 (GMT) Received: FROM dnsbak.fairchildsemi.com BY hqnttest01.fairchildsemi.com ; Wed Jun 13 15:28:17 2001 -0400 Received: from notes.fairchildsemi.com (fsce16.fairchildsemi.com [172.21.18.66]) by dnsbak.fairchildsemi.com (8.9.3+Sun/8.9.3) with ESMTP id PAA06099; Wed, 13 Jun 2001 15:29:19 -0400 (EDT) Subject: Re: BIRD 68.1 To: Bob Ross Cc: ibis@eda.org From: Adam.Tambone@fairchildsemi.com Date: Wed, 13 Jun 2001 15:28:42 -0400 Message-ID: X-MIMETrack: Serialize by Router on SPNOTES01/Corporate/FSC(Release 5.0.6a |January 17, 2001) at 06/13/2001 03:28:43 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii Bob, Thank you again for your response, it is very clear. Another question. If the user should simulate with the IBIS model using an input stimulus with the same trise and tfall as was used with the input stimulus in S2I translation, how does the user know what this is as it is not a parameter included in the IBIS datasheet? I assume the user should refer to the vendor's datasheet for input tr and tf, but that is assuming the IBIS datasheet generator used the same tr and tf. Should input tr and tf be parameters included in an IBIS datasheet? Respectfully, Adam Tambone Bob Ross @relay1.mentorg.com on 06/13/2001 03:16:48 PM Sent by: bobr@relay1.mentorg.com To: Adam Tambone/SouthPortland/Fairchild@Fairchild cc: ibis@eda.org Subject: Re: BIRD 68.1 Adam: Some responses are in your text. Bob Ross Mentor Graphics > Adam.Tambone@fairchildsemi.com wrote: > > Bob and David, > > Thank you both for your responses. They have led me to more questions, > please excuse their simplicity. > > Bob, I am not clear about your statement, "they have to be offset by the > same amount of time". > > Can you provide more description? > I actually met that the captured waveforms must be delayed relative to the same reference input or clock. Suppose the rising waveform and falling waveforms are both exact 1 ns ramps into the same test load, which also happens to be the actual load. However, both of these ramps start at 1 ns after the clock edge. So the actual waveforms that are stored in the IBIS model cover 2 ns. The maximum pulse width and clock frequency are 2 ns and 250 MHz without causing distorted simulation results. However the real device can operate at a higher frequency. The model developer might choose to truncate the leading edge delay. An equal amount of delay should be removed from both the rising and falling waveform tables. (The EDA tool may also do this.) Then the pulse width and clock frequency can be set to 1 ns and 500 MHz without distortion. > David, The netlists we use in S2I translation include only the buffers ( > we are currently considering using netlists that include full data paths > instead ) and so my question is, should additional delay be added to the > rising and falling waveforms to account for the delay through circuitry not > included in these netlists? > > Another question. > > Since the rising and falling edges represented in the rising and falling > waveforms were gained with an input stimulus with a specific trise and > tfall, is it necessary for the simulations to be run with the same trise > and tfall on the input stimulus? In other words, if simulations are run > with an input stimulus that has different trise and tfall then that of the > input stimulus used to produce the rising and falling waveforms will not > the edge rates in simulation be invalid? > I would recommend the same trise and tfall for input stimulus. Using an input that corresponds to an actual input is probably a good strategy. The effect of using a different edge rate is probably to change the simulation delay. > Thank You Again, > Adam Tambone > > Adam: > > The rising and falling V-T tables do not have to > start at the same time as the input stimulus, but > they have to be offset by the same amount of time. > > Then the buffers should simulate in an undistorted > manner - provided that the pulse width is wide > enough to capture the whole rising and falling > waveforms. The pulse width can be reduced if > a leading edge delay time removal algorithm is > used to remove equal delays in both rising and > falling waveform sets. > > Bob Ross > Mentor Graphics > > Hi Adam, > > Well, you are pretty close. The Bird clarifies IBIS in hope that--if > everytning is done correctly--you will not see duty cycle distortion in > simulation. Hence, as you say, the V-T tables should begin at the same > time > with respect to some edge stimulus inside the device you are modeling. Any > difference in delay between rising a falling edges should be represented by > where the actual edge occurs in the respective tables. You should not need > to manually add any additional delay; the data from your transistor level > simulator should do that for you if it is modeling the differences in > internal delays already. > > If you are taking bench data on real silicon, then you will need to build > the tables to show the differences in delays. Your digital scope might do > that for you if you are triggering from a common clock, for example. > > But in addition to all of the above, the simulator you are using must also > handle the waveforms correctly, in order to avoid the duty cycle > distortion. > Some may, others may not. It is always a good idea to run some correlation > simulations to compare with the bench test data or transistor level > simulator to make sure it is all working the way it should be. > > Best regards, > David Lorang > > > Adam.Tambone@fairchildsemi.com wrote: > > > > Hello All, > > > > I have question regarding BIRD 68.1. Does the BIRD state that if the > > recommendations within it are followed ( i.e. if the v-t tables for > rising > > and falling begin at the same time as the rising and falling edges of > the > > input stimulus, and additional delay is introduced to account for delay > not > > within the buffers ) then undistorted duty cycles will be represented in > > simulation? > > > > Thanks, > > Adam Tambone From owner-ibis Wed Jun 13 13:21:58 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DKLv7n013010 for ; Wed, 13 Jun 2001 13:21:58 -0700 (PDT) Received: from [147.34.96.11] (svr-orw-exc-02.wv.mentorg.com) by relay1.wv.mentorg.com (8.8.8/CF5.40F) id NAA23203; Wed, 13 Jun 2001 13:21:02 -0700 (PDT) Received: from mentor.com (bob.wv.mentorg.com [147.34.70.103]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id MXC416J7; Wed, 13 Jun 2001 13:21:47 -0700 Sender: bobr@relay1.mentorg.com Message-ID: <3B27CB2C.12032BE6@mentor.com> Date: Wed, 13 Jun 2001 13:21:01 -0700 From: Bob Ross X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Adam.Tambone@fairchildsemi.com CC: ibis@eda.org Subject: Re: BIRD 68.1 References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Adam: As long as the rising and falling waveforms are reasonable for the area of operation, you probably do not need the tr and tf information. However, you could document it as a Note or comment. The EDA tool probably would not use the information. Bob Ross Mentor Graphics > Adam.Tambone@fairchildsemi.com wrote: > > Bob, > > Thank you again for your response, it is very clear. > > Another question. > > If the user should simulate with the IBIS model using an input stimulus > with the same trise and tfall as was used with the input stimulus in S2I > translation, how does the user know what this is as it is not a parameter > included in the IBIS datasheet? I assume the user should refer to the > vendor's datasheet for input tr and tf, but that is assuming the IBIS > datasheet generator used the same tr and tf. Should input tr and tf be > parameters included in an IBIS datasheet? > > Respectfully, > Adam Tambone > From owner-ibis Wed Jun 13 16:32:41 2001 Received: from hebe.or.intel.com (jffdns02.or.intel.com [134.134.248.4]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5DNWc7n013399 for ; Wed, 13 Jun 2001 16:32:40 -0700 (PDT) Received: from SMTP (orsmsxvs01-1.jf.intel.com [192.168.65.200]) by hebe.or.intel.com (8.9.1a+p1/8.9.1/d: relay.m4,v 1.40 2001/06/06 21:14:49 root Exp $) with SMTP id XAA21070; Wed, 13 Jun 2001 23:31:43 GMT Received: from orsmsx29.jf.intel.com ([192.168.70.29]) by 192.168.70.200 (Norton AntiVirus for Internet Email Gateways 1.0) ; Wed, 13 Jun 2001 23:31:43 0000 (GMT) Received: by orsmsx29.jf.intel.com with Internet Mail Service (5.5.2653.19) id ; Wed, 13 Jun 2001 16:31:41 -0700 Message-ID: From: "Lorang, David D" To: "'Adam.Tambone@fairchildsemi.com'" , ibis@eda.org Subject: RE: BIRD 68.1 Date: Wed, 13 Jun 2001 14:40:51 -0700 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="ISO-8859-1" Adam, You wrote: >David, The netlists we use in S2I translation include only the buffers ( >we are currently considering using netlists that include full data paths >instead ) and so my question is, should additional delay be added to the >rising and falling waveforms to account for the delay through circuitry not >included in these netlists? Possibly, but not necessarily. It depends on how well you want to model the duty cycle distortion in your actual design. You can choose to simulate a certain signal all the way from the input pins of your IC, depending on what internal timing differences for that signal that you want to capture. In general, IBIS tries to specify only the edges, but not their timings. But in the case of an individual signal, if you are conserned about--and want to model--duty cycle distortion, you need to maintain some timing information. That timing information can be carried in the assumption the start of each edge table as a common point of reference. So the number of nanoseconds into the tables where the rising and falling edges occur relative to each other should match up with where the edges occur relative to each other in the silicon (or the transistor level simulation of the silicon if that is what you are correlating to.) Dave Lorang From owner-ibis Thu Jun 14 11:57:10 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5EIv87n016997; Thu, 14 Jun 2001 11:57:09 -0700 (PDT) Received: from svr-orw-exc-02.wv.mentorg.com ([147.34.96.11]) by relay1.wv.mentorg.com (8.8.8/CF5.40F) id LAA12291; Thu, 14 Jun 2001 11:56:13 -0700 (PDT) Received: from mentor.com (bob.wv.mentorg.com [147.34.70.103]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id M7GSLRTC; Thu, 14 Jun 2001 11:57:00 -0700 Sender: bobr@relay1.mentorg.com Message-ID: <3B2908CC.3813248D@mentor.com> Date: Thu, 14 Jun 2001 11:56:12 -0700 From: Bob Ross X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: ibis@eda.org, ibis-users@eda.org CC: "Ross, Bob" , gdeburgh@innoveda.com Subject: IBIS Summit Meeting Agenda 6/21/01 Content-Type: multipart/mixed; boundary="------------8A96D7F1443FEFBE3FF401D3" This is a multi-part message in MIME format. --------------8A96D7F1443FEFBE3FF401D3 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit To All: Below is the planned agenda for the IBIS Summit Meeting to be held on Thursday June 21, 2000 during the Design Automation Conference in Las Vegas, Nevada. The meeting consists of presentations and discussions. The meeting is free to people interested in IBIS modeling, digital circuit design and related EDA tool development. Refreshments and lunch are included. If you plan to attend, please contact Bob Ross or Guy de Burgh at the addresses below (if you haven't already done so): Bob Ross Mentor Graphics Chair, EIA IBIS Open Forum bob_ross@mentor.com Guy de Burgh Innoveda Secretary, EIA IBIS Open Forum gdeburgh@innoveda.com --------------8A96D7F1443FEFBE3FF401D3 Content-Type: text/plain; charset=us-ascii; name="agenda.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="agenda.txt" ________________________________________________________________________ AGENDA, IBIS SUMMIT MEETING June 21, 2001 Las Vegas Hilton Regency Hotel Las Vegas, Nevada 8:30 AM REFRESHMENTS AND SIGN-IN 9:00 AM INTRODUCTIONS 9:10 AM IBIS STATUS Bob Ross, Mentor Graphics 9:30 AM PRE-EMPHSIS BUFFER MODELING Hazem Hegazy, Fady Galal, and Roshdy Hegazy, Mentor Graphics 10:00 AM SCSI, FIBER CHANNEL IBIS MODELING OVERVIEW Larry Barnes, LSI Logic 10:30 AM BREAK 10:45 AM DRIVER SCHEDULE MODELING Chris Reid and Bob Ross, Mentor Graphics 11:05 AM MAKING BEHAVIORAL MODELS FOR FREQUENCY DOMAIN ANALYSIS Arpad Muranyi, Intel 11:35 AM ELECTION OF OFFICERS AND OTHER BUSINESS 12:00 PM LUNCH (Provided to Attendees) 1:00 PM IBIS-X and IBIS MACRO LANGUAGE PROGRESS Stephen Peters, Intel IBIS-X AND IBIS-ML Stephen Peters, Intel APPLYING THE IBIS MACRO LANGUAGE TO NEW KEYWORDS Al Davis, Independent 3:00 PM BREAK 3:15 PM EMC PARAMETERS FOR IBIS Guy de Burgh, Innoveda 3:45 PM OPEN DISCUSSION AND AD HOC PRESENTATIONS - Next Meetings - Etc. 5:00 PM MEETING ENDS ________________________________________________________________________ --------------8A96D7F1443FEFBE3FF401D3-- From owner-ibis Tue Jun 19 10:00:15 2001 Received: from mailhost.conwin.com (mailhost.conwin.com [12.24.19.233]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5JH0D7n005370 for ; Tue, 19 Jun 2001 10:00:14 -0700 (PDT) Received: from vamseedhark.conwin.com (floyd.conwin.com [12.24.19.234]) by mailhost.conwin.com (8.9.3/8.9.3) with ESMTP id LAA22421 for ; Tue, 19 Jun 2001 11:59:23 -0500 Message-Id: <5.1.0.14.2.20010619115346.00a4dda0@mail.conwin.com> X-Sender: vkalam@mail.conwin.com X-Mailer: QUALCOMM Windows Eudora Version 5.1 Date: Tue, 19 Jun 2001 12:01:54 -0500 To: ibis@eda.org From: Vamseedhar Kalam Subject: Seeking your help Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; format=flowed Hi, My name is Vamseedhar Kalam and i am presently working as an intern in Connor Winfield Corporation. My work is on the ibis modeling of the outputs (LVPECL and LVTTL12S) for SCG6500 using virtex2 as the component. I am facing a problem as i am not having sufficient data available for C_comp , temperature range, voltage range, current( min and max values), dv/dt _r and dv/dt_f (min and max values), voltages (min and max values) in the case of LVPECL and C_comp(min value), temperature range (min value), voltage range(min value), current (min value), dv/dt_r, dv/dt_f (min values) and voltage(min) in the case LVTTL12S. I would be really thankful to you if you could let me know if there is a means by which I could derive the data . Also, tell me if this approach is right or wrong? Thanks, Regards, Vamseedhar Kalam From owner-ibis Tue Jun 19 13:06:58 2001 Received: from ip210.c246.blk1.bel.nwlink.com (ip210.c246.blk1.bel.nwlink.com [209.20.246.210]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with SMTP id f5JK6s7n005811; Tue, 19 Jun 2001 13:06:56 -0700 (PDT) Received: from no.name.available by ip210.c246.blk1.bel.nwlink.com via smtpd (for server.eda.ORG [171.64.101.101]) with SMTP; 19 Jun 2001 20:06:01 UT Received: from hlgw.hyperlynx.com (hlgw.hyperlynx.com [192.168.149.1]) by mail.hyperlynx.com (8.9.3/8.9.3/SuSE Linux 8.9.3-0.1) with SMTP id NAA27803; Tue, 19 Jun 2001 13:05:59 -0700 Message-ID: <053501c0f8fb$868bea10$8ecab58b@Kaluga> From: "John Angulo" To: , Received: from no.name.available by hlgw.hyperlynx.com via smtpd (for [192.168.149.2]) with SMTP; 19 Jun 2001 20:05:59 UT References: <7FD5C79AD680D211AC4100A0C96B501C084A781A@orsmsx49.jf.intel.com> Subject: Reminder: send subscription requests to ibis-request@eda.org Date: Tue, 19 Jun 2001 13:07:54 -0700 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Hello, Lately, some requests to subscribe or unsubscribe from IBIS reflectors have been posted to ibis-users@eda.org. For such requests, please use this dedicated address instead: ibis-request@eda.org This prevents unnecessary administrative traffic on the reflectors. Thanks, John Angulo IBIS Open Forum Postmaster From owner-ibis Tue Jun 19 17:07:05 2001 Received: from rumor.cps.intel.com (rumor.cps.intel.com [192.102.198.242]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5K0727n006481; Tue, 19 Jun 2001 17:07:03 -0700 (PDT) Received: from SMTP (fmsmsxvs05-1.fm.intel.com [132.233.42.205]) by rumor.cps.intel.com (8.9.1a+p1/8.9.1/d: relay.m4,v 1.40 2001/06/06 21:14:49 root Exp $) with SMTP id AAA28728; Wed, 20 Jun 2001 00:06:00 GMT Received: from fmsmsx28.fm.intel.com ([132.233.48.28]) by 132.233.48.205 (Norton AntiVirus for Internet Email Gateways 1.0) ; Wed, 20 Jun 2001 00:06:02 0000 (GMT) Received: by fmsmsx28.fm.intel.com with Internet Mail Service (5.5.2653.19) id ; Tue, 19 Jun 2001 17:06:01 -0700 Message-ID: <7FD5C79AD680D211AC4100A0C96B501C084A7824@orsmsx49.jf.intel.com> From: "Peters, Stephen" To: "'ibis@eda.org'" , "'ibis-users@eda.org'" Subject: IBIS-X spec rev 0.6 now available Date: Tue, 19 Jun 2001 17:05:52 -0700 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" Greetings: An updated copy of the IBIS-X specification is now available on the IBIS web site. http://www.eda.org/pub/ibis/futures/ This revision (rev 0.6a) has been updated (from rev 5.0) as follows: -- Added description of "class name" selector ([Model Selector] keyword) and updated keyword tree -- Moved revision history to just after the TOC and renumbered sections -- Corrected argument and description of [End] keyword. -- Editorial/typo corrections, including replacing occurrences of "CAE" with "EDA" The IBIS-X document will be discussed and reviewed at Thursday's IBIS Open Forum meeting at DAC in Las Vegas. Note that if you are planning on attending the summit, only a limited number of copies will be available at the meeting, so download a copy to take with you. In addition to the IBIS-X specification, the working draft version of the IBIS-ML Language Reference Manual (LRM) is available for download. Note that only sections 7 and 8 of the LRM have been reviewed by the IBIS futures working group, and the document has a number of editorial and format issues. In other words, this document is very much a work in progress, and is being made available only to aid the IBIS-X discussion. A much more complete version of the LRM will be available after the summit. I'd also like to take this opportunity to extend a public thank you to the members of the IBIS futures group for their hard work in making the IBIS-X spec a reality. Great job, folks! Best Regards, Stephen Peters Intel Corp. Chair, IBIS Futures Working Group From owner-ibis Thu Jun 21 04:59:19 2001 Received: from md5.vsnl.net.in (md5.vsnl.net.in [202.54.6.50]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5LBxF7n011871 for ; Thu, 21 Jun 2001 04:59:16 -0700 (PDT) Received: from et-t (unknown [61.1.242.226]) by md5.vsnl.net.in (Postfix) with SMTP id A5D1122B00 for ; Thu, 21 Jun 2001 17:27:26 +0530 (IST) From: Hahaha Subject: Snowhite and the Seven Dwarfs - The REAL story! MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="--VEQ7SHYB0HUV0X" Message-Id: <20010621115726.A5D1122B00@md5.vsnl.net.in> Date: Thu, 21 Jun 2001 17:27:26 +0530 (IST) To: undisclosed-recipients:; ----VEQ7SHYB0HUV0X Content-Type: text/plain; charset="us-ascii" Today, Snowhite was turning 18. The 7 Dwarfs always where very educated and polite with Snowhite. When they go out work at mornign, they promissed a *huge* surprise. Snowhite was anxious. Suddlently, the door open, and the Seven Dwarfs enter... ----VEQ7SHYB0HUV0X Content-Type: application/octet-stream; name="sexy virgin.scr" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="sexy virgin.scr" VIRUS DELETED ----VEQ7SHYB0HUV0X-- From owner-ibis Thu Jun 21 10:10:24 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5LHAL7n012865 for ; Thu, 21 Jun 2001 10:10:23 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id NAA14493 for ; Thu, 21 Jun 2001 13:09:23 -0400 (EDT) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id NAA21080 for ; Thu, 21 Jun 2001 13:09:22 -0400 (EDT) Received: from pcjpowell ([139.181.195.135]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id KAA24266 for ; Thu, 21 Jun 2001 10:09:19 -0700 (PDT) From: "Jon Powell" To: Subject: Virus Alert Date: Thu, 21 Jun 2001 10:07:57 -0700 Message-ID: <001101c0fa74$b88f18f0$87c3b58b@pcjpowell> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook CWS, Build 9.0.2416 (9.0.2910.0) X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Importance: Normal Someone is sending the "SNOW WHITE" virus out. Don't read any mail with anything about SNOW WHITE in the header. Anyone who has should get off the net and virus scan their computer. This is an OLD ONE. jon From owner-ibis Thu Jun 21 10:46:28 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5LHkQ7n012942 for ; Thu, 21 Jun 2001 10:46:27 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id NAA15584 for ; Thu, 21 Jun 2001 13:45:28 -0400 (EDT) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id NAA22136 for ; Thu, 21 Jun 2001 13:45:27 -0400 (EDT) Received: from pcchrisr (pc-chrisr.camarillo.innoveda.com [139.181.194.170]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id KAA25352 for ; Thu, 21 Jun 2001 10:45:24 -0700 (PDT) From: "Chris Rokusek" To: "Ibis@Eda. Org" Subject: Junk mail? Date: Thu, 21 Jun 2001 10:48:08 -0700 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.2416 (9.0.2910.0) X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Importance: Normal In-Reply-To: Hi All, I've just recently received a few spam messages at my work address which to my knowledge is only known by the IBIS and SI-LIST reflectors. I am concerned over the list's security. Can 3rd parties harvest our email addresses or post messages to the list without being members? I've received four or five messages over the last week, some which appear to be "sonar pings." The latest two spam messages that I received had subject: Your Reg #AD6 - received 6/18 Snow White - received 6/21 The Snow White (is supposedly a virus) definitely came from ibis@eda.org but the first one could have come from elsewhere. If others on the list are receiving these besides me we should act quickly to plug the leak before we get the to state where 50% of email per day is spam (trust me, it happens quickly!). Chris Rokusek Innoveda From owner-ibis Thu Jun 21 14:31:12 2001 Received: from topaz.3com.com (topaz.3com.com [192.156.136.158]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5LLVA7n013620 for ; Thu, 21 Jun 2001 14:31:11 -0700 (PDT) Received: from opal.3com.com (opal.3com.com [139.87.50.117]) by topaz.3com.com (Switch-2.1.1/Switch-2.1.0) with ESMTP id f5LKs8601538; Thu, 21 Jun 2001 13:54:08 -0700 (PDT) Received: from hqoutbound.ops.3com.com (hqoutbound.ops.3com.com [139.87.48.104]) by opal.3com.com (Switch-2.1.1/Switch-2.1.0) with SMTP id f5LKu8I17583; Thu, 21 Jun 2001 13:56:08 -0700 (PDT) Received: by hqoutbound.ops.3com.com(Lotus SMTP MTA v4.6.7 (934.1 12-30-1999)) id 88256A72.0072FB1A ; Thu, 21 Jun 2001 13:55:53 -0700 X-Lotus-FromDomain: 3COM From: Roy_Leventhal@3com.com To: "Chris Rokusek" cc: "Ibis@Eda. Org" Message-ID: <88256A72.0072F93C.00@hqoutbound.ops.3com.com> Date: Thu, 21 Jun 2001 15:56:13 -0500 Subject: Re: Junk mail? Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Yeh, I got Snow White too. But, I immediately deleted it and was OK. Regards, Roy From owner-ibis Thu Jun 21 15:58:08 2001 Received: from InterJet.apsimtech.com (adsl-66-121-137-98.dsl.snfc21.pacbell.net [66.121.137.98]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5LMw67n013756 for ; Thu, 21 Jun 2001 15:58:07 -0700 (PDT) Received: (from daemon@localhost) by InterJet.apsimtech.com (8.8.5/8.8.5) id QAA21509; Thu, 21 Jun 2001 16:04:53 -0700 (PDT) Received: from apsim3.apsimtech.com(192.168.1.103), claiming to be "apsimtech.com" via SMTP by InterJet.apsimtech.com, id smtpd021507; Thu Jun 21 23:04:51 2001 Sender: fred@apsimtech.com Message-ID: <3B327ADE.16ECFF68@apsimtech.com> Date: Thu, 21 Jun 2001 15:53:18 -0700 From: Fred Balistreri Organization: Apsim X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.6 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: Chris Rokusek CC: "Ibis@Eda. Org" Subject: Re: Junk mail? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I also got these and belong to the same two reflectors. Best Regards, Chris Rokusek wrote: > > Hi All, > > I've just recently received a few spam messages at my work address which to > my knowledge is only known by the IBIS and SI-LIST reflectors. I am > concerned over the list's security. Can 3rd parties harvest our email > addresses or post messages to the list without being members? > > I've received four or five messages over the last week, some which appear to > be "sonar pings." > > The latest two spam messages that I received had subject: > > Your Reg #AD6 - received 6/18 > Snow White - received 6/21 > > The Snow White (is supposedly a virus) definitely came from ibis@eda.org but > the first one could have come from elsewhere. > > If others on the list are receiving these besides me we should act quickly > to plug the leak before we get the to state where 50% of email per day is > spam (trust me, it happens quickly!). > > Chris Rokusek > Innoveda -- Fred Balistreri fred@apsimtech.com http://www.apsimtech.com From owner-ibis Fri Jun 22 04:40:18 2001 Received: from hadar.amcc.com ([192.195.69.168]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5MBeG7n015601 for ; Fri, 22 Jun 2001 04:40:18 -0700 (PDT) Received: from mailhost (mailhost.amcc.com [192.195.69.30]) by hadar.amcc.com (Netscape Messaging Server 4.15) with SMTP id GFBXJK01.P1L for ; Fri, 22 Jun 2001 04:35:44 -0700 Received: from amcc.com ([10.102.9.202]) by mailhost (NAVIEG 2.1 bld 63) with SMTP id M2001062204392108312 ; Fri, 22 Jun 2001 04:39:21 -0700 Message-ID: <3B332E5B.29BEE153@amcc.com> Date: Fri, 22 Jun 2001 07:39:07 -0400 From: Peter LaFlamme X-Mailer: Mozilla 4.7 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 To: Fred Balistreri CC: Chris Rokusek , "Ibis@Eda. Org" Subject: Re: Junk mail? References: <3B327ADE.16ECFF68@apsimtech.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit ditto to that. Fred Balistreri wrote: > > I also got these and belong to the same two reflectors. > > Best Regards, > > Chris Rokusek wrote: > > > > Hi All, > > > > I've just recently received a few spam messages at my work address which to > > my knowledge is only known by the IBIS and SI-LIST reflectors. I am > > concerned over the list's security. Can 3rd parties harvest our email > > addresses or post messages to the list without being members? > > > > I've received four or five messages over the last week, some which appear to > > be "sonar pings." > > > > The latest two spam messages that I received had subject: > > > > Your Reg #AD6 - received 6/18 > > Snow White - received 6/21 > > > > The Snow White (is supposedly a virus) definitely came from ibis@eda.org but > > the first one could have come from elsewhere. > > > > If others on the list are receiving these besides me we should act quickly > > to plug the leak before we get the to state where 50% of email per day is > > spam (trust me, it happens quickly!). > > > > Chris Rokusek > > Innoveda > > -- > Fred Balistreri > fred@apsimtech.com > > http://www.apsimtech.com -- Peter LaFlamme Applied Micro Circuits Corp. Staff System Applications Engineer 200 Minuteman Rd, 3rd Floor Andover, MA 01810 978-247-8470 phone 978-623-0055 Fax From owner-ibis Fri Jun 22 12:22:40 2001 Received: from hebe.or.intel.com (jffdns02.or.intel.com [134.134.248.4]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5MJMb7n016748 for ; Fri, 22 Jun 2001 12:22:39 -0700 (PDT) Received: from SMTP (orsmsxvs01-1.jf.intel.com [192.168.65.200]) by hebe.or.intel.com (8.9.1a+p1/8.9.1/d: relay.m4,v 1.40 2001/06/06 21:14:49 root Exp $) with SMTP id TAA03707 for ; Fri, 22 Jun 2001 19:21:38 GMT Received: from orsmsx29.jf.intel.com ([192.168.70.29]) by 192.168.70.200 (Norton AntiVirus for Internet Email Gateways 1.0) ; Fri, 22 Jun 2001 19:21:38 0000 (GMT) Received: by orsmsx29.jf.intel.com with Internet Mail Service (5.5.2653.19) id ; Fri, 22 Jun 2001 12:21:36 -0700 Message-ID: <7FD5C79AD680D211AC4100A0C96B501C084A782C@orsmsx49.jf.intel.com> From: "Peters, Stephen" To: "'ibis@eda.org'" Subject: RE: Junk mail? Date: Fri, 22 Jun 2001 12:21:29 -0700 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" Hi Chris, All: I've been receiving the occasional spam for the past year or two now (including the #AD6 one you mention), and like you I suspect someone has harvested my address off of the IBIS list. As far as volume, it's been pretty light -- maybe one group of spam posts a month -- but then again I live behind a pretty sophisticated firewall that detects/blocks spam and virus. (Also, if one does make it thru I report it.) As far as your question goes, I believe anyone can send a message to the list without being a member (witness the 'subscribe' messages sent to ibis@eda.org). Setting up a system that forces folks to subscribe before posting, and then check all posting for a legit subscription address would help discourage random spamming, and I will work with John Angulo (IBIS postmaster) to see what is possible with our current mail setup. Unfortunately, I don't know of a foolproof way to protect the list or the users on it. The best defense is consistently reporting UCE/spam to the originating ISP thereby getting the spammer's account pulled, but tracking 'em down can be time consuming. Any volunters? Hope this helps. Regards, Stephen Peters Intel Corp. From owner-ibis Tue Jun 26 08:33:22 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id f5QFXJ7n027967 for ; Tue, 26 Jun 2001 08:33:20 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id LAA17806 for ; Tue, 26 Jun 2001 11:32:18 -0400 (EDT) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id LAA08922 for ; Tue, 26 Jun 2001 11:32:17 -0400 (EDT) Received: from innoveda.com (lap-gdeburgh.camarillo.innoveda.com [139.181.194.159]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with ESMTP id IAA03178 for ; Tue, 26 Jun 2001 08:32:01 -0700 (PDT) Message-ID: <3B38AAAC.5945A48@innoveda.com> Date: Tue, 26 Jun 2001 08:30:52 -0700 From: Guy de Burgh Organization: Innoveda X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 To: ibis@eda.org Subject: EIA IBIS Summit minutes (6/21/01) Content-Type: multipart/mixed; boundary="------------72B88016B030B267C42AF479" This is a multi-part message in MIME format. --------------72B88016B030B267C42AF479 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------72B88016B030B267C42AF479 Content-Type: text/plain; charset=us-ascii; name="m062101.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="m062101.txt" DATE: 6/26/01 SUBJECT: 6/21/01 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 2001 PARTICIPANTS LIST: 3Com (& CommWorks) Roy Leventhal Ansoft Corporation (Eric Bracken) Apple Computer John Figueroa Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Balistreri Avanti (Chen Hongyu) Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek Lynne Green*, Lance Wang Cisco Systems Syed Huq*, Lungfu Chen EMC Corporation Brian Arsenault, Jinhua Chen Fairchild Semiconductor Adam Tambone Huawei Technologies Rachild Chen IBM Michael Cohen, Greg Edlund, Wes Martin, Yeon-Chang Hahm, Bill DeVey, Pravin Patel Innoveda (& HyperLynx) Guy de Burgh*, John Angulo*, Cary Mandel, Matthew Flora, Steve Kaufer* Intel Corporation Stephen Peters*, Arpad Muranyi*, Dave Lorang, Michael Mirmak, Qinglun Chen, Will Hobbs, Wei-hsing Huang* LSI Logic Larry Barnes* Mentor Graphics Bob Ross*, Tom Dagostino*, Chris Reid, Mike Donnelly, Hazem Hegazy*, Tony Dunbar, Griff Derryberry, Dan Lake, Sherif Hammad, Mohammed Korany, Weston Beal*, Chris Swaim, Ali Samii, Eric Ronger, Karine Loudet, Daisaku Shiga*, Kenji Kushima* Micron Technology Randy Wolff, Yong Phan Mitsubishi Pat Hefferan* Molex Incorporated Gus Panella, Brian O'Malley Motorola (Rick Kingen) National Semiconductor Milt Schwartz North East Systems Associates Edward Sayre Philips Semiconductor Zack Ciccone, Rob Mataheroe Quantic EMC (Mike Ventham) Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz SiQual Scott McMorrow, Rob Hinz, Bernard Voss, Chris Brewster Texas Instruments Thomas Fisher*, Stephen Nolan, Ramzi Ammar, Jean Claude Perrin, Moshiul Haque* Time Domain Analysis Systems Dima Smolyansky, Steve Corey Tyco Electronics (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) John Berrie, Ralf Burning* OTHER PARTICIPANTS IN 2001: Actel Corporation Silvia Montoya Acuson Kim Helliwell AMCC Jeff Smith ASIS Ltd David Wright Brocade Communications Robert Badal BMW Friedrich Hasinger Cereva Networks Bob Haller Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam, Bill Ham Cypress (Rajesh Manapat) EADS Airbus Industry Claude Huet (Aerospatiale) EFM Ekkehard Miersch, Horle Raines EIA Cecilia Fleming* Ericsson Radio Systems Anders Ekholm* FCI Sercu Stefaan Foundary Networks Bertram Chan Framatom Conectors Danny Morlion Fraunhofer Institute Mariusz Faferko, Peter Kralicek Reliability and Integration Fujitsu Ltd Tadashi Arai, Takeshi Murakami Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt Hyundai Electronics Jongho Kang Idaho State University Al Davis* Infineon Technologies Christian Sporrer Intrinsix Corporation Steven Chin National Institute of Applied Etienne Sicard Science (INSA) Nokia Tapani von Ravner, Mika Castren, Janne Uusitalo Nortel Networks Calvin Trowell Oak Technology Darmin Jin Plexus Technology Group Joseph Socha Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier, Katja Koller, Wolfram Meyer, Eckhard Lenski, Gerald Bannert, Burkhard Muller, Christian Marot, Manfred Maurer, Amir Motamedi, Hans Pichlmaier Sintecs Hans Klos STMicroelectronics Peter Hirt, Fabrice Boissieres Sun Adrian Udenze Toshiba Corp. Hirokaza Kato*, Yuichi Koga*, Toshio Sudo* Xilinx Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode July 20 (888) 316-5901 none 8744603 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum, and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS The IBIS Summit Meeting was held in Las Vegas, Nevada the day after the trade show portion of the Design Automation Conference (DAC 2001) at the Las Vegas Hilton Hotel. The EIA IBIS Open Forum sponsored the meeting, lunch, and refreshments through membership funding. About 25 people representing 13 organizations participated. Bob Ross welcomed the participants. Everyone introduced him/herself. Semiconductor vendors, EDA vendors and users of EDA tools and IBIS models were represented. (Also, thanks to Cecilia Fleming and Guy de Burgh for handling the administrative and registration details.) All of the presentations and meeting documentation will be uploaded at http://www.eda.org/pub/ibis/summits/jun01/ The notes below give only some of the content and discussion. IBIS REPORT Bob Ross, Mentor Graphics Bob Ross introduced the general topics of the meeting. They consisted of An IBIS Report Business and Election of Officers Pre-emphasis Modeling and Driver Schedule SCSI and Fiber Channel Report Frequency Response and EMC IBIS-X and IBIS Macro Language Other Discussions and Ad Hoc Presentations Bob then gave a general status report. The EIA IBIS Open Forum continues to be active since 1993. It has about 30 official members and about 350 to 400 people on the e-mail reflectors. It has built up about a $14,000 reserve for future payments and projects. This year, ANSI/EIA-656-A (IBIS Version 3.2) was ratified as IEC 62014-1. Also Version 3.2.7 of the ibischk3 parser was released. More IBIS Accuracy report material was uploaded. The current IBIS projects include working on the Connector Specification, producing an IBIS Version 4.0 upgrade, and also working on a future version of IBIS designated IBIS-X and the IBIS Macro Language. In addition the Open Forum monitors and works with other committees including IMIC, EMC/EMI (ICEM) JEDEC and now T10 and T11 activities. Bob briefly outlined some Connector Specification Features and some approved and pending BIRDs for IBIS Version 4.0. The IBIS-X work will be reviewed later in the meeting. The Connector Specification and IBIS-X working groups are meeting regularly and are bringing the documents into syntactical alignment. The work has been going slowly, but it is continuing. Bob stated that IBIS continues to be well accepted in industry. IBIS models are supported by EDA, semiconductor, and modeling vendors and by the technical press. Finally, Bob thanked everyone for their contributions to IBIS. In particular, Bob thanked the officers and several other members including those who have made some technical contributions last year or who have helped set up the IBIS Summit meetings. The IBIS Open Forum works because several people are contributing to a number of tasks. PRE-EMPHSIS BUFFER MODELING Hazem Hegazy, Fady Galal, and Roshdy Hegazy, Mentor Graphics Hazem Hegazy shared some pre-emphasis modeling extraction based on some real IBIS model development projects. He defined pre-emphasis to mean that for a period of time additional current is supplied by the buffer at the initial part of a transition. One problem is extracting the DC I-V tables. Since a clock is necessary for correct operation, Hazem extracts the DC data using an AC, slow stair-step voltage at the output with steps at 0.1 V. Hazem proposed two modeling techniques. The first uses just the final DC I-V tables, but uses the [Rising Waveform] and [Falling Waveform] tables to provide the output transition shapes. This technique provides a reasonable simulation response, but is valid for only one frequency. A second modeling technique actually decomposes each transition of the response into two regions. The High-High region is based on extracting the stronger, pre-emphasized DC I-V tables and using the [Rising Waveform] Table to describe the shape. The Medium-High region uses the weaker DC I-V tables and a different [Rising Waveform] table. These two regions are concatenated by using the [Driver Schedule] keyword. A similar set of regions: Low-Low and Medium-Low are used with [Falling Waveform] tables for the falling transition. Arpad Muranyi, Larry Barnes and others questioned concatenation of the [Driver Schedule] models since many times the weaker driver just adds to an exiting transition. Hazem stated that it gave good results and provided an easier method to match waveform shapes. Al Davis commented that there would be problems with over-clocked situations because of the confusion of documenting delays within waveforms (versus) ramps. Bob Ross commented that actual waveform shapes need to be preserved for [Driver Schedule] tables and that IBIS would not handle the over-clocked situation. Hazem showed excellent correlation with the original Spice model. He showed improvement using the waveform tables instead of the [Ramp] keyword by itself to capture some overshoot shapes. This technique works for a range of clock frequencies (if the [Driver Schedule] times are adjusted). SCSI, FIBER CHANNEL IBIS MODELING OVERVIEW Larry Barnes, LSI Logic Larry Barnes presented an update on the T10 and T11 Committee modeling. First he outlined the SCSI and Fibre Channel Specifications and the purpose of SCSI and Fibre Channel Signal Modeling. On SCSI Signal Modeling Larry mentioned that the technical report is in final review, and will be forwarded to T10 for letter ballot in July 2001. The Fibre Channel Signal Modeling group is expected to complete its document by September 2001 and general release is expected in January 2002. These groups have select IBIS as the data exchange format for Semiconductor device models, Terminator models (SCSI only) and Connector models (SCSI only). Larry went on to say that IBIS 3.2 can be used for present SCSI devices, but cannot completely model "Fallback". There are also concerns that IBIS may not be accurate enough to model 1GHz / 750ps risetime signals. Also "emphasis" is not completely modeled. Larry outlined the SCSI and Fibre Channel future with particular attention to needs in IBIS. DRIVER SCHEDULE MODELING Chris Reid and Bob Ross, Mentor Graphics Bob Ross presented some work done by Chris Reid on investigating using the [Driver Schedule] keyword to approximate the second bit reduction effect. Larry Barnes had presented the need for modeling such an effect at the IBIS Summit meeting in January 29, 2001. Bob first presented some [Driver Schedule] syntax samples showing enhancement and reduction operation. The Syntax also showed an illegal case that might be promising when the actual clock frequency was out of synchronization from the delays in the [Driver Schedule] keyword. It was not acceptable because the initial DC level was ambiguous. Bob presented a simple test circuit that demonstrated the SCSI circuit operation. The operation involved switching a strong and weaker totem-pole CMOS stage into a terminated load biased at mid-voltage. In actual practice, the drivers are differential and the termination is a differential resistor. The sample circuit a set of output levels from 1 V to 4 V in 1 V steps and was implemented using the [Driver Schedule] keyword. Several people commented that the [Driver Schedule] documentation needs more examples and details on how it operates. IBIS Version 3.2 is not clear. Two cases for reduced strength operation were demonstrated. The first case used standard [Driver Schedule] syntax. The second case used the illegal syntax. However, it did not give the correct pulse widths. So, there is no need to extend the [Driver Schedule] keyword to accept the illegal syntax. What this means is that even with illegal syntax [Driver Schedule] can still only handle a single clock (bit period) frequency. Bob then showed an extended example which produced output levels from 1 V to 8 V in 1 V steps. Bob illustrated using the [Driver Schedule] syntax to produce a stair-step waveform over several cycles with 1 V, 1 nS steps. This application required configuring the driver switching using some Open_drain and Open_source stages because multiple transitions occurred within a the overall rising and overall falling portion of the cycle. The high-Z state of the Open_* drivers effectively disabled that driver and allowed another one to be turned on or off at a later time. Bob concluded that all of the examples worked correctly only for a given clock frequency that was in synchronization with the [Driver Schedule] keyword. This is a current limitation of the existing IBIS syntax and how it is used. We moved the election of officers as the next agenda item. ELECTION OF OFFICERS AND OTHER BUSINESS Bob Ross thanked the existing officers and gave each of them thank you plaques. Stephen Peters gave Bob a thank you plaque for his service as Chair. Bob Ross asked for nominations from the floor for the six officer positions starting with Chair. All of the existing officers had agreed to serve again and had been nominated previously. In the case of contested positions, only member companies can vote, one vote per company. Previously submitted proxy votes will be counted. Bob then nominated Stephen Peters to succeed him as Chair. With no other candidates, Stephen was elected by a show of hands. Stephen nominated Bob for Vice-Chair, and Bob was elected by a show of hands. The remaining officers were nominated by Bob and re-elected by a show of hands since all positions were uncontested. The following people will serve as officers of the EIA IBIS Open Forum for the 2001-2002 year. Chair: Stephen Peters, Intel Corporation Vice-Chair: Bob Ross, Mentor Graphics Secretary: Guy de Burgh, Innoveda Web Master: Syed Huq, Cisco Systems Postmaster: John Angulo, Innoveda Librarian: Roy Leventhal, 3Com The following presentation was made before lunch. MAKING BEHAVIORAL MODELS FOR FREQUENCY DOMAIN ANALYSIS (Moved from before the election of officers) Arpad Muranyi, Intel Arpad Muranyi explained why frequency effects are easier to analyze in the frequency domain. He presented a resonant circuit as an example showing how the shape of the waveforms are affected by the resonance effects. Controlling these effects means a buffer model that is accurate at all frequencies. Arpad then went on to talk about the frequency response of an IBIS model and its problems. He proposed a new model and went into the mathematical detail on the real and imaginary parts of it. A Laplace transform of the resonant circuit was created and simulated showing exact match with the behavioral model. Arpad described the current issues and work in progress and in his conclusion he mentioned that only one additional element for IBIS-X is needed, that complex number and Laplace transform capability is needed, and the concept can be extended to multi-port circuits. IBIS-X and IBIS MACRO LANGUAGE PROGRESS Stephen Peters, Intel Stephen Peters started by introducing the members of IBIS futures committee and summarizing the progress since the last summit. The IBIS-X document (Rev 0.6) has been posted for review and work is well underway in documenting the IBIS-ML macro language. One more document -- a library guide -- is planned but has not been started. Due to the emphasis on getting the macro language documented, work has not begun on defining the nodal-based package model syntax. The IBIS futures committee has also been reviewing the connector specification with an eye towards aligning the syntax, common keywords, and document format with the IBIS-X spec. Progress has been made, but it has become a bigger job than anticipated. Several people expressed the desire to turn the Connector Specification into the nodal-based package model description. Stephen pointed out that there are significant differences between describing a regular structure such as a connector and an irregular PCB or package. No definitive conclusion was reached, however Stephen stated that the futures committee would strongly consider the possibility. Stephen also noted that no work has been done on an API and he is awaiting someone to champion this idea. Stephen then concluded this part of his presentation by noting the immediate goal of the futures committee is to finish the macro language documentation, followed by defining the nodal-based package syntax and driving the connector spec to completion. The discussion then turned to a review of the IBIS-X document itself. Stephen started by presenting the philosophy behind IBIS-X (separation of data from algorithm) then showed how it is backwards compatible with current IBIS and a possible transition path between the two. He then described the two step process for creating a new buffer model in IBIS-X. In brief, the [Define] keyword allows the user to create a behavioral description of a buffer using IBIS-ML (the macro language). The data for the model is still provided using an IBIS-X data template, just as in traditional IBIS. Stephen also introduced the concept of object 'classes' and 'types' and object 'customization'. Stephen then gave a brief overview of the sections of the document itself, pointing out new keywords and changes. The General Syntax Rules and Guidelines has adopted the connector spec "120 character line" limit and ambiguous/unclear rules have been clarified. Major sections of the file now have [Begin][End] blocking and keywords for text and library 'Include' functions have been added. While the [Component] section remains basically unchanged, the [Model] section has been replaced with a section describing how to define new models (as shown above). A placeholder for the forthcoming package model has been included, and the existing EBD specification has been incorporated. A brief discussion was held on the possibility of turning the EBD spec into a nodal based syntax, thus creating our package description. IBIS-X AND IBIS-ML Stephen Peters, Intel Finally, Stephen presented a selection of slides from another presentation given previously that showed some of the syntax of the IBIS Macro Language. Basic R/L/C elements, dependent and independent sources, and the syntax for including then in a netlist were presented. Arpad Muranyi requested that a 'Laplace' type element be added, as well as support for complex numbers. After discussion Stephen agreed that the need was there and they would be added. Stephen also covered some of the programming constructs available in the language, emphasizing the difference between the run time checks of alarm and the compile time static logic checks of the if-then-else and select-case constructs. A 'foreach' operator was also presented. Stephen then turned the podium over to Al Davis. APPLYING THE IBIS MACRO LANGUAGE TO NEW KEYWORDS Al Davis, Idaho State University Al Davis described some applications using the Macro Language. He showed how to define a component as a macro explaining Pin Mapping, Series Pin Mapping and Diff Pin. Al then explained how a standard macro could be 'inherit'ed and 'extend'ed. He gave, as an example, a true differential buffer. Also Test data and Test loads explaining the concept of 'trigger's was presented. EMC PARAMETERS FOR IBIS Guy de Burgh, Innoveda Guy de Burgh presented a number of parameters that could be used for EMI analysis. These include the Power Dissipation Capacitance (Cpd) which is readily available in databooks, and can also be used for thermal analysis. Also presented were parameters for heatsinks and connectors. Examples of how these parameters would fit into the IBIS specification were shown. In conclusion a more detailed specification is being prepared that will include how to measure these parameters. This will then be submitted as a Bird. BUS SWITCH MODELING ISSUE (Ad Hoc presentation) Tom Dagostino, Mentor Graphics Tom Dagostino commented on some unanticipated bus switch behaviors he observed on actual parts. The conventional Series MOSFET model describes an NMOS device. The [On] tables assume that the gate is held high, and the Vgs tables describe low current levels at low Vgs voltages for constant Vds values. Some devices are constructed using PMOS devices. The [On] state gate is held low, and the actual Vgs table starts with a high current that decreases with increasing Vgs values. Furthermore, an NMOS and PMOS FET can be put in parallel and switched by a driver. This typically produces a non-monotonic table with high currents at low and high Vgs voltages, and lower currents in the middle. The last two variations were not anticipated by the [Series MOSFET] keyword. For the second case, ibischk3 reports the wrong polarity. For the third case, ibischk3 reports an monotonicity error. In both cases, the EDA tool algorithms probably do not work. Some discussion occurred regarding some of the MOSFET model table details. Tom asked if this was a serious enough problem to create a new BIRD to handle the new cases. There seemed to be general agreement to consider both a BIRD and a possible fix to ibischk3, if needed to deal with these technologies. It may require implementation in IBIS-X, but at least the issue needs to be documented. OVERCLOCKED PROBLEMS (Ad Hoc presentation) Arpad Muranyi, Intel Arpad Muranyi described the overclocked problem. IBIS waveforms preserve initial delay. When the clock frequency is increased (pulse width is reduced), the transition of a falling edge to the rising edge may occur before the falling edge has completed, and the algorithm jumps into the same truncated value in the rising edge. This process causes the initial delay be eliminated. This may cause false Tco values for the second pulse. Arpad showed some illustrations on the white board showing a succession of such transitions for a real device based on Spice simulations. Arpad proposed a process that retains the initial delay. It may apply only to a CMOS buffers with some internal capacitance pre-shoot. The peak of the preshoot defines when the actual output buffers start the transition. Stephen Peters asked why we should be concerned with this. The period is too small. Bob Ross responded that customers were operating buffers at actual clock frequencies. Larry Barnes indicated that this was important for double edged clocking. Bob indicated that this could also be an artifact of two-waveform based edges where one of the edges is usually much slower than the other. Al Davis asked if the IBIS Specification should state what the EDA tool is to do in this case. Bob stated that the tool should produce results that match the data best. However, it is not known what algorithm is best (or even if there is a good solution). However, a specific solution could be implemented in IBIS-X. CLOSING THE MEETING Because of vacation schedules, the next teleconference meeting is scheduled on July 20, 2001. Bob Ross thanked the participants and presenters for their contributions and Cecilia Fleming and Guy de Burgh for helping in the meeting arrangements. Stephen Peters thanked Bob for his service as Chair. Stephen then discussed some working group meeting plans and mentioned that the next IBIS Summit Meeting is scheduled in Massachusetts in September 2001. With no further discussion, Stephen closed the meeting. NEXT MEETING: The next teleconference meeting will be on Friday, July 20, 2001, from 8:00 AM to 10:00 AM. ============================================================================== NOTES IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831 stephen.peters@intel.com Senior Hardware Engineer, Intel Corporation M/S JF4-215 2111 NE 25th Ave. Hillsboro, OR 97124-5961 VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799 roy_leventhal@3com.com Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary) 1800 W. Central Rd. Mt. Prospect, IL 60056-2293 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 jangulo@innoveda.com Development Engineer, Innoveda 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== --------------72B88016B030B267C42AF479--