From owner-ibis Mon Mar 5 12:56:33 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f25KuU125838 for ; Mon, 5 Mar 2001 12:56:31 -0800 (PST) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id PAA08931 for ; Mon, 5 Mar 2001 15:56:34 -0500 (EST) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id PAA03179 for ; Mon, 5 Mar 2001 15:56:32 -0500 (EST) Received: from f22.innoveda.com (f22.camarillo.innoveda.com [139.181.194.48]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id MAA00140 for ; Mon, 5 Mar 2001 12:55:26 -0800 (PST) Received: by f22.innoveda.com (SMI-8.6/SMI-SVR4) id MAA08396; Mon, 5 Mar 2001 12:56:25 -0800 Date: Mon, 5 Mar 2001 12:56:25 -0800 From: guy@camarillo.innoveda.com (Guy de Burgh) Message-Id: <200103052056.MAA08396@f22.innoveda.com> To: ibis@eda.org Subject: EIA IBIS Open Forum Meeting Minutes Date: 3/5/01 SUBJECT: 3/02/01 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS AND 2001 PARTICIPANTS LIST: 3Com (& CommWorks) Roy Leventhal* Agilent (Mark Chang) Ansoft Corporation (Eric Bracken) Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Balistreri Avanti (Chen Hongyu) Brocade Communications Robert Badal Cadence Design Ian Dodd* Cisco Systems Syed Huq, Lungfu Chen Compaq Peter LaFlamme, Ron Bellomio, Quang Dam Cypress (Rajesh Manapat) EMC Corporation Brian Arsenault, Jinhua Chen Fairchild Semiconductor Adam Tambone* IBM Michael Cohen, Greg Edlund*, Wes Martin, Yeon-Chang Hahm, Bill DeVey, Pravin Patel* Innoveda (& HyperLynx) Guy de Burgh*, John Angulo* Intel Corporation Stephen Peters*, Arpad Muranyi*, Dave Lorang, Michael Mirmak*, Qinglun Chen, Will Hobbs LSI Logic Larry Barnes* Mentor Graphics Bob Ross*, Tom Dagostino, Chris Reid, Mike Donnelly, Hazem Hegazy, Tony Dunbar, Griff Derryberry, Dan Lake, Sherif Hammad Mohammed Korany, Weston Beal Micron Technology Randy Wolff*, Yong Phan* Mitsubishi (Tam (Tom) Cao) Molex Incorporated Gus Panella, Brian O'Malley Motorola (Ron Werner) National Semiconductor Milt Schwartz Nortel Networks Calvin Trowell North East Systems Associates Edward Sayre Philips Semiconductor Zack Ciccone Quantic EMC (Mike Ventham) Robinson-Nugent, Inc. (Alexander Barr) Siemens AG Bernhard Unger, Helmut Katzier Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz SiQual Scott McMorrow, Rob Hinz, Bernard Voss, Chris Brewster Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar Time Domain Analysis Systems Dima Smolyansky, Steve Corey Tyco Electronics (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) (Werner Rissiek) OTHER PARTICIPANTS IN 2001: Actel Corporation Silvia Montoya Acuson Kim Helliwell AMCC Jeff Smith Apple Computer John Figueroa ASIS Ltd David Wright Cereva Networks Bob Haller* EIA Cecilia Fleming* FCI Sercu Stefaan Foundary Networks Bertram Chan Framatom Conectors Danny Morlion Fujitsu Ltd Tadashi Arai, Takeshi Murakami Huawei Technologies Rachild Chen Hyundai Electronics Jongho Kang Intrinsix Corporation Steven Chin Nokia Tapani von Ravner Oak Technology Darmin Jin Plexus Technology Group Joseph Socha STMicroelectronics Peter Hirt Xilinx Susan Wu Independent, Consultant Al Davis In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode March 16, 2001 European IBIS Summit Meeting - No Phone Bridge March 30, 2001 (916) 356-9200 2-524673 6244264 April 20, 2001 (916) 356-9200 2-524674 3881934 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM Bob Haller from Cereva Networks (a 250 person "start-up" company) joined. Bob had been active in the past years with another company. He is now involved as actively uses IBIS models and is interested in accuracy issues. Bob also expressed interest in getting his company to become an official member of the EIA IBIS Open Forum. Adam Trambone of Fairchild Semiconductor had attended the Designcon 2001 IBIS Summit Meeting. He is responsible for producing IBIS models for several technologies. MEMBERSHIP UPDATE AND TREASURER'S REPORT Bob Ross reported that Signal Integrity Software (SISoft) is now an official EIA IBIS Open Forum member (and now listed in the Voting Members Participants List). Bob stated, as previously reported, that we have about 22 payments out of 36 invoices so far. Bob said that he is working with Cecilia Fleming on the final year 2000 results. He expects credit for some additional revenue that was not given in the preliminary report at the February 16, 2001 meeting. REVIEW OF MINUTES AND AR'S The February 16, 2001 IBIS Minutes were approved without change. The AR's will be discussed during the meeting. MISCELLANY/ANNOUNCEMENTS None. PRESS AND WEB PAGE UPDATES Bob Ross reported that Syed Huq made roster updates and added a new logo in the Poster link. NEW MODELS AVAILABLE, LIBRARY UPDATE None. OPENS FOR NEW ISSUES During the Meeting, Bob Ross - Version 4.0 Release Plans INTERNATIONAL/EXTERNAL PROGRESS - IEC 62014-1 (IBIS Version 3.2) - Cecilia Fleming added more clarification to the previous report that if the FDIS (Final Draft International Standard) vote is successful, IBIS Version 3.2 can be published as an official international standard sometime after April 13, 2001. - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) - No report. - IEC PWI 93-1 Models of Integrated Circuits for EMI Behavioral Simulation (formerly designated as IEC 93/67/NP IBIS and EMC Simulation) - Bob Ross mentioned that there are three presentations planned at the European IBIS Summit Meeting in Munich, Germany on March 16, 2001. This will be discussed later. Also, there are two other related presentations on EMI and ground bounce issues. - JEDEC JC-16 - Modeling and Testing - No report. - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the National Committee for Information Technology (NCITS)) - Larry Barnes reported on the meeting held February 20-22, 2001. Work is progressing on the SCSI Signal Modeling (SSM) Technical Report. The Committee is interested in proposing a "fallback driver" function in IBIS similar to [Driver Schedule] that reduces the strength of the buffer if a second consecutive bit is specified. This functionality is needed soon since the final specification of the SCSI device will be ready in several months. Larry also mentioned that 3-level logic will become standardized in several years, but is not pushing for this functionality in the current IBIS Standard. Bob Ross stated that this would be implemented better in IBIS-X. Larry commented that the SSM report took much information from the IBIS Cookbook and adapted it to the SCSI standard. Bob also mentioned that had a few editorial comments related to some nomenclature conventions we adopted after the cookbook was issued. The document can be retrieved from the SCSI Signal Modeling Technical Report (SCM) link under: http://www.t10.org/ssm.htm or directly at: ftp://ftp.t10.org/drafts/ssm/ssm-r02.pdf Larry recommended to his Committee members to become involved with the IBIS Open Forum. DATE 2001 EUROPEAN IBIS SUMMIT MEETING Bob Ross introduced the topic by giving the basic information so far on the European IBIS Summit meeting to be held Friday, March 16, 2000 in Munich, Germany along with the Design Automation and Testing in Europe (DATE 2001) conference and exhibit. The IBIS Summit Meeting is on the day after the trade show portion of the show. Bob stated that four companies are co-sponsors of the meeting: Cadence, Innoveda, Mentor Graphics, and Zuken (Incases). This pays for the meeting room, refreshments and free lunch to participants. Bob stated that a third Announcement was recently sent on February 27, 2001, with about eleven presentations. The program now completely filled with about fourteen presentations, and the meeting will last all day. So far, Bob estimates about 25 people have signed up, which translates into about 40 attendees so far. The next announcement will contain a revised Agenda and will ask for signup responses to better anticipate the number of reservations for lunch that is provided. Bob then went over the additions to the program from the last announcement. A draft Agenda is listed below. EUROPEAN IBIS SUMMIT MEETING Astron Hotel, Munich Germany MARCH 16, 2001 8:30 REFRESHMENTS 9:00 INTRODUCTIONS AND PROGRAM Bob Ross, Mentor Graphics, USA 9:30 Experiences with and Tips for IBIS Models Eckhard Lenski, Siemens AG, Germany 10:00 Extraction of Key IBIS Parameters for Easier Model Selection John Berrie, Zuken, England 10:30 BREAK 10:45 DOGEN, A Siemens Internal Model Tool, Extension 1999 - 2001 Hans Pichlmaier, Siemens AG, Germany 11:15 LVDS Modeling Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt 12:00 LUNCH 13:00 STTL-2 Modeling Experiences Bernhard Unger, Siemens AG, Germany 13:30 CAN (Controller Area Network) Bus Modeling Manfred Maurer, Siemens AG, Germany 14:00 EMC Standardization Progress (title to be determined) Jean-Claude Perrin, Texas Instruments, France 14:15 EMC Models (title to be determined) Christian Marot, Siemens, France 14:30 Parasitic IC Emission Modeling Etienne Sicard, National Institute of Applied Science, Toulouse, France 15:00 BREAK 15:15 Ground-Noise Model Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration, Germany 15:45 Radiated Emission Model for IC Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, Germany 16:15 Points of View for High Frequency IBIS Models Gerald Bannert, Siemens AG, Germany 16:30 IBIS-X Arpad Muranyi, Intel, USA 16:55 Concluding Items 17:00 END Arpad Muranyi stated that he plans to attend and can work with the final twenty five minutes with information based on some previous presentations. IBIS MODEL REVIEW COMMITTEE DISCUSSION John Angulo stated (later in the meeting) that he has received no new models since the report on the February 16, 2001 meeting. CONNECTOR PROPOSAL REVIEW Bob Ross summarized a meeting between he and Gus Panella held on February 27, 2001. The main changes were to add the [Begin Header] and [End Header] syntax as done in the IBIS-X document. Bob also indicated that there will be a pass to improve the document appearance including removing the left-hand bars. Ian Dodd had sent out a revised code proposal to the committee to bring its syntax closer to the IBIS-X macro language proposed syntax. Bob stated that this revised code would be included. The basic plan is to finish doing these changes and then issue a new document for the IBIS Open Forum to review. It would be in several formats including .txt, .doc, and .pdf. The plan is to schedule some time (15 to 30 minutes) of each teleconference meeting to review specified portions of the document. People can still comment on the document as a whole and we can continue to work in the other areas. Hopefully this review completion can be completed in the targeted June 2001 time frame. IBIS FUTURES (IBIS-X, API, BIRDxx) Stephen Peters reported on the progress to date and on the February 20, 2001 meeting. The next meeting will be on the two week schedule on March 6, 2001. Stephen is working on another update of the specification document the Working Group is developing. The target is to get this document and the IBIS-X macro language documented by the June 2001 time frame. One item that needs more work is the pin to pad packaging portion. There might also be interest in applying the Swathing methods in the Connector document. Also, Bob Ross mentioned that a number of older proposals could be reviewed. Bob also mentioned that at the next Working Group meeting, Arpad's IBIS-X presentation for the European IBIS Summit might be discussed. IBISCHK3 BUG TRACKING Bob Ross moved this agenda item ahead until Greg Edlund returned to the call. Bob reported that Matthew Flora is working on the fix to BUG53 and BUG34. Matthew will coordinate with Atul Agarwal and send the revised source code to him. BUG34 was authored by Matthew, and Bob felt that Matthew knew the issues and possible areas of code that needed fixing. Bob wants to get an ibischk3 Version 3.2.7 distributed quickly, even if that is the only fix. - BUG54 - Corners with NA give Bad Test Load Warnings Bob Ross introduced BUG54, authored by Michael Mirmak. It reports a Warning message for the timing test load Vmeas crossing for min and max column cases even when the min and max columns contain NA entries. Bob classified BUG54 as Annoying, Low, and Open. However, Bob expressed some concerns regarding BUG54. While most of the min and max columns contained NA entries, three keywords ([Ramp], [Voltage Range], and [Temperature Range]) did contain min and max column numerical entries. The problem may still exist if these entries were NA, but the example needs to be produced to test this. Also, since most EDA tools should use default typical entries if NAs exist, the problem may still exist. Bob thought that with such defaults, the model should work fine and should not produce Warning messages. More investigation is needed in this area. Bob thought the actual set of tests and Warnings might become complicated and require effort to sort out combinations when only some keywords contain NA entries. Bob was concerned about the effort involved versus the benefit obtained. Michael commented later in the meeting that he would issue a new version of BUG54 with a better example or examples. Bob planned more discussion at the next teleconference meeting to decide on whether or not to fix BUG54 and how to fix it. BIRD69.1 - GOLDEN WAVEFORMS Greg Edlund introduced BIRD69.1 by noting that it was issued in response to comments of the February 16, 2001 meeting. Briefly, the intent of BIRD69.1 is to provide golden waveforms within the IBIS model along with the test configuration used to obtain these waveforms. The user would have the golden waveform information and could test the IBIS model using the specified test configuration to validate the performance of the model. The EDA tool could also perform such a test. However, since this information is contained in new keywords, the EDA tool could also ignore these keywords. Greg noted the changes made in BIRD69.1. They are documented in BIRD69.1 and include the following: Change Node to Test_point Remove Driver_model_name since it was redundant Add R_diff for differential models Change some terminology so that parallel terminators V_term1 and V_term2 can be attached to different voltages Add Pkg_pin to describe what package is to be used for the model Bob Ross called for discussion. Stephen Peters commented that it still called for a big network with fixed topology. The IBIS-X approach would support a more general tester functionality. Roy Leventhal commented that he favors BIRD69.1 since it could be specified for IBIS Version 4.0 earlier than the anticipated IBIS-X. Bob Haller is concerned about the accuracy of models. He emphasized that the the EDA tool could use or ignore the information. But the golden waveform provides important information about the accuracy of the model. Stephen stated that while there may be merit, it might not be of as high a priority as some other items. We set a new agenda item to talk about the possible new items needed for Version 4.0. Greg stated that this should be a low impact BIRD. However, it would increase the size of the IBIS Standard, and create more work for updating ibischk3. Yong Phan stated that one customer required golden data. In the short term this need was satisfied by suppling a Spice model as reference. Bob provided some technical comments about BIRD69.1 and about some related implications: One implication concerning the R_diff entry that both the Non-Inverting and Inverting drivers would have to be from the same model. This is not an IBIS requirement. The models could be different. However, Bob did not know whether this restriction would be a problem. Bob was unsure that the Tref entry to state a time reference was needed or the best way to handle this. EDA tools might do their own alignment of data. The actual alignment might be shifted by leading edge removal that is implied by BIRD68. The Pkg_pin addition was a good idea. Some of the golden data might be from measurements, and we need to know what pin is used. However, the approach in IBIS is still ambiguous. Some semiconductor vendors supply several components with a file that may reference the same model. One reason for doing this is to cover package variations that are shipped. These variations may even have different pin outs. Bob also stated another implication of this subparameter. It is not clear clear what to do if Pkg_pin referred to a pin that was modeled using a coupled package model. Greg stated that he did assume a single pin model configuration. Bob noted that the original [Rising Waveform] and [Falling Waveform] keywords got around the pin ambiguity problem by adding R_dut, L_dut, and C_dut subparameters. A similar approach could be used for the golden waveform keywords. Another implication of having [Golden Rising Waveform] and [Golden Falling Waveform] is that the golden responses would be for only one edge. Bob thinks this is all right. However, some semiconductor vendors might want to provide full cycle references. Also there might be some implications if the IBIS model was actually derived from edges after several cycles. Finally, Bob stated that all of the subparameters should be optional. A large list is currently required, as BIRD69.1 is now structured. The defaults could be stated based on unspecified shunt elements being open and series elements being shorted. Also, this resolves an inconsistency regarding requiring "none" if no Receiver model or Pkg_pin were needed. They should be included only if listed. Bob felt that not all of the comments needed to be addressed by changes, but some of the limitations should noted. Bob asked Greg to consider the comments and propose a response as BIRD69.2 for further discussion at the next teleconference meeting. VERSION 4.0 RELEASE PLANS - New Topic Bob Ross opened the topic by noting that the six approved BIRDs could go into IBIS Version 4.0 or could be implemented in IBIS-X as a Version 4.0 emulation mode. Stephen Peters felt that IBIS Version 4.0 was needed along with IBIS-X. Arpad Muranyi commented that it is needed, and is about a year late from when it was originally expected. Larry Barnes stated that the fallback driver functionality is needed soon since SCSI applications will have this feature in months. Bob stated he would work off line with Larry to propose a BIRD. Bob noted that some other related features that are needed could be included. He favored using the Submodel approach rather than a method patterned after [Driver Schedule]. Stephen noted that some PCI functionality concerning more timing thresholds has been discussed on e-mail reflectors and is needed. He plans to work on this. Greg Edlund commented that he and Syed Huq have also been concerned about PCI specification needs and might join in helping define and review this functionality. Bob stated that he might want to include some possible improvements for SSO (simultaneous switching output) modeling as proposed last year by Bernhard Unger. Bob stated that IBIS Version 4.0 is still intended to be a "minor" upgrade to capture some of the recent needs for completeness. However, some EDA tools might actually use IBIS-X methods to implement the new features. Bob also stated that in targeting a Version 4.0 release in the near futures, all of the possible improvements need to be proposed soon. He expects that a few more BIRDs may also be proposed as part of the process to reach closure. NEXT MEETING: The next meeting will be the European IBIS Summit Meeting in Munich, Germany on Friday, March 16, 2001. No teleconference connection is planned. The next teleconference meeting will be on Friday, March 30, 2001, from 8:00 AM to 10:00 AM. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 stephen.peters@intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799 roy_leventhal@3com.com Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary) 1800 W. Central Rd. Mt. Prospect, IL 60056-2293 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 jangulo@innoveda.com Development Engineer, Innoveda 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== From owner-ibis Mon Mar 5 13:04:51 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f25L4n125888; Mon, 5 Mar 2001 13:04:49 -0800 (PST) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id NAA16491; Mon, 5 Mar 2001 13:04:53 -0800 (PST) Received: from mentor.com (bob.wv.mentorg.com [147.34.83.63]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id FW9BGNA7; Mon, 5 Mar 2001 13:04:52 -0800 Sender: bobr@relay1.mentorg.com Message-ID: <3AA3FF72.B3313EC1@mentor.com> Date: Mon, 05 Mar 2001 13:04:50 -0800 From: Bob Ross X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: si-list@silab.eng.sun.com, ibis@eda.org, ibis-users@eda.org CC: "Ross, Bob" Subject: EUROPEAN IBIS SUMMIT MEETING DRAFT AGENDA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit To All: Here is a draft Agenda of the European IBIS Summit Meeting scheduled on Friday, March 16, 2001 in Munich Germany. We will have a full, all day meeting with interesting presentations and discussions. If you plan to attend and have not yet signed up, please notify Karine Loudet: karine_loudet@mentor.com If any of the presenters have problems with the time slots, let me know. A final agenda will be sent out later this week. Bob Ross Mentor Graphics bob_ross@mentor.com EUROPEAN IBIS SUMMIT MEETING Astron Hotel/Neue Messe Eggenfeldener Strasse 100, Munich Germany MARCH 16, 2001 8:30 REFRESHMENTS 9:00 INTRODUCTIONS AND PROGRAM Bob Ross, Mentor Graphics, USA 9:30 Experiences with and Tips for IBIS Models Eckhard Lenski, Siemens AG, Germany 10:00 Extraction of Key IBIS Parameters for Easier Model Selection John Barrie, Zuken, England 10:30 BREAK 10:45 DOGEN, A Siemens Internal Model Tool, Extension 1999 - 2001 Hans Pichlmaier, Siemens AG, Germany 11:15 LVDS Modeling Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt 12:00 LUNCH 13:00 STTL-2 Modeling Experiences Bernhard Unger, Siemens AG, Germany 13:30 CAN (Controller Area Network) Bus Modeling Manfred Maurer, Siemens AG, Germany 14:00 EMC Standardization Progress Jean-Claude Perrin, Texas Instruments, France 14:15 EMC Models Christian Marot, Siemens, France 14:30 Parasitic IC Emisson Modeling Etienne Sicard, National Institute of Applied Science, Toulouse, France 15:00 BREAK 15:15 Ground-Noise Model Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration, Germany 15:45 Radiated Emission Model for IC Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, Germany 16:15 Points of View for High Frequency IBIS Models Gerald Bannert, Siemens AG, Germany 16:30 IBIS-X Arpad Muranyi, Intel, USA 16:55 CONCLUDING ITEMS Bob Ross, Mentor Graphics, USA 17:00 END From owner-ibis Mon Mar 5 15:00:05 2001 Received: from ganymede.or.intel.com (jffdns01.or.intel.com [134.134.248.3]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f25N03126407 for ; Mon, 5 Mar 2001 15:00:04 -0800 (PST) Received: from SMTP (orsmsxvs02-1.jf.intel.com [192.168.65.201]) by ganymede.or.intel.com (8.9.1a+p1/8.9.1/d: relay.m4,v 1.35 2001/02/12 09:03:45 smothers Exp $) with SMTP id XAA00911; Mon, 5 Mar 2001 23:00:13 GMT Received: from orsmsx29.jf.intel.com ([192.168.70.29]) by 192.168.70.201 (Norton AntiVirus for Internet Email Gateways 1.0) ; Mon, 05 Mar 2001 23:00:12 0000 (GMT) Received: by orsmsx29.jf.intel.com with Internet Mail Service (5.5.2653.19) id ; Mon, 5 Mar 2001 15:00:09 -0800 Message-ID: From: "Mirmak, Michael" To: "'ibis@vhdl.org'" , "'ibis@eda.org'" Subject: Proposal for treatment of BUG54... Date: Mon, 5 Mar 2001 15:00:06 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" In Friday's IBIS Forum, I took an AR to examine how the parser treats IBIS files where all the min/max parameters are set to NA (rather than just the min/max V-I curves). Recall that BUG54 was filed in order to correct the parser's treatment of models missing a [Pullup] section and max/min V-I curves. The parser currently shows warnings regarding the inability of such a model to drive the buffer delay test load through the specified Vmeas point. The parser continues to give errors on the missing max/min V-I curves, regardless of whether ramps, c_comp or voltage range min/max values are present or absent. I have enclosed an additional example below. Therefore, we may conclude that the parser is only looking for V-I curves in the min & max columns (for models without a [Pullup] section) to use in determining whether the model can satisfy the buffer delay voltage requirements. To decide how to resolve BUG54, we need to decide how the parser should treat the keyword "NA" for this case. The spec unfortunately allows two interpretations of "NA," according to the two rules below: Rule 1) "NA" means "no data" -- no assumption is to be made as to the operation of the modeled device in those columns under those conditions. This is the intent behind using NA to entirely replace a column of V-I, t-V, ramp, c_comp or operating condition data. Rule 2) "NA" means "no explicit data" -- data is not given for this particular condition in this particular column, but the state of the device at this point is to be inferred from the surrounding context by the sim tool. This is the normal usage of NA, when mixed into a column of V-I or t-V data. This is also the reason behind prohibiting the use of NA as a starting or ending point in a column of data. Currently, the parser checks V-I curves using Rule 2 above for models where partial data is available in all three columns. Rule 1 is used for most models where NA completely replaces V-I data in a min or max column. BUG54 was filed because the parser incorrectly applies Rule 2 for models where the keyword [Pullup] is missing and entire V-I columns are replaced by NA. For any other case where an entire column is missing, Rule 1 is the only rule applied. So, to "fix" BUG54, I would suggest simply eliminating the warning messages and applying Rule 1 to all models without a [Pullup] section and without min/max V-I curves. This makes the parser self-consistent and also gives sim tool vendors the same flexibility about the treatment of NA as they currently have. No additional cases or interpretation would be required. Any suggestions or advice? I will incorporate any consensus here into a revised BUG54, which I will distribute for posting a week before the next IBIS meeting (March 30). Thanks! - Michael Mirmak, Intel Corp. |*********************************************************************** | [IBIS Ver] 3.2 [File Name] bug54a.ibs [File Rev] 0.0a [Date] 05-March-2001 [Source] File created from specification [Notes] Using the IBISCHK3 v3.2.5 & v3.2.6 parsers, the following file will show two misleading warnings related to the buffer delay fixture. | [Disclaimer] (C) Copyright 2001 Intel Corp. All rights reserved This model is for demonstration purposes only, | [Component] GENERIC_IBIS [Manufacturer] Intel Corp. | [Package] | typ min max R_pkg 6.0mO NA NA L_pkg 5.0nH NA NA C_pkg 1.0pF NA NA | | [Pin] signal_name model_name R_pin L_pin C_pin 1 TestSignal1 TestModel1 | |************************************************************************ | [Model] TestModel1 Model_type I/O_open_sink |Model_type I/O Polarity Non-Inverting Enable Active-Low | Vinl = 800mV Vinh = 2.0V | Cref = 0F Rref = 25ohms Vref = 5.0V Vmeas = 2.5V | C_comp 5.00pF NA NA | [Temperature Range] 27.00 NA NA [Voltage Range] 5.0V NA NA | |[Pullup] || voltage I(typ) I(min) I(max) || | -5.0000 0.0m NA NA | -4.0000 0.0m NA NA | 0.0000 0.0m NA NA | 5.0000 0.0m NA NA | 10.0000 0.0m NA NA | | [Pulldown] | voltage I(typ) I(min) I(max) | -5.0000 -40.0m NA NA -4.0000 -39.0m NA NA 0.0000 0.0m NA NA 5.0000 200m NA NA 10.0000 400m NA NA | | [GND Clamp] | voltage I(typ) I(min) I(max) | -5.0000 -3900.0mA NA NA -0.7000 -80.0m NA NA -0.6000 -22.0m NA NA -0.5000 -2.4m NA NA -0.4000 0.0A NA NA 5.0000 0.0A NA NA | [Power Clamp] | voltage I(typ) I(min) I(max) | -5.0000 4450.00m NA NA -0.7000 95.0m NA NA -0.6000 23.0m NA NA -0.5000 2.4m NA NA -0.4000 0.0m NA NA 0.0000 0.0m NA NA | [Ramp] |variable typ min max dV/dt_r 2.20/1.06n NA NA dV/dt_f 2.46/1.21n NA NA R_load = 300ohms | | |************************************************************************ [End] From owner-ibis Wed Mar 7 17:11:12 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f281BB109837 for ; Wed, 7 Mar 2001 17:11:12 -0800 (PST) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id RAA29951; Wed, 7 Mar 2001 17:08:51 -0800 (PST) Received: from mentor.com (bob.wv.mentorg.com [147.34.83.63]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id FW9BG4W4; Wed, 7 Mar 2001 17:08:50 -0800 Sender: bobr@relay1.mentorg.com Message-ID: <3AA6DBA1.B5355EFC@mentor.com> Date: Wed, 07 Mar 2001 17:08:49 -0800 From: Bob Ross X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: "Mirmak, Michael" CC: "'ibis@eda.org'" Subject: Re: Proposal for treatment of BUG54... References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Michael: Here are some thoughts. I think your rule 1 proposal makes sense for the purposes of ibischk3 testing. However, it might still be complicated. The revised rule would be to not perform the test if NA's exist for all entries of either the [Pulldown] or [Pullup] tables. The *_Open* cases have to be treated separately with a different rule. Many models with typical only clamps exist, so NA's can still exist in the typ columns only. In practice, the EDA tools might apply rule 2 in some manner, but ibischk3 cannot perform the check. Anyway, there are a lot of implications. I would favor a proposal that removes erronous Warnings rather than tries to sort out some possible acceptable combinations that are not formally specified. Bob Ross Mentor Graphics "Mirmak, Michael" wrote: > > In Friday's IBIS Forum, I took an AR to examine how the parser treats > IBIS files where all the min/max parameters are set to NA (rather than > just the min/max V-I curves). Recall that BUG54 was filed in order to > correct the parser's treatment of models missing a [Pullup] section and > max/min V-I curves. The parser currently shows warnings regarding the > inability of such a model to drive the buffer delay test load through > the specified Vmeas point. > > The parser continues to give errors on the missing max/min V-I curves, > regardless of whether ramps, c_comp or voltage range min/max values > are present or absent. I have enclosed an additional example below. > > Therefore, we may conclude that the parser is only looking for V-I curves > in the min & max columns (for models without a [Pullup] section) to use > in determining whether the model can satisfy the buffer delay voltage > requirements. > > To decide how to resolve BUG54, we need to decide how the parser should > treat the keyword "NA" for this case. The spec unfortunately allows two > interpretations of "NA," according to the two rules below: > > Rule 1) "NA" means "no data" -- no assumption is to be made as to > the operation of the modeled device in those columns under those > conditions. This is the intent behind using NA to entirely replace > a column of V-I, t-V, ramp, c_comp or operating condition data. > > Rule 2) "NA" means "no explicit data" -- data is not given for > this particular condition in this particular column, but the state > of the device at this point is to be inferred from the surrounding > context by the sim tool. This is the normal usage of NA, when > mixed into a column of V-I or t-V data. This is also the reason > behind prohibiting the use of NA as a starting or ending point in > a column of data. > > Currently, the parser checks V-I curves using Rule 2 above for models > where partial data is available in all three columns. Rule 1 is used > for most models where NA completely replaces V-I data in a min or max > column. > > BUG54 was filed because the parser incorrectly applies Rule 2 for models > where the keyword [Pullup] is missing and entire V-I columns are > replaced by NA. For any other case where an entire column is missing, > Rule 1 is the only rule applied. > > So, to "fix" BUG54, I would suggest simply eliminating the warning > messages and applying Rule 1 to all models without a [Pullup] section > and without min/max V-I curves. This makes the parser self-consistent > and also gives sim tool vendors the same flexibility about the treatment > of NA as they currently have. No additional cases or interpretation > would be required. > > Any suggestions or advice? I will incorporate any consensus here into a > revised BUG54, which I will distribute for posting a week before the next > IBIS meeting (March 30). > > Thanks! > > - Michael Mirmak, Intel Corp. > > |*********************************************************************** > | > [IBIS Ver] 3.2 > [File Name] bug54a.ibs > [File Rev] 0.0a > [Date] 05-March-2001 > [Source] File created from specification > [Notes] Using the IBISCHK3 v3.2.5 & v3.2.6 parsers, the > following file will show two misleading warnings > related to the buffer delay fixture. > | > [Disclaimer] > (C) Copyright 2001 Intel Corp. > All rights reserved > This model is for demonstration purposes only, > | > [Component] GENERIC_IBIS > [Manufacturer] Intel Corp. > | > [Package] > | typ min max > R_pkg 6.0mO NA NA > L_pkg 5.0nH NA NA > C_pkg 1.0pF NA NA > | > | > [Pin] signal_name model_name R_pin L_pin C_pin > 1 TestSignal1 TestModel1 > | > |************************************************************************ > | > [Model] TestModel1 > Model_type I/O_open_sink > |Model_type I/O > Polarity Non-Inverting > Enable Active-Low > | > Vinl = 800mV > Vinh = 2.0V > | > Cref = 0F > Rref = 25ohms > Vref = 5.0V > Vmeas = 2.5V > | > C_comp 5.00pF NA NA > | > [Temperature Range] 27.00 NA NA > [Voltage Range] 5.0V NA NA > | > |[Pullup] > || voltage I(typ) I(min) I(max) > || > | -5.0000 0.0m NA NA > | -4.0000 0.0m NA NA > | 0.0000 0.0m NA NA > | 5.0000 0.0m NA NA > | 10.0000 0.0m NA NA > | > | > [Pulldown] > | voltage I(typ) I(min) I(max) > | > -5.0000 -40.0m NA NA > -4.0000 -39.0m NA NA > 0.0000 0.0m NA NA > 5.0000 200m NA NA > 10.0000 400m NA NA > | > | > [GND Clamp] > | voltage I(typ) I(min) I(max) > | > -5.0000 -3900.0mA NA NA > -0.7000 -80.0m NA NA > -0.6000 -22.0m NA NA > -0.5000 -2.4m NA NA > -0.4000 0.0A NA NA > 5.0000 0.0A NA NA > | > [Power Clamp] > | voltage I(typ) I(min) I(max) > | > -5.0000 4450.00m NA NA > -0.7000 95.0m NA NA > -0.6000 23.0m NA NA > -0.5000 2.4m NA NA > -0.4000 0.0m NA NA > 0.0000 0.0m NA NA > | > [Ramp] > |variable typ min max > dV/dt_r 2.20/1.06n NA NA > dV/dt_f 2.46/1.21n NA NA > R_load = 300ohms > | > | > |************************************************************************ > [End] From owner-ibis Thu Mar 8 18:21:32 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f292LV115744; Thu, 8 Mar 2001 18:21:32 -0800 (PST) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id SAA06643; Thu, 8 Mar 2001 18:21:38 -0800 (PST) Received: from mentor.com (bob.wv.mentorg.com [147.34.83.63]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id FW9BGY1Q; Thu, 8 Mar 2001 18:21:37 -0800 Sender: bobr@relay1.mentorg.com Message-ID: <3AA83E31.6FAF545E@mentor.com> Date: Thu, 08 Mar 2001 18:21:37 -0800 From: Bob Ross X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com Subject: EUROPEAN IBIS SUMMIT AGENDA 3/16/01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit To All: Here is the Agenda for the European IBIS Summit Meeting . It has some updated titles and slight changes in the presentation order. If you plan to attend and have not yet signed up, please let me know. We are looking forward to a productive meeting. Bob Ross Mentor Graphics bob_ross@mentor.com EUROPEAN IBIS SUMMIT MEETING Astron Hotel/Neue Messe Eggenfeldener Strasse 100, Munich Germany MARCH 16, 2001 8:30 REFRESHMENTS 9:00 INTRODUCTIONS AND PROGRAM Bob Ross, Mentor Graphics, USA 9:30 Experiences with and Tips for IBIS Models Eckhard Lenski, Siemens AG, Germany 10:00 Extraction of Key IBIS Parameters for Easier Model Selection John Berrie, Zuken, England and Michael Schaeder, Zuken Germany 10:30 BREAK 10:45 DOGEN, A Siemens Internal Model Tool, Extensions 1999 - 2001 Hans Pichlmaier, Siemens AG, Germany 11:15 LVDS Modeling Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt 12:00 LUNCH 13:00 SSTL-2 Modeling Experiences Bernhard Unger, Siemens AG, Germany 13:30 CAN (Controller Area Network) Bus Modeling Manfred Maurer, Siemens AG, Germany 14:00 Parasitic IC Emission Modeling Etienne Sicard, National Institute of Applied Science, France 14:30 EMC Models Christian Marot, Siemens, France 14:45 EMC Standardization Progress Jean Claude Perrin, Texas Instruments, France 15:00 BREAK 15:15 Modelling of Ground-Noise for Circuits with Short-Channel Transistors Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration, Germany 15:45 An Electromagnetic Emission Model for Integrated Circuits Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, Germany 16:15 Points of View for High Frequency IBIS Models Gerald Bannert, Siemens AG, Germany 16:30 IBIS-X and the IBIS Macro Language Stephen Peters and Arpad Muranyi, Intel, USA 16:55 CONCLUDING ITEMS Bob Ross, Mentor Graphics, USA 17:00 END From owner-ibis Fri Mar 9 06:43:04 2001 Received: from showboat.teradyne.com (showboat.teradyne.com [198.51.251.10]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f29Eh2120000; Fri, 9 Mar 2001 06:43:03 -0800 (PST) Received: from chorus.teradyne.com (chorus.teradyne.com [131.101.1.195]) by showboat.teradyne.com (8.8.8+Sun/8.8.8) with ESMTP id JAA22557; Fri, 9 Mar 2001 09:43:12 -0500 (EST) From: owner-si-list@silab.eng.sun.com Received: from jaypeak.corp.teradyne.com (jaypeak.corp.teradyne.com [131.101.17.23]) by chorus.teradyne.com (8.8.8+Sun/8.7.1) with ESMTP id JAA07370; Fri, 9 Mar 2001 09:43:11 -0500 (EST) Received: from chorus.teradyne.com ([131.101.1.195]) by madriver.corp.teradyne.com (Lotus Domino Release 5.0.4a) with ESMTP id 2001030821350999:97611 ; Thu, 8 Mar 2001 21:35:09 -0500 Received: from kiki.icd.teradyne.com (kiki.icd.teradyne.com [131.101.10.126]) by chorus.teradyne.com (8.8.8+Sun/8.7.1) with ESMTP id VAA13441 for ; Thu, 8 Mar 2001 21:36:33 -0500 (EST) Received: from chorus.teradyne.com (chorus.teradyne.com [131.101.1.195]) by kiki.icd.teradyne.com (8.9.3+Sun/8.9.3) with ESMTP id VAA19326 for ; Thu, 8 Mar 2001 21:36:33 -0500 (EST) Received: from showboat.teradyne.com (showboat.teradyne.com [198.51.251.10]) by chorus.teradyne.com (8.8.8+Sun/8.7.1) with ESMTP id VAA13435 for ; Thu, 8 Mar 2001 21:36:32 -0500 (EST) Received: from mercury.Sun.COM (mercury.Sun.COM [192.9.25.1]) by showboat.teradyne.com (8.8.8+Sun/8.8.8) with ESMTP id VAA12330 for ; Thu, 8 Mar 2001 21:36:32 -0500 (EST) Received: from engmail2.Eng.Sun.COM ([129.146.1.25]) by mercury.Sun.COM (8.9.3+Sun/8.9.3) with ESMTP id SAA07635; Thu, 8 Mar 2001 18:35:09 -0800 (PST) Received: from silab.eng.sun.com (silab.Eng.Sun.COM [129.146.121.121]) by engmail2.Eng.Sun.COM (8.9.3+Sun/8.9.3/ENSMAIL,v2.1p1) with SMTP id SAA07196; Thu, 8 Mar 2001 18:35:02 -0800 (PST) Received: by silab.eng.sun.com (SMI-8.6/SMI-SVR4) id SAA08848; Thu, 8 Mar 2001 18:22:09 -0800 Received: from engmail1.Eng.Sun.COM by silab.eng.sun.com (SMI-8.6/SMI-SVR4) id SAA08844; Thu, 8 Mar 2001 18:22:03 -0800 Received: from patan.sun.com (patan.Central.Sun.COM [129.147.5.43]) by engmail1.Eng.Sun.COM (8.9.3+Sun/8.9.3/ENSMAIL,v2.1p1) with ESMTP id SAA05123 for ; Thu, 8 Mar 2001 18:21:47 -0800 (PST) Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by patan.sun.com (8.9.3+Sun/8.9.3) with ESMTP id SAA10555 for ; Thu, 8 Mar 2001 18:21:46 -0800 (PST) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id SAA06643; Thu, 8 Mar 2001 18:21:38 -0800 (PST) Received: from mentor.com (bob.wv.mentorg.com [147.34.83.63]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id FW9BGY1Q; Thu, 8 Mar 2001 18:21:37 -0800 Message-ID: <3AA83E31.6FAF545E@mentor.com> X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.5.1 sun4u) MIME-Version: 1.0 Subject: [SI-LIST] : EUROPEAN IBIS SUMMIT AGENDA 3/16/01 Reply-To: Bob Ross X-MIMETrack: Itemize by SMTP Server on MadRiver/Bos/Teradyne(Release 5.0.4a |July 24, 2000) at 03/08/2001 09:35:10 PM, MIME-CD by Router on Aspen/Bos/Teradyne(Release 5.0.6a |January 17, 2001) at 03/08/2001 09:35:18 PM, MIME-CD complete at 03/08/2001 09:35:18 PM, Serialize by Router on JayPeak/Teradyne(Release 5.0.4a |July 24, 2000) at 03/09/2001 09:41:33 AM To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com Sender: charles_bishop@notes.teradyne.com Date: Fri, 9 Mar 2001 09:41:53 -0500 Content-type: text/plain; charset=us-ascii To All: Here is the Agenda for the European IBIS Summit Meeting . It has some updated titles and slight changes in the presentation order. If you plan to attend and have not yet signed up, please let me know. We are looking forward to a productive meeting. Bob Ross Mentor Graphics bob_ross@mentor.com EUROPEAN IBIS SUMMIT MEETING Astron Hotel/Neue Messe Eggenfeldener Strasse 100, Munich Germany MARCH 16, 2001 8:30 REFRESHMENTS 9:00 INTRODUCTIONS AND PROGRAM Bob Ross, Mentor Graphics, USA 9:30 Experiences with and Tips for IBIS Models Eckhard Lenski, Siemens AG, Germany 10:00 Extraction of Key IBIS Parameters for Easier Model Selection John Berrie, Zuken, England and Michael Schaeder, Zuken Germany 10:30 BREAK 10:45 DOGEN, A Siemens Internal Model Tool, Extensions 1999 - 2001 Hans Pichlmaier, Siemens AG, Germany 11:15 LVDS Modeling Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt 12:00 LUNCH 13:00 SSTL-2 Modeling Experiences Bernhard Unger, Siemens AG, Germany 13:30 CAN (Controller Area Network) Bus Modeling Manfred Maurer, Siemens AG, Germany 14:00 Parasitic IC Emission Modeling Etienne Sicard, National Institute of Applied Science, France 14:30 EMC Models Christian Marot, Siemens, France 14:45 EMC Standardization Progress Jean Claude Perrin, Texas Instruments, France 15:00 BREAK 15:15 Modelling of Ground-Noise for Circuits with Short-Channel Transistors Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration, Germany 15:45 An Electromagnetic Emission Model for Integrated Circuits Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, Germany 16:15 Points of View for High Frequency IBIS Models Gerald Bannert, Siemens AG, Germany 16:30 IBIS-X and the IBIS Macro Language Stephen Peters and Arpad Muranyi, Intel, USA 16:55 CONCLUDING ITEMS Bob Ross, Mentor Graphics, USA 17:00 END **** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu **** From owner-ibis Fri Mar 9 11:03:22 2001 Received: from ASATUS_EXCH1.ASAT.COM ([209.1.119.15]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f29J3K123637 for ; Fri, 9 Mar 2001 11:03:21 -0800 (PST) Received: by ASATUS_EXCH1 with Internet Mail Service (5.5.2653.19) id ; Fri, 9 Mar 2001 11:02:00 -0800 Message-ID: <7B38E704DFCAD311A8A9009027855FBE01559B28@ASATUS_EXCH1> From: Pat Diao To: "'ibis@eda.org'" Subject: IBIS Date: Fri, 9 Mar 2001 11:01:59 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" I am working to install a s2ibis in my company. Could you give me any info on if any s2ibis for WinNT or Win2000 is available? The only one I find on your wedsite is for Win95. Thanks a lot. Pat Diao __________________________________________________ Pat Diao, Ph.D. Sr. Staff Engineer Electronic packaging, Thermal/Electrical ASAT Inc. 46335 Landing Parkway Fremont, CA 94538 phone: 510-249-1227 fax: 510-249-9105 e-mail: pat_diao@asat.com __________________________________________________ From owner-ibis Fri Mar 9 11:25:44 2001 Received: from pop.nwlink.com (pop.nwlink.com [209.20.130.39]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f29JPg123787 for ; Fri, 9 Mar 2001 11:25:43 -0800 (PST) Received: from ip210.c246.blk1.bel.nwlink.com (ip210.c246.blk1.bel.nwlink.com [209.20.246.210]) by pop.nwlink.com (8.9.3/8.9.3) with SMTP id LAA14108; Fri, 9 Mar 2001 11:25:55 -0800 (PST) Received: from mail.hyperlynx.com by ip210.c246.blk1.bel.nwlink.com via smtpd (for pop.nwlink.com [209.20.130.39]) with SMTP; 9 Mar 2001 19:25:55 UT Received: from [192.168.149.1] (hlgw.hyperlynx.com [192.168.149.1]) by mail (8.9.3/8.9.3/SuSE Linux 8.9.3-0.1) with SMTP id LAA25669; Fri, 9 Mar 2001 11:25:51 -0800 Message-ID: <001101c0a8ce$ca135d90$9594a8c0@hyperlynx.com> From: "Matthew Flora" To: "Pat Diao" , Received: from no.name.available by [192.168.149.1] via smtpd (for mail.hyperlynx.com [192.168.149.2]) with SMTP; 9 Mar 2001 19:25:50 UT References: <7B38E704DFCAD311A8A9009027855FBE01559B28@ASATUS_EXCH1> Subject: Re: IBIS Date: Fri, 9 Mar 2001 11:26:02 -0800 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Dear Pat Diao, The last link to SPICE-to-IBIS on the Web page http://www.eigroup.org/ibis/tools.htm Should work nicely. Best regards, Matthew Flora ----- Original Message ----- From: "Pat Diao" To: Sent: Friday, March 09, 2001 11:01 AM Subject: IBIS > > I am working to install a s2ibis in my company. Could you give me any info > on if any s2ibis for WinNT or Win2000 is available? The only one I find on > your wedsite is for Win95. > > Thanks a lot. > > > Pat Diao > > > > > > __________________________________________________ > Pat Diao, Ph.D. > Sr. Staff Engineer > Electronic packaging, Thermal/Electrical > ASAT Inc. > 46335 Landing Parkway > Fremont, CA 94538 > phone: 510-249-1227 > fax: 510-249-9105 > e-mail: pat_diao@asat.com > __________________________________________________ > > > From owner-ibis Mon Mar 12 14:51:59 2001 Received: from e3.ny.us.ibm.com (e3.ny.us.ibm.com [32.97.182.103]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2CMpv110261; Mon, 12 Mar 2001 14:51:58 -0800 (PST) Received: from northrelay02.pok.ibm.com (northrelay02.pok.ibm.com [9.117.200.22]) by e3.ny.us.ibm.com (8.9.3/8.9.3) with ESMTP id RAA92190; Mon, 12 Mar 2001 17:50:59 -0500 From: hasf@us.ibm.com Received: from d01ml221.pok.ibm.com (d01ml221.pok.ibm.com [9.117.200.51]) by northrelay02.pok.ibm.com (8.8.8m3/NCO v4.95) with ESMTP id RAA24370; Mon, 12 Mar 2001 17:46:41 -0500 Importance: Normal To: ibis@eda.org, ibis-request@eda.org X-Mailer: Lotus Notes Release 5.0.5 September 22, 2000 Message-ID: Date: Mon, 12 Mar 2001 17:50:45 -0500 X-MIMETrack: Serialize by Router on D01ML221/01/M/IBM(Release 5.0.6a |January 17, 2001) at 03/12/2001 05:50:49 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii This note is a request to become a member of the IBIS Open Forum Reflector as well as the IBIS Users' Group Reflector. Please let me know what is required of me to be added to the distribution list. Regards, Hirut Asfaw Hirut Asfaw ASIC I/O Developement IBM Microelectronics Division External: (802) 769-0652 T/L: 6-0652 hasf@us.ibm.com From owner-ibis Fri Mar 16 11:36:06 2001 Received: from e1.ny.us.ibm.com (e1.ny.us.ibm.com [32.97.182.101]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2GJa1522932 for ; Fri, 16 Mar 2001 11:36:05 -0800 (PST) Received: from northrelay02.pok.ibm.com (northrelay02.pok.ibm.com [9.117.200.22]) by e1.ny.us.ibm.com (8.9.3/8.9.3) with ESMTP id OAA85330 for ; Fri, 16 Mar 2001 14:31:57 -0500 Received: from d27ml104.rchland.ibm.com (d27ml104.rchland.ibm.com [9.5.39.61]) by northrelay02.pok.ibm.com (8.8.8m3/NCO v4.95) with ESMTP id OAA20340 for ; Fri, 16 Mar 2001 14:28:57 -0500 Importance: Normal Subject: BIRD 70 To: ibis@vhdl.org X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000 Message-ID: From: "Gregory R Edlund" Date: Fri, 16 Mar 2001 13:34:56 -0600 X-MIMETrack: Serialize by Router on d27ml104/27/M/IBM(Release 5.0.6a |January 17, 2001) at 03/16/2001 01:34:57 PM MIME-Version: 1.0 Content-type: text/plain; charset=us-ascii Hi Everyone, BIRD 69.1 has evolved into BIRD 70. The main change is making one test load available to ALL models through a new keyword, [Test Load], and a new subparameter under [Rising Waveform] and [Falling Waveform], Golden_test_load. Thanks to Al Davis and Bob Ross for their input. Please see the section "ANALYSIS PATH" for the details. I am very interested to know if this BIRD is "obvious to the casual observer" or "obscure to anyone not involved!" Greg p.s. A similar concept could be used for expanded standard loads, e.g. PCI, etc. ******************************************************************************* ******************************************************************************* BIRD ID#: 70 ISSUE TITLE: Golden Waveforms REQUESTOR: Greg Edlund, IBM DATE SUBMITTED: March 16, 2000 DATE REVISED: DATE ACCEPTED BY IBIS OPEN FORUM: Pending ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: Golden Waveforms are a set of SPICE waveforms simulated using known ideal test loads. They are useful in verifying the accuracy of behavioral simulation results for any given simulator. They are not the same thing as the traditional VT tables recommended in the "IBIS Cookbook." The "I/O Buffer Accuracy Handbook" recommends a set of ideal test loads for classical push-pull and open-drain drivers. There is currently a problem with including Golden Waveforms in an IBIS datasheet: the simulator tries to use these waveforms to construct its stimulus waveform, and erroneous simulations result. This BIRD proposes a new syntactical construct to tell the simulator that a waveform is a Golden Waveform. The simulator may then choose to ignore the data or (better yet) run a set of simulations using the network and circuit parameters provided and report the correlation between the simulation results and the Golden Waveforms. The mechanism for describing a Golden Waveform involves a new subparameter under the [Rising Waveform] and [Falling Waveform] keywords and a new keyword, [Test Load], whose scope is global and whose subparameters are accessible by all models. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: |============================================================================= | Keywords: [Rising Waveform], [Falling Waveform] | Required: No | Description: Describes the shape of the rising and falling edge waveforms | of a driver. | Sub-Params: R_fixture, V_fixture, V_fixture_min, V_fixture_max, C_fixture, |* L_fixture, R_dut, L_dut, C_dut, Golden_test_load . . . | All tables assume that the die capacitance is included. | Potential numerical problems associated with processing the | data using the effective C_comp for effective die capacitance | may be handled differently among simulators. | |* A model developer may use the Golden_test_load subparameter |* to document Golden Waveforms whose purpose is to facilitate |* the correlation of SPICE and behavioral simulations. The |* value of Golden_test_load must be a valid [Test Load] name. |* Golden_test_load is mutually exclusive of all other |* subparameters and nullifies them if used. The process, |* temperature, and voltage conditions under which the waveforms |* are generated must be identical to those used to generate |* the VI and VT tables. The Golden Waveforms must be generated |* using unpackaged driver and receiver models. The simulator |* must not use the Golden Waveform tables in the construction |* of its internal stimulus function. | |----------------------------------------------------------------------------- . . . | | Example Golden Waveforms: | [Rising Waveform] Golden_test_load = Load1 | Time V(typ) V(min) V(max) 0.0000s 25.2100mV 15.2200mV 43.5700mV 0.2000ns 2.3325mV -8.5090mV 23.4150mV 0.4000ns 0.1484V 15.9375mV 0.3944V 0.6000ns 0.7799V 0.2673V 1.3400V 0.8000ns 1.2960V 0.6042V 1.9490V 1.0000ns 1.6603V 0.9256V 2.4233V 1.2000ns 1.9460V 1.2050V 2.8130V 1.4000ns 2.1285V 1.3725V 3.0095V 1.6000ns 2.3415V 1.5560V 3.1265V 1.8000ns 2.5135V 1.7015V 3.1600V 2.0000ns 2.6460V 1.8085V 3.1695V | ... 10.0000ns 2.7780V 2.3600V 3.1670V | [Falling Waveform] Golden_test_load = Load1 | Time V(typ) V(min) V(max) 0.0000s 5.0000V 4.5000V 5.5000V 0.2000ns 4.7470V 4.4695V 4.8815V 0.4000ns 3.9030V 4.0955V 3.5355V 0.6000ns 2.7313V 3.4533V 1.7770V 0.8000ns 1.8150V 2.8570V 0.8629V 1.0000ns 1.1697V 2.3270V 0.5364V 1.2000ns 0.7539V 1.8470V 0.4524V 1.4000ns 0.5905V 1.5430V 0.4368V 1.6000ns 0.4923V 1.2290V 0.4266V 1.8000ns 0.4639V 0.9906V 0.4207V 2.0000ns 0.4489V 0.8349V 0.4169V | ... 10.0000ns 0.3950V 0.4935V 0.3841V | . . . |============================================================================= | Keywords: [Test Load] | Required: No | Description: Defines a generic test load network and its associated | electrical parameters for reference by Golden Waveforms | defined in [Rising Waveform] and [Falling Waveform] tables. | The Golden Waveform tables access a given [Test Load] | by the value of the Golden_test_load subparameter under the | [Rising Waveform] and [Falling Waveform] keywords. | Sub-Params: C1_near, Rs_near, Ls_near, C2_near, Rp1_near, Rp2_near, | Td, Zo, Rp1_far, Rp2_far, C2_far, Ls_far, Rs_far, C1_far, | R_diff, V_term1, V_term2, Receiver_model_name, Test_point, | Tline_present | Usage Rules: The subparameters specify the electrical parameters | associated with a fixed generic test load. The diagram | below describes the generic test load schematically. | | V_term1 | o-----------o | | | | \ \ receiver_model_name | ______ / / ______ | | | NEAR Rp1_near \ \ Rp1_far FAR | | | | |\ | / / | |\ | | | | \ | Rs_near Ls_near | _____ | Ls_far Rs_far | | \ | | | | >-|---o--/\/\--@@@@--o----o--O_____)--o----o--@@@@--/\/\--o---|-| > | | | | / | | | | Td | | | | | / | | | |/ | | C1_near | \ Zo \ | C2_far | | |/ | | |______| === === / / === === |______| | | C2_near | \ \ | C1_far | | | | / / | | | | | | V_term2 | | | | o--------------o o-----------o o--------------o | | Rp2_near Rp2_far | | GND GND | | | R_diff is not shown in the schematic but would be connected | between the true and complement far end nodes in the case | of a differential driver. In this case, the true and | complement nets will be identical as defined by the other | subparameters. | | V_term1 defines the termination voltage for parallel | termination resistors Rp1_near and Rp1_far. This voltage | is not related to the [voltage range] keyword. | V_term2 defines the termination voltage for parallel | termination resistors Rp2_near and Rp2_far. | | Receiver_model_name is optional and indicates which, if any, | receiver is connected to the far end node. If not used, the | network defaults to no receiver. | | Test_point is required and defines the node in the above | schematic at which the Golden Waveform is measured. It must | have the value near or far. | | Tline_present is required and indicates whether or not | the transmission line exists in the network. It must have | the value yes or no. If no, the transmission line is | replaced by a short circuit. This prevents the user from | having to specify a very small delay value when no | transmission is present, which would result in the simulator | taking excessively small time steps. | | The following parameters are optional and default to the | values specified in table below: | | C1_near = 1f | Rs_near = 1M | Ls_near = 1p | C2_near = 1f | Rp1_near = 1M | Rp2_near = 1M | Td = 1ns | Zo = 50 | Rp1_far = 1M | Rp2_far = 1M | C2_far = 1f | Ls_far = 1p | Rs_far = 1M | C1_far = 1f | R_diff = 1M | V_term1 = 1 | V_term2 = 0 | |----------------------------------------------------------------------------- | [Test Load] Load1 C1_near = 1p Rs_near = 10 Ls_near = 1n C2_near = 1p Rp1_near = 100 Rp2_near = 100 Td = 1ns Zo = 50 Rp1_far = 100 Rp2_far = 100 C2_far = 1p Ls_far = 1n Rs_far = 10 C1_far = 1p R_diff = 100 Receiver_model_name Input1 Test_point far Tline_present yes | variable typ min max Vterm1 1.5 1.4 1.6 Vterm2 0.0 0.0 0.0 | | Example Transmission Line and Receiver test load from "I/O Buffer Accuracy | Handbook," section 3.4.4. | [Test Load] Tline_rcv Td = 1n Zo = 50 Receiver_model_name Input1 Test_point far |----------------------------------------------------------------------------- ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Please refer to BIRD 69.1 for history. BIRD 70 came about a result of an attempt to make BIRD 69.1 upwardly compatible with IBIS-X. BIRD 70 is actually more compact and efficient because it allows multiple models to access the same [Test Load]. Recommendations came from Bob Ross, Al Davis, and the IBIS Open Forum, 3/2/01. Changes between BIRD 69.1 and BIRD 70: 1. Scope of the "generic test load" is now global rather than being local to a particular model. This is a big improvement. 2. Added one subparameter, Golden_test_load, to [Rising Waveform], [Falling Waveform] keywords. Added text to describe new the subparameter. The Golden_test_load subparameter calls a [Test Load]. 3. Exported all the other code to the new [Test Load] keyword. 4. Removed T_ref subparameter. To do timing correlation, the simulator can pick a point on the 50 Ohm VT waveform as its "SPICE reference point" and then simulate both the 50 Ohm load and the Golden_test_load to calculate a time difference. 5. Removed Pkg_pin parameter. It is too complicated. The user can model a simple single-pin lumped circuit using the parameters supplied. 6. Added Tline_present subparameter. If not used, the Tline should be removed from the simulation rather than assigned a very small delay value. This prevents the simulator from taking ridiculously small time steps. 7. Replaced V_termxxx with tables similar to the dV/dt_x subparameters. This makes the BIRD more economical. 8. Got rid of the paragraph that read, "Using the Golden Waveform tables..." This seemed to be redundant. 9. Specified which parameters are optional and which are required. NOTE: BIRD70 adds approximately 130 extra lines to IBIS. Of this, 25 line are actual code and the remaining 105 are comments. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: See BIRD 69.1. ******************************************************************************* From owner-ibis Wed Mar 21 08:52:16 2001 Received: from mercury.lss.emc.com (mercury.eng.emc.com [168.159.40.77]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2LGqD503658 for ; Wed, 21 Mar 2001 08:52:15 -0800 (PST) Received: by mercury.eng.emc.com with Internet Mail Service (5.5.2653.19) id ; Wed, 21 Mar 2001 11:48:58 -0500 Message-ID: From: "ruston, matt" To: "'ibis@eda.org'" Subject: subscribe Date: Wed, 21 Mar 2001 11:48:55 -0500 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2653.19) Content-Type: text/plain; charset="iso-8859-1" From owner-ibis Thu Mar 22 18:31:07 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2N2V4513172 for ; Thu, 22 Mar 2001 18:31:05 -0800 (PST) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id VAA11393 for ; Thu, 22 Mar 2001 21:28:06 -0500 (EST) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id VAA23043 for ; Thu, 22 Mar 2001 21:28:04 -0500 (EST) Received: from f22.innoveda.com (f22.camarillo.innoveda.com [139.181.194.48]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id SAA04185 for ; Thu, 22 Mar 2001 18:28:02 -0800 (PST) Received: by f22.innoveda.com (SMI-8.6/SMI-SVR4) id SAA14621; Thu, 22 Mar 2001 18:28:01 -0800 Date: Thu, 22 Mar 2001 18:28:01 -0800 From: guy@camarillo.innoveda.com (Guy de Burgh) Message-Id: <200103230228.SAA14621@f22.innoveda.com> To: ibis@eda.org Subject: EIA IBIS European IBIS Summit Meeting Minutes Date: 3/22/01 SUBJECT: 3/16/01 EIA IBIS European IBIS Summit Meeting Minutes VOTING MEMBERS AND 2001 PARTICIPANTS LIST: 3Com (& CommWorks) Roy Leventhal Agilent (Mark Chang) Ansoft Corporation (Eric Bracken) Apple Computer John Figueroa Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Balistreri Avanti (Chen Hongyu) Brocade Communications Robert Badal Cadence Design Ian Dodd, Patrick Dos Santos*, Heiko Dudek* Cisco Systems Syed Huq, Lungfu Chen Compaq Peter LaFlamme, Ron Bellomio, Quang Dam Cypress (Rajesh Manapat) EMC Corporation Brian Arsenault, Jinhua Chen Fairchild Semiconductor Adam Tambone IBM Michael Cohen, Greg Edlund, Wes Martin, Yeon-Chang Hahm, Bill DeVey, Pravin Patel Innoveda (& HyperLynx) Guy de Burgh, John Angulo, Cary Mandel* Intel Corporation Stephen Peters, Arpad Muranyi*, Dave Lorang, Michael Mirmak, Qinglun Chen, Will Hobbs LSI Logic Larry Barnes Mentor Graphics Bob Ross*, Tom Dagostino*, Chris Reid, Mike Donnelly, Hazem Hegazy, Tony Dunbar, Griff Derryberry, Dan Lake, Sherif Hammad*, Mohammed Korany*, Weston Beal, Chris Swaim*, Ali Samii*, Eric Ronger*, Karine Loudet* Micron Technology Randy Wolff, Yong Phan Mitsubishi (Tam (Tom) Cao) Molex Incorporated Gus Panella, Brian O'Malley Motorola (Ron Werner) National Semiconductor Milt Schwartz Nortel Networks Calvin Trowell North East Systems Associates Edward Sayre Philips Semiconductor Zack Ciccone, Rob Mataheroe* Quantic EMC (Mike Ventham) Robinson-Nugent, Inc. (Alexander Barr) Siemens (& Automotive) AG Bernhard Unger*, Helmut Katzier, Katja Koller*, Wolfram Meyer*, Eckhard Lenski*, Gerald Bannert*, Burkhard Muller*, Christian Marot*, Manfred Maurer*, Amir Motamedi*, Hans Pichlmaier* Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz SiQual Scott McMorrow, Rob Hinz, Bernard Voss, Chris Brewster Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar, Jean Claude Perrin* Time Domain Analysis Systems Dima Smolyansky, Steve Corey Tyco Electronics (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) John Berrie* OTHER PARTICIPANTS IN 2001: Actel Corporation Silvia Montoya Acuson Kim Helliwell AMCC Jeff Smith ASIS Ltd David Wright BMW Friedrich Hasinger* Cereva Networks Bob Haller EADS Airbus Industry Claude Huet* (Aerospatiale) EFM Ekkehard Miersch*, Horle Raines* EIA Cecilia Fleming FCI Sercu Stefaan Foundary Networks Bertram Chan Framatom Conectors Danny Morlion Fraunhofer Institute Mariusz Faferko*, Peter Kralicek* Reliability and Integration Fujitsu Ltd Tadashi Arai, Takeshi Murakami Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt* Huawei Technologies Rachild Chen Hyundai Electronics Jongho Kang Infineon Technologies Christian Sporrer* Intrinsix Corporation Steven Chin National Institute of Applied Etienne Sicard* Science (INSA) Nokia Tapani von Ravner, Mika Castren*, Janne Uusitalo* Oak Technology Darmin Jin Plexus Technology Group Joseph Socha Sintecs Hans Klos* STMicroelectronics Peter Hirt, Fabrice Boissieres* Sun Adrian Udenze* Xilinx Susan Wu Independent, Consultant Al Davis In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode March 30, 2001 (916) 356-9200 2-524673 6244264 April 20, 2001 (916) 356-9200 2-524674 3881934 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit Meeting held all day at the Astron Hotel/Neue Messe, Munich Germany. About 39 people from 19 companies and institutes attended. The notes below capture some of the meeting content and discussions. The meeting presentations and other material will be uploaded at: http://www.eda.org/pub/ibis/summits/mar01/ Bob Ross opened the meeting by having everyone introduce themselves. The EDA, user and semiconductor were well represented. Bob thanked the co-sponsors for the meeting, Cadence, Innoveda, Mentor Graphics, and Zuken for sharing the meeting expenses. Bob also thanked Karine Loudet of Mentor Graphics for helping in the meeting logistics, collecting registrations, copying presentations, creating badges, and producing the beautiful European IBIS Summit Meeting poster. As a business item, Bob stated that Apple Computer is now a full EIA IBIS Open Forum member and is now listed in the Voting Members portion of the Participants list. Bob gave a brief overview of the meeting agenda: Current IBIS Model Development and Validation Specific Bus Technology Problems and Experiences EMI/EMC Modeling Issues High-Speed Issues Future IBIS-X Progress and Discussion Closing Issues and Discussions EXPERIENCES WITH AND TIPS FOR IBIS MODELS Eckhard Lenski, Siemens AG, Germany Eckhard Lenski shared his experiences regarding the problems that he has seen with IBIS models. He currently supports about 1500 IBIS I/O models for internal Siemens usage world-wide. Models come from all sources including measurement, Spice extraction, IBIS Web sites, and data books. Newer technologies (LVDS, CAN, PCML, PECL etc.) provide additional challenges. Complete and consistent information is needed. Eckhard showed some typical concerns in models and some details that should be considered. The topics included the gap between ground and power clamps, unreasonable ramp voltage values, inconsistent ramp values, I-V and V-T data load line mismatch, double counting of clamps, incorrect V_fixture voltage information. Because Siemens provides models for different simulators, Eckhard shared some tips and experiences on model details. He showed how models referenced by the [Driver Schedule] keyword has pullup, pulldown and clamp table keywords that are located differently in non-IBIS formats (or visa versa). These details must be understood to provide correct translations. Eckhard also commented that differential buffers need the Vdiff parameter. When different Vmeas values exist for rising and falling edges (a situation that cannot be handled by the existing IBIS syntax), Eckhard suggests using the average value. He also showed how the timing test loads given by parallel resistors could be converted into the equivalent load required by the IBIS syntax. Eckhard spoke about package model details. He showed simulations differences between a model with cascaded lumped sections and with a single lumped stage. Eckhard also showed that different sized packages may actually use the same die and have different lengths to the pins. Semiconductor vendors often shrink the die in later versions of the chip. These details should be modeled correctly, with different package models for different component packages. Additional details were presented. Differential inputs can have termination resistors connected to a common voltage such as 1.2 V. Clamp tables can model this effect and also include any clamp diodes. Eckhard needs to create three separate models for timing test load variations for typ/min/max cases. Also, Eckhard commented on LVDS ramp model difficulties with 50 Ohms to Ground and to Vcc. A waveform model is required. The datasheet may give guidance regarding the number of model variations that the IBIS model needs. Different output strengths may be documented for output buffers, and different leakage currents may be documented for inputs. The IBIS model should be consistent with this information. The correct C_comp value is critical for DIMM models where a number of inputs are in parallel. Also input capacitance can have different values at different frequencies. A bad value can introduce delay errors. Often when the die is shrunk (for manufacturing yield improvement), the electrical characteristics change. A new model should be requested. Fabrice Boissieres commented that clamps also change with die shrinkage. Eckhard presented some future needs. He really wants different component keywords for different devices for the same family instead of a generic part. Finally, he listed quick (one-week) responses to questions to vendors, an electrical model checker, and EMI model parameters. He summarized that both IBIS-X and the new approved BIRDs are good. Complete IBIS Version 3.2 models are currently needed that have the relevant optional parameters, have two rising and two falling waveforms, have the over and undershoot parameters and better package model files (not just R_pkg, L_pkg, and C_pkg). When you see a pyramid top in a rain forest, you do not see the larger base underneath that is needed. Fabrice added that typ/min/max values for Vref are needed. EXTRACTION OF KEY IBIS PARAMETERS FOR EASIER MODEL SELECTION John Berrie, Zuken, England and Michael Schaeder, Zuken Germany John Berrie described some common problems he has seen when getting IBIS models from Web sites. Problems (observed more often in older models) include pins not even modeled or modeled incorrectly. Unique model names are needed for different types of buffers. The ibischk3 parser provides one level of testing and specific EDA tools can provide additional tests. However, a method to provide just basic file information is needed. John stated that Michael Schaeder is developing such a tool for giving basic information about the contents of the file containing IBIS models. This tool (still being improved) lists the number of pins (modeled and supply pins), model names and model types, and package model references, and model details. These details include the additional keywords and subparameters such as thresholds, timing test loads, voltage range, and static characteristics (such as inclusion of power and ground clamps). Also, output parameters include documenting the [Ramp] values and the [Rising Waveform] and [Falling Waveform] fixture resistance and voltage values. John showed samples of the output. Such a utility would provide a quick check of the contents of the file for the user to see that the information is complete and consistent. Normally such information is scattered throughout the file and is difficult to detect. Zuken is planning to donate this utility to the IBIS Open Forum for public use. This will assist in visual inspection and could be the basis for some additional automatic reality checking in the future. The utility, designated "ibsinf" (IBIS Information), is expected to be ready in several months. Bob Ross asked, and John responded that it will be supplied in Windows and in Unix (Sun Solaris and Hewlett Packard) formats. Gerald Bannert suggested that more checks are possible. DOGEN, A SIEMENS INTERNAL MODEL TOOL, EXTENSIONS 1999 - 2001 Hans Pichlmaier, Siemens AG, Germany Hans Pichlmaier gave an overview of DOGEN, an internal modeling tool he has been working on for several years. It does: Quad to IBIS, IBIS to Quad and Spice to IBIS .ebd Conversions IBIS Scaling of typ to min/max Checks of Quad and IBIS models Works standalone or within a BIOLIB library environment Supports the BIOLIB structure BIOLIB is IBIS+ with IC, passive and module data structures. ELAN provides layout data with the part numbers and passive components. These are used in as system to generate project tool libraries for Quad, ICX and Specctra based projects. The library generator gives local copies with EDA tool specific features. For example, four cases of models for signal integrity, minimum delay, maximum delay, and worst case crosstalk analysis are generated for Quad based projects. The extension made in the last two years consists of: Passive component models .ebd modules inside BIOLIB Evidence of usage in projects Complex packages inside BIOLIB Model Viewer for I-V and V-T tables Conversion of Altera and Xilinx FPGA files to IBIS Pinouts IBIS split and IBIS expand to make BIOLIB Elements from IBIS models Support of IBIS Version 3.2 Support of new Quad syntaxes for DIFFPIN and SERIESPIN Hans illustrated the passive part generation utility where internal part numbers, values, packages and tolerances can be input. The appropriate IBIS models are generated. He also showed the command line and resulting files for module generation within BIOLIB. The [Reference Designator Map] is used differently in BIOLIB than in IBIS to refer to actual part numbers instead of file names. ELAN keeps track of model usage by projects. Updates to models can be sent automatically to any site world-wide by e-mail. Hans stated that the data base will be extended for EMI analysis and power bus decoupling in the future. Arpad Muranyi asked about scaling, and Hans indicated that V-T and I-V typical data can be scaled independently for min and max columns. The V-T scaling is done in a manner that the starting and ending values are consistent with the adjusted I-V data. Adrian Udenze asked about the monotonic check on V-T tables. Overshoots and undershoots are clipped if less than 10 percent to be compatible with some EDA tools. Over or undershoots greater than 10 percent are suspicious and flagged as an error. Non-monotonic ledges during the ramp section is removed by straight line approximations. Tom Dagostino commented that this could lead to slower model transition times if the ledge were due to an internal package reflection. At the conclusion, Hans announced that he will lead the third annual Bavarian IBIS Summit climb in the Bavarian Alps on March 17, 2001. Everyone is invited. LVDS MODELING Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt Mohammed Korany provided new material from a similar presentation given at the DesignCon 2001 IBIS Summit Meeting on January 29, 2001. Mohammed started by introducing some LVDS basic terminology. The problem is how to extract the correct I-V tables when differential outputs are connected to internal differential termination resistors. Sometimes such a topology is not evident in encrypted models output models, and sometimes there is a equal current sourcing and sinking circuitry. Conventional techniques may cause unexpected DC shifts if the termination resistor is changed. Normally each pad and padn path is terminated by a single-ended resistor (usually 50 ohms) connected to a Vref value. Some original methods (Methods I - III) based on some early ideas all had DC shift mismatches for some loads. Proposal I used equal, but opposite sign delta voltages connected to the pad and padn pins and attached to a common Vms (mid swing voltage). The time response had correct DC values when the termination resistor was 50 ohms (same as the fixture value), but significant DC shift from Spice reference simulations when the termination resistor was 100 ohms. Proposal II overcame the DC shift problem by doing the DC sweeps by connecting equal resistors to pad and padn. The resistor value was swept to obtain the I-V tables. This proposal had overlaying waveforms for both the single-ended 50 and 100 ohm loads, and excellent correlation with a lossy differential transmission line interconnection. Proposal III was a new proposal that used sweeps to actually extract the value of the differential termination resistor. Two equal sweeps connected to the pad and padn sides of the internal differential resistor was used to extract the I-V tables values for each buffer while nulling out the effect of the differential terminator. This setup sparked some questions which were discussed and resolved off-line. Mohammed showed the schematic for the first set of sweeps for padn set to 0 V and 1 V respectively to extract the differential resistance value. The resulting LVDS differential model based on single-ended models and an [R Series] differential termination correlated very well to the same tests as Proposal II. Mohammed added that the C_comp value is important for such simulations. He showed that severe mismatched single-ended terminations (such as 150 ohms for 50 ohm lines), produce reflections. The input C_comp value impacts the shape and amplitude of the reflections and glitches. The correct value of C_comp can be estimated by such a setup by providing a value that produces the closest responses to a reference Spice simulation. Mohammed concluded that Proposals II and III produced the best results. The estimation of C_comp was very important. SSTL_2 MODELING EXPERIENCES Bernhard Unger, Siemens AG, Germany Bernhard Unger investigated simulations for one and two waveform based IBIS models for SSTL_2 (Stub Series Terminated Logic for 2.5V) Class 1 symmetrically single parallel terminated output load and series series resistor. The one waveform models (suggested by Bob Ross) used R_fixture = 50 ohms and V_fixture = 1.25 V. The two waveform models (suggested by Eckhard Lenski) used R_fixture = 50 ohms and V_fixture = 0 and 2.5 V. Spice (HSpice B-element) and IBIS model simulations were compared. Three loading conditions were checked: Case 1: Parallel terminated tr-line (Z0 = 50, Td = 1.5 nS); Rpara = 50 ohms, Vterm = 1.125 V; Cload = 2.5 pF Case 2: Unterminated tr-line (Z0 = 50, Td = 1.5 nS); Cload = 2.5 pF Case 3: Parallel and series terminated tr-line (Z0 = 50, Td = 1.5 nS); Rseries = 25 ohms; Rpara = 50 ohms, Vterm = 1.125 V; Cload = 2.5 pF Bernhard showed the overlaid simulations for these cases: Case 1 Case 2 Case 3 1 Waveform: Good Bad mismatch More mismatch 2 Waveforms: Slight mismatch Slight mismatch Slight mismatch The Case 2, 1 Waveform simulations had a strong dependence on the HSpice specific multiplier relationship of rwf/rfw. The default setting of 0.1 produced poor results, and the setting of 1.0 provided improved results. Bernhard checked the 1 Waveform results using an arbitrary multipler table constraint: Kpudr/f(t) + Kpdr/f(t) = 1 The 1 Waveform results were better, but a zoomed in view showed that the 2 Waveform simulations were still closer to the reference simulations. Bernhard concluded that there is a strong dependency on loading conditions and assumptions on multiplier relationships. He said that golden waveforms may be needed to check the tool dependent behavioral models and real world applications. Bob questioned why Case 2 was considered since that case SSTL-2 was typically used with parallel terminations. Bernhard responded that a specific customer had requested comparisons for Case 2 in order to save power. LUNCH The participants were treated to a delicious hot lunch. CAN BUS MODELING Manfred Maurer, Bernhard Unger, Siemens, Friedrich Hasinger, BMW Manfred Maurer described a project to develop models for automotive control units to support CAN (Controller Area Network) busses. CAN is a serial 2-wire differential bus concept introduced by BOSCH to interconnect microcontrollers, actuators, and sensors. Spice models were not available, so IBIS models were produced from measurement data. Manfred present the CAN characteristics, applications areas, and a circuit model. The network has bit rates up to 1 Mbit/sec and up to 40 m length, and supports at least 30 bus participants. It also can be used in other applications such as for medical equipment and systems. Busses are doublely terminated by 120 ohms at each end, and are wired using a 120 Ohm differential characteristic impedance interconnections per ISO/DIS 11898. The electrical operation for differential signals is not symmetrical. The CAN_H signal swings between 2.5 V and 3.5 V. The CAN_L signal swings between 1.5 V and 2.5 V. The Recessive state is when both sides are at 2.5 V (0 V differential), and the Dominant state is when the CAN_H and CAN_L differential voltage is 2.0 V. An internal termination provides a 2.5 V reference. Manfred showed actual automotive routing (in a BMW) and some electrical bus configurations. He stated, in response to a question from Arpad Muranyi, that twisted cable can be used. Manfred created single-ended IBIS models independently for the CAN_H and CAN_L drivers. The waveforms were extracted by measurement using a 60 ohm differential load. It is normal to a single cycle of significant preshoot and corresponding overshoot ring. The initial modeling approach based on assuming a fixed V_fixture value of 2.5 V did not produce satisfactory simulation results. Manfred presented a new approach to derive the Kpu(t) and Kpd(t) coefficients. He connected the CAN_H pad to a 60 ohm load, and terminated it with a variable V_fixture(t) equal to the the CAN_L voltage (and visa-versa for CAN_L). With this approach, the resulting IBIS differential IBIS model gave overlaying simulations with the measurement data. Manfred also showed excellent simulation correlation with in an actual bus applications. The comparisons showed similar similar ringing on the lines, the simulation ringing amplitude was less damped. This provided a more conservative response and indicated that some losses in the bus might not have been modeled. Manfred concluded that the IBIS can be used to produce a good match between behavioral simulation and measurements when a a new algorithm to generate switching coefficients is used. Arpad Muranyi suggested considering issuing a BIRD for adding time a varying V_fixture(t) table to support this new approach. PARASITIC IC EMISSION MODELING Etienne Sicard, National Institute of Applied Science, France Etienne Sicard provided the overall context of the study by showing examples of increasing EMI radiation. Over the past 10 years the number of components and the clock frequencies have increased significantly, voltage levels have decreased, but transition times and scaled currents have become more of a problem. He showed that radiation can be generated from many sources. The IERSET project is a cooperative effort with industry and academia by the European Research Centre on Electronics for Transportation. Its objectives are to (1) study and evaluate emission and susceptibility measurement methods for integrated circuits, and (2) to define and validate a model to be used in PCB CAD tools to guarantee the EMC of electronic systems. EMC simulation compliance should be part of the IC design flow. Etienne introduced the core emission model. It consists of a current source Ib, and the following parameters connected to the external Vdd and Vss: Rvdd, Lvdd, Rvss, Lvss, Cb and Cd. Existing approaches are too detailed and become impractical for large sized chips or else are too simple and not accurate. With the new approach, Ib is an equivalent current generator. Etienne showed reasonable simulation and measurement correlation. This model can be attached to the IBIS I/O cell through a Zsub resistance and Cio decoupling capacitor. This added detail gives better validation. Etienne also added inductive and capacitive coupling for better correlation with measurement in a TEM cell. Etienne concluded by noting that a simple model has been proposed and has produced satisfactory predictions of emission. The model proposal is being standardized by the French standards body UTE as ICEM. The next step is to produce an ICEM cookbook. Bernhard Unger asked about the physical meaning of the inductance, and Etienne stated that it is related to length of the supply paths within a chip. Arpad Muranyi was concerned about lumping all pins into one model. Etienne stated that there was a 15 dB error in simulations in non-critical regions. The simple model was a good start. Gerald Bannert commented that he expected a 5 dB mismatch. Tom Dagostino stated that shielding within shielding could affect the actual measurement. Patrick dos Santos commented that a plane close to the die also could change the results. INTEGRATED CIRCUITS MODELING, ELECTROMAGNETIC COMPATIBILITY SIMULATION ON PRINTED CIRCUIT BOARD Christian Marot, Siemens, France Christian Marot continued the ICEM presentation by showing actual testing environments for systems and boards. All electronic systems have to fulfill Electromagnetic compatibility tests. It is too late in the design cycle and very expensive if the unit fails EMC testing in an anechoic chamber. Christian showed how IC noise sources based on clock resonances cause the PCB to act as an antenna through supply lines and signal lines. Simulations are needed early in the design process to reduce EMC test stage costs. Currently Spice and IBIS are used for models, and IMIC and ICEM are new proposals to be used along with board RLGC matrices. Increase IC model accuracy is to be linked to the IC internal activity through supply lines, signal lines and direct radiations. Christian advocated an IC data flow linking models and simulation tools. The objective is to use EMC simulation tools to tune virtual test boards and to reduce the amount of expensive actual measurement validation testing. INTEGRATED CIRCUITS MODELING, ICEM INTEGRATED CIRCUITS ELECTROMAGNETIC MODEL PROPOSAL: IEC 62014-3 Jean Claude Perrin, Texas Instruments, France and Christian Huet, EADS Airbus, France Jean Claude Perrin concluded the presentation of ICEM by noting that this is the fourth year that he has participated in the European IBIS Summit. Jean Claude summarized simulation needs for EMC/EMI for integrated circuit manufacturers and printed circuit board designers. Simulation is now needed to comply with EMC directives and standards. Jean Claude listed the members of the UTE EMC Task Force and also traced the history starting with a Working Group in 1994 and continuing through the current CDV proposal that is sent to IEC for standards approval in March 2001 as IEC 62014-3. This is intended to be technical document. The details of the proposed model were again presented. The first schematic showed the power line contribution. The second schematic added the I/O contribution to a single supply structure. The third schematic showed how the I/O contribution can be modeled in a multiple supply structure. Then Jean Claude showed how ICEM can be implemented in an IBIS data base. He showed some related keywords for package modeling and then presented some new keyword possibilities to describe the current generator and to document the intercoupling between supplies. Direct IC electromagnetic emission is mainly due to the package. The variables of interest are pin length, frequency and RLC resonances. Jean Claude concluded that ICEM data can be added to files such as IBIS for simulations for EMC due to internal activity and I/O noise coupling. He listed some planned actions: Issue a cookbook to explain how ICEM model parameters are obtained (a first draft is written) Evaluate the model through the IBIS Open Forum Integrate ICEM in model data bases such as IBIS Integrate EMC simulation capability with ICEM Validate the software There was some discussion on how to obtain the internal currents. Jean Claude commented that IC manufactures must know this information in order to prevent metal migration problems in package designs. Other comments related to getting information from measurements and field solvers. Patrick dos Santos commented that the package model may need to be more detailed. MODELING OF GROUND-NOISE FOR CIRCUITS WITH SHORT-CHANNEL TRANSISTORS Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration, Germany Mariusz Faferko defined ground-noise in terms of a voltage drop across an effective inductance. The test circuit consists of N buffers that switch simultaneously from high to low. Each buffer is simplified to just a CMOS inverter. His solution to model the resulting ground noise is to split the ground noise signal into three phases: Slew Rate linear increase Time response RL circuit Oscillation Circuit The presentation shows the equivalent circuits and mathematical derivations for each phase. Mariusz summarized the resulting equations. These equations were in terms of some physical parameters taken from transistor models, circuit parameters from the schematic some simulation parameters that could be available from IBIS models. Mariusz showed excellent correlation between simulations based on the new model and full circuit Spice simulations, both in the time and frequency domains. He also showed excellent correlation in a second example between simulation and actual measurement. Mariusz added later that this approach has been implemented in a commercial EDA tool. The resulting noise could be added as a source to the signal. Tom Dagostino asked what is covered by Leff, and Mariusz clarified that it does include the package inductance. Tom commented that the formulation ignores common mode (crossbar) currents through the driver. This could be added. Ekkehard Miersch questioned whether this approach could scale linearly for a very large number of drivers (100 or so), as implied in the formulation. There may be other interactions such as supply current limits and voltage drops. Mariusz stated that he thought that it would, and he has had excellent correlation with about 30 drivers. AN ELECTROMAGNETIC EMISSION MODEL FOR INTEGRATED CIRCUITS Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, Germany Peter Kralicek noted that ICs typically are modeled by equivalent circuits that do not contribute to emitted field analysis. This is not sufficient for today's speeds and complex packages. He proposes a another new macromodel. Peter listed the modeling requirements: Good approximation of near and far fields Low number of model parameters Parameter determination via measurement and simulation Simple integration into existing commercial EDA tools Support different modes of operation and connected circuitry He listed a number of possible approaches and is pursuing multipole expansion of the electromagnetic field. The advantage of this approach is that it is scalable for the complexity of the analysis. He showed plots for dipole, quadrupole, octopole and hexapole patterns. More modes can be added, if needed, for more accurate analysis. Two models are proposed: the Simple Emission Model (SEM) and the Voltage Controlled Emission Model (VCEM). The SEM has these attributes: Valid in near and far field Physical model Parameter determination via measurement of simulation No consideration of external circuitry The model parameters are multipole coefficients, and these can optionally support different modes. The VCEM adds these attributes: Voltages at IC ports control modal emissions External circuitry (parasitic effects) considered Peter summarized the workflow. The model parameters could be added to IBIS models. This method has been used in an EDA tool that uses a method of moments field solver to approximate the fields for multipole expansion. Linear system matrix mathematics is used to determine unknown currents. Peter reports only a minimal increase in calculation time. Several different coupling methods are taken into account in a diagram that shows radiations from the PCB/MCM, coupling to/from an antenna, conductive coupling of wires to/from the PCB/MCM, and field coupling of the wires to the PCB/MCM and to/from the antenna. Peter shared some excellent simulation correlation results with almost overlaying comparisons in the time and frequency domains to full wave references. He also showed a case where multipole expansion added more accurate simulation detail. This approach is computationally efficient. POINTS OF VIEW FOR HIGH FREQUENCY IBIS MODELS Gerald Bannert, Siemens AG, Germany Gerald Bannert provided a list of number of detailed points regarding high frequency IBIS models. His classifications are extensive and detailed, and he talked about several of them during the presentation. Some other points had been covered in earlier presentations. Overall, Gerald supports including many of the relevant optional parameters in IBIS models including some new ones that are described in approved BIRDs. He listed a number of technological changes made over the past 10 years. The general trend is for higher speed and complexity, greater I/O variety and greater influence of parasitics. In another table Gerald provided some desired Version 3.2 improvements for handling: New output technologies Scaling algorithm for process, temperature and voltages Coupled package sections Ground bounce Complex input EMI parameters He needs better package detail using coupled sections, but some of the losses are currently not so important. These include skin effect and dielectric losses. One needed improvement is to model cross bar current. Gerald summarized his concerns: He questions if there is a big demand for IBIS-X Further development is needed for IBIS He proposes technical model classification with supporting examples Official IBIS statement on proper model development methods IBIS-X AND THE IBIS MACRO LANGUAGE Stephen Peters and Arpad Muranyi, Intel, USA In the remaining time, Arpad Muranyi gave a brief overview of the IBIS-X ongoing work. He adapted some of Stephen Peters' earlier presentation material for this presentation. The problem is that IBIS is has some serious limitations regarding a number of important parameters. These include: Dealing with some new technologies Return path modeling support Coupled package modeling support Receiver model advances Frequency domain analysis The IBIS-X approach is to keep the good features of IBIS, but add flexibility including nodal interconnection support for model and die interconnect advances, and a macro language for the flexibility of creating new model prototypes. The presentation gave some examples of details. Arpad warned that the syntax is still evolving, so some IBIS-X details are presented only for information on what is being considered. IBIS-X has the flexibility to define new tables and add other formats for numerical data. The IBIS-X extensions also include a number of Spice compatible primitives. Arpad touched on a number of topics. The syntax of elements looks like a more formal version of Spice syntax. Data input can take on may forms from numerical and symbolic values to multidimensional tables. A number of familiar operators are defined, such as || for OR. Extended blocks are defined for: Driver Reshape Delay Voltage Controlled Delay Other likely extensions include: Behavioral voltage and current sources similar to the Berkeley "B" element Integrator block Differentiator block Behavioral integrator Behavioral differentiator Other extensions being considered include: Model creation/functionality - .trigger, .local, .inherit Debug/visibility related - .export, .alarm, .assert Program flow - .if .elseif, .endif, .select, .case, .end select, .array General equations - Berkeley B element Arpad summarized the current status: IBIS Version 3.2 has been implemented in the IBIS-ML (macrolanguage) The Working Group is meeting bi-weekly doing - The overall IBIS-X specification Library guide Programmers Language Reference Manual Much work remains on the die interconnection section In response to Gerald Bannert's question, Arpad stated that IBIS-X goes beyond both Spice and IBIS and addresses things that cannot be done currently. Gerald added that analog simulation can be possible. Ekkehard Miersch commented that lumped package approximations are not sufficient. Bob Ross stated that distributed models are expected to be supported. Etienne Sicard questioned how IBIS-X relates ot IBIS and IMIC, and Arpad responded that these formats and other formats are just levels of abstraction for model details. Someone asked why an existing higher level language such as VHDL-AMS or Verilog-AMS was not used. Arpad responded that we had heard presentations and considered a number of approaches at the June 8, 2000 IBIS Summit Meeting. We chose the macro language approach because in matched what we were trying to accomplish and we were not expert enough to deal with understanding other approaches. The alternatives including extending IBIS, using Spice or IMIC, etc. seemed to be limited in some respects. In a sense, IBIS-X could also be viewed as a Spice-X extension since Spice was also limited for our needs. For example, IMIC table model extensions could be issued using the macro language to describe the table transistor format and its interconnections. Arpad added that when the IBIS-X discussion is moved from the Working Group to the IBIS Open Forum for review, and the macro language is better defined, that topic could be revisited. Bob Ross added that someone would have to help drive an alternative higher level language approach. A formal description of IBIS-X might be the starting point. However, the current plan is to continue with the macro language development and concurrent parser implementation. CONCLUDING REMARKS Bob Ross thanked the participants for attending and the presentors for providing a fine set of presentations. Bob also thanked the sponsors and Karine Loudet again for the setup. The poster she produced is available at the Web site given above. NEXT MEETING: The next teleconference meeting will be on Friday, March 30, 2001, from 8:00 AM to 10:00 AM. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 stephen.peters@intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799 roy_leventhal@3com.com Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary) 1800 W. Central Rd. Mt. Prospect, IL 60056-2293 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 jangulo@innoveda.com Development Engineer, Innoveda 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ============================================================================== From owner-ibis Fri Mar 23 08:40:11 2001 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2NGe8516910 for ; Fri, 23 Mar 2001 08:40:10 -0800 (PST) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id LAA24893 for ; Fri, 23 Mar 2001 11:37:04 -0500 (EST) Received: from taurus.camarillo.innoveda.com (taurus.camarillo.innoveda.com [139.181.194.20]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id LAA12408 for ; Fri, 23 Mar 2001 11:37:03 -0500 (EST) Received: from f22.innoveda.com (f22.camarillo.innoveda.com [139.181.194.48]) by taurus.camarillo.innoveda.com (8.9.3/8.9.3) with SMTP id IAA07787 for ; Fri, 23 Mar 2001 08:37:00 -0800 (PST) Received: by f22.innoveda.com (SMI-8.6/SMI-SVR4) id IAA14739; Fri, 23 Mar 2001 08:37:01 -0800 Date: Fri, 23 Mar 2001 08:37:01 -0800 From: guy@camarillo.innoveda.com (Guy de Burgh) Message-Id: <200103231637.IAA14739@f22.innoveda.com> To: ibis@eda.org Subject: IBIS Open Forum Meeting Agenda IBIS Open Forum Meeting Agenda for 3/30/01 Bridge Number Reservation # Passcode (916) 356-9200 2-524673 6244264 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Ross/Fleming - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Leventhal, All - Opens for New Issues All 8:15 Administrative and Project Discussions International/External Progress - IEC 62014-1 (IBIS Version 3.2) Ross/Fleming - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) Ross - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Ross - JEDEC JC-16 Modeling and Testing Sessions - T10, Project 1414-DT - SCSI Signal Modeling Barnes Date 2001 European IBIS Summit Meeting Review Ross DAC 2001 IBIS Summit Meeting Planning Ross IBIS Model Review Committee Angulo New Administrative Issues All 8:45 Technical Discussion (some topics may be deferred) Connector Proposal Review Panella IBIS Futures Group Report (IBIS-X, API, BIRDxx) Peters BIRD69.1 - Golden Waveforms Edlund BIRD70 - Golden Waveforms Edlund Other Pending BIRDS Ross ibischk3 Bug Tracking Ross - BUG54 - Corners with NA Give Bad Test Load Warnings Mirmak New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Ross 9:55 Sign Off From owner-ibis Fri Mar 30 14:34:02 2001 Received: from relay1.wv.mentorg.com (relay1.mentorg.com [192.94.38.42]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f2UMXx503775; Fri, 30 Mar 2001 14:34:01 -0800 (PST) Received: from svr-orw-exc-02.wv.mentorg.com by relay1.wv.mentorg.com (8.8.8/CF5.40F) id OAA04887; Fri, 30 Mar 2001 14:33:31 -0800 (PST) Received: from mentor.com (bob.wv.mentorg.com [147.34.83.63]) by svr-orw-exc-02.wv.mentorg.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id H6NA0XZX; Fri, 30 Mar 2001 14:33:30 -0800 Sender: bobr@relay1.mentorg.com Message-ID: <3AC509B8.B7F4A864@mentor.com> Date: Fri, 30 Mar 2001 14:33:28 -0800 From: Bob Ross X-Mailer: Mozilla 4.61 [en] (X11; I; SunOS 5.5.1 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: ibis@eda.org, ibis-users@eda.org Subject: New ibischk3 Version 3.2.7 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit To All: New ibischk3 Version 3.2.7 executables have been uploaded under http://www.eda.org/pub/ibis/ibischk3/ The older executables are archived under the same directory. The new executables correct a defect where Warning messages are issued for correct *Open_drain and *Open_sink or *Open_source models. Thanks to Matthew Flora for making the correction and producing the Windows executable and thanks to Guy de Burgh for producing the new Unix executables. A Linux executable still needs to be created and uploaded. The new Source code has been distributed to the companies holding the source code licence. Bob Ross Mentor Graphics