From cpk@Cadence.COM Fri Apr 1 11:01:19 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06957; Fri, 1 Apr 94 11:01:19 PST Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id KAA11740 for ; Fri, 1 Apr 1994 10:59:06 -0800 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma011688; Fri Apr 1 10:58:17 1994 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA05806; Fri, 1 Apr 94 10:55:21 -0800 Received: by hot (5.65+/1.5) id AA28359; Fri, 1 Apr 94 13:57:45 -0500 Date: Fri, 1 Apr 94 13:57:45 -0500 From: cpk@cadence.com (C. Kumar) Message-Id: <9404011857.AA28359@hot> To: ibis@vhdl.org Subject: sample ecl model Folks: Here is a smple ecl model with correct signs (hopefully!!) Here is an ecl pullup and pulldown example [Pullup] Voltage I(typ) I(min) I(max) 0.0 0 0 0 0.7 -0.2m -0.2m -0.2m 0.73 -0.4m -0.4m -0.4m 0.75 -0.8m -0.8m -0.8m 0.76 -1.2m -1.2m -1.2m 0.77 -1.6m -1.6m -1.6m 0.8 -4.4m -4.4m -4.4m 0.82 -7.6m -7.6m -7.6m 0.85 -14.2m -14.2m -14.2m 0.9 -30.0m -30.0m -30.0m 1.0 -58.0m -58.0m -58.0m [Pulldown] Voltage I(typ) I(min) I(max) 0.0 0 0 0 1.6 -0.2m -0.2m -0.2m 1.62 -0.4m -0.4m -0.4m 1.64 -0.6m -0.6m -0.6m 1.65 -0.8m -0.8m -0.8m 1.66 -1.2m -1.2m -1.2m 1.67 -1.6m -1.6m -1.6m 1.68 -2.4m -2.4m -2.4m 1.69 -3.2m -3.2m -3.2m 1.70 -4.4m -4.4m -4.4m 1.72 -7.4m -7.4m -7.4m 1.75 -14.2m -14.2m -14.2m 1.8 -30.5m -30.5m -30.5m 1.9 -65.0m -65.0m -65.0m - Kumar From bob@icx.com Fri Apr 1 13:05:23 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07679; Fri, 1 Apr 94 13:05:23 PST Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA17404 for ; Fri, 1 Apr 94 15:43:43 -0500 Date: Fri, 1 Apr 94 12:21:39 PST From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA17763; Fri, 1 Apr 94 12:21:39 PST Message-Id: <9404012021.AA17763@icx.com> To: ibis@vhdl.org Subject: S2IBIS COMMENTS To IBIS Community: I thought for visibility I would post Steve's response to some recent feedback I provided him regarding my testing of the S2IBIS program with PSpice. Most of my prior discussions related to my own trials and tribulations (and failure to read the documentation) in getting the program running. Overall, excellent progress is being made. Note that the partitioning problem of clamping data and pullup and pulldown data that we discussed today relate to this program as well. Bob Ross, Interconnectix, Inc. Subject: RE:S2IBIS FEEDBACK Date: Fri, 01 Apr 94 12:48:49 EST Status: R Bob: Thank you *very* much for your excellent help! You are quite right about the erroneous voltage ranges in the Pullup and Power_clamp tables. I got this right in the unix version, but when I modified s2ibis to deal with SPICE 3 and PSPICE, I had to rewrite the output handling section. As you know, the IBIS spec requires these tables to be handled differently. The voltage in the table is really Vcc-Voutput. In Version 0.1, the SPICE output is handled the same way for all tables, so these two tables are totally screwed up now. I can not find anything in the IBIS 1.1 spec regarding the partitioning problem. I think I understand your explanation below, but I will wait until I get your papers before I try to fix the program. Regarding vil, vih, etc: this is why I wanted you guys who are actually going to use s2ibis to try it out. I can easily tailor this to work the way you want. For instance, instead of model_type SPICE_NODE ramp_time input_pin [enable_pin] etc... the pindata line for (generic) outputs could include input ramp data such as vih, vil, tr, tf, etc. and look more like: model_type SPICE_NODE ramp_sim_time vil vih tr tf input_pin [enable_pin] etc... Please let me know if this seems like a reasonable approach, or better yet, if you can suggest a better approach. Regarding the alpha-numeric name thing. I ran the example using cc22 in place of node 22 in the SPICE deck (including on pin 8's pindata line) and all worked well. Did you perhaps change the 8 to cc22 as well? I guess the IBIS spec does not explicitly require that pins be integers, but I thought that's what it meant. s2ibis currently requires integer pin names but I could change that easily enough. It is only important (for DOS compatibility) that the pins have less than six characters. Please let me know if you think I should allow alphanumeric pin numbers. Regarding using the same model for several pins: Sorry about that, it's dead easy for s2ibis to do. I put the hooks in to do it, I just forgot to implement them because all of my test files have only one pin with any given model name. I will wait until we straighten out some of these problems before I put anything new on vhdl.org. Once again, thank you very much for your effort and help! Steve
Message-Id: <9403312037.AA14543@icx.com>
To: slipa@eos.ncsu.edu
Subject: S2IBIS FEEDBACK

Steve,

I have done a few tests and am beginning to understand more the program.
Here are some comments to date on the PSpice version on DOS:

(1) I just noticed that in the original and preview versions, the [Pullup] &
[Power_clamp] table voltages extend incorrectly from 10V to 5V using
your example. This may be related to the suspiciously low rise and
fall ramp voltages and results. This may be a problem only in the
PSpice version???

(2) One application I tried was to use the same output model for
several pins. The result was to produce several identical output
model files rather than to recognize that the simulation has already
been done. IBIS_CHK flags as an error models of the same name. In
constructing a [Pin] file, you would normally have sets of identical
models.

(3) There may be confusion about the vil and vih parameters. I initially
viewed them as methods to set the [Model] Vinh = 2.0 and Vinl = 0.8 (for
TTL) values (or corresponding CMOS Input levels of approximately 1.5 and 3.5V).
In my opinion the insertion of such values is a "virtual" requirement for
proper input timing analysis, although making them required fell through
the cracks when IBIS Version 1.1 was drafted.

S2IBIS does not insert Vinh and Vinl because vil and vih is for a
different purpose - specifing the low and high state input voltages for
low and high output states. The documentation needs to indicate that
the input pulse amplitudes are also controlled by vih and vil. Typically
Data Books give ranges such as 0 to 3 V for TTL (5 V supply) for input
pulses and these are useful. A refine (which is debatable) is to also
insert a 25 Ohm series resistance in the ru and rd models at the input
to represent a typical terminated pulse generator used in specification.
This would be the case if you are basing models from measurements and
want to resimulate the setup.

I would like a separate, optional method to insert Vinh and Vinl in the
[Model] in some future release.

(4) Regarding C_comp, this is an underspecified parameter that rarely
appears in data books. The TI ABT data book contains Ci and Co values
for the die which would be C_comp values for Input and Output or I/O
models. The supplied values are reasonable estimations (often under
specified voltage conditions) of the non-linear capacitance reactance
one would really observe, and what on gets when the device models with
Cjo are used with Spice. IBIS supports only a fixed, constant value.
For higher speed devices, typical values range from about 3 to 10 pF.
While this is a crude estimate, it is still useful when the IBIS model
is used in Signal Integrity AND Timing analysis. Therefore, an
extension to the program would be to allow this parameter to be inserted
as a specified value for each [Model]. Normally Output and I/O models
will have larger C_comp values than Input models.

(5) Regarding alphanumeric pin designation, I get an error in your sample
model when is insert pin cc27 in place of pin 8. It accepts pin aa25
in place of pin 3 although the resulting file did not capture the output
model name. Also, the resulting *.spi files used 0 as the pin extension
rather than the alphanumeric designation.

Steve, I am really enjoying working with the program and expect to be
supplying you more feedback. Some of what I am reporting appear to be
bugs. The rest is to make to program in full compliance with IBIS Version 1.1
including most if not all the optional specifications and to make the S2IBIS
program of production versus prototype quality. I still remain very
impressed with what you have produced. I hope this helps.

Bob Date: Thu, 31 Mar 94 19:32:48 PST >From: bob ( Bob Ross) To: slipa@eos.ncsu.edu Subject: MORE S2IBIS FEEDBACK Status: R Steve, I got the BIPOLAR F244 model working after finally getting the Input and Enable polarities sorted out. Here are some more comments. (1) Regarding the [GND_clamp] and [Pulldown] tables, there apprears to be a general partitioning problem. For Output type models, the [Gnd_clamp] currents are added to the [Pulldown] currents, so in producing a [Pulldown] model for the voltages extending into the clamping regions, the [Gnd_clamp] and [Pulldown] currents must be partioned so that the combination of currents produces the currents you get with Spice simulations. I am sending you copies of a handwritten presentation I gave at the IBIS Forum in November, 1993 which shows some aspects of the "partitioning" problem. The same comments apply for CMOS models, but the partitioning strategy is different. I am also sending you a copy of my F244 model and one that was produces as an example. There are other problems with the F244 model previously noted. (2) Another suggestion is to put in detection routines to sense the existence or non-existence of clamps. Even though large tables are provided, the [Power_clamp] does not really exist in the model provided. Bob From speters@ichips.intel.com Fri Apr 1 16:31:34 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09187; Fri, 1 Apr 94 16:31:34 PST Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Fri, 1 Apr 94 16:29:16 -0800 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Fri, 1 Apr 94 16:28:50 -0800 Received: from localhost by xtg801.intel.com (4.1/10.0i); Fri, 1 Apr 94 16:28:59 PST Message-Id: <9404020028.AA07568@xtg801.intel.com> To: ibis@vhdl.org Subject: new IBIS model Date: Fri, 01 Apr 1994 16:28:58 -0800 From: Stephen Peters Fellow IBISans -- At the meeting today we discussed a model from Intel that contained non-monotonic data in the pulldown table. As promised during the conversion here is the model for your inspection and use. By the way, this and four other chip set models have been sent to vhdl.org and will be available soon. Best regards, Stephen Peters Intel Corp. -------------------- cut here ---------------------------------- |**************************************************************************** | [IBIS Ver] 1.1 [File name] psc_a2.ibs [File Rev] 0.9 [Date] 3/25/94 [Source] File originated at Intel Corporation. [Notes] The following information corresponds to the A2 stepping of the 82425EX. [Disclaimer] This information is for modeling purposes only, and is not guaranteed. | |**************************************************************************** | [Component] 82425EX [Manufacturer] Intel [Package] | typ min max R_pkg 252m 227m 277m L_pkg 29.75nH 26.75nH 32.75nH C_pkg 1.28pF 1.21pF 1.36pF | |**************************************************************************** | [Pin] signal_name model_name R_pin L_pin C_pin | 1 VSS GND 2 SERR# PSCB12211A0S2AZZZZC 3 CMDV# PSCB08080A1K3KZZKMB 4 SIDLE# PSCB08080A1K3KZZKMB 5 LREQ# PSCI00000A1K3KZZNMC 6 LGNT# PSCB08080A0S2AZZKMB 7 PCICLKIN PSCI00000A0S2AZZNMC 8 A31 PSCB08081A0S2AZZKMB 9 A25 PSCB08081A0S2AZZKMB 10 VDD POWER 11 A26 PSCB08081A0S2AZZKMB 12 A17 PSCB08081A0S2AZZKMB 13 A23 PSCB08081A0S2AZZKMB 14 A19 PSCB08081A0S2AZZKMB 15 VSS GND 16 A21 PSCB08081A0S2AZZKMB 17 A18 PSCB08081A0S2AZZKMB 18 A14 PSCB08081A0S2AZZKMB 19 A24 PSCB08081A0S2AZZKMB 20 A22 PSCB08081A0S2AZZKMB 21 A15 PSCB08081A0S2AZZKMB 22 A12 PSCB08081A0S2AZZKMB 23 A20 PSCB08081A0S2AZZKMB 24 A16 PSCB08081A0S2AZZKMB 25 A13 PSCB08081A0S2AZZKMB 26 A9 PSCB08081A0S2AZZKMB 27 VSS GND 28 A5 PSCB08081A0S2AZZKMB 29 A11 PSCB08081A0S2AZZKMB 30 A7 PSCB08081A0S2AZZKMB 31 A8 PSCB08081A0S2AZZKMB 32 A10 PSCB08081A0S2AZZKMB 33 A2 PSCB08081A0S2AZZKMB 34 A3 PSCB08081A0S2AZZKMB 35 A6 PSCB08081A0S2AZZKMB 36 A4 PSCB08081A0S2AZZKMB 37 SMI# PSCI00000A0S2AZKNUC 38 VSS GND 39 HCLKIN PSCI00000A0S2AZZVTC 40 CPURST PSCI00000A0S2AZZNMC 41 SRESET/INIT PSCB08081A0S2AZZKMB 42 TAG8 PSCB04041A0S2AZZHIB 43 VDD POWER 44 TAG0 PSCB04041A0S2AZZHIB 45 TAG1 PSCB04041A0S2AZZHIB 46 TAG2 PSCB04041A0S2AZZHIB 47 TAG3 PSCB04041A0S2AZZHIB 48 TAG4 PSCB04041A0S2AZZHIB 49 TAG5 PSCB04041A0S2AZZHIB 50 TAG6 PSCB04041A0S2AZZHIB 51 TAG7 PSCB04041A0S2AZZHIB 52 TWE# PSCB04041A0S2AZZHIB 53 BE0# PSCB08081A0S2AZZKMB 54 BE1# PSCB08081A0S2AZZKMB 55 BE2# PSCB08081A0S2AZZKMB 56 BE3# PSCB08081A0S2AZZKMB 57 HITM# PSCI00000A0S2AZKNUC 58 ADS# PSCI00000A0S2AZZNMC 59 BLAST# PSCI00000A0S2AZKNUC 60 VSS GND 61 VDD POWER 62 HLDA PSCI00000A0S2AZZNMC 63 M/IO# PSCB04041A0S2AZZHIB 64 W/R# PSCB08081A0S2AZZKMB 65 D/C# PSCI00000A0S2AZKNUC 66 PCD/CACHE# PSCI00000A0S2AZZNMC 67 BRDY# PSCB08080A0S2AZZKMB 68 KEN# PSCB08080A0S2AZZKMB 69 RDY# PSCB08080A0S2AZZKMB 70 HOLD PSCB08080A0S2AZZKMB 71 EADS# PSCB08080A0S2AZZKMB 72 HD0 PSCB08081A0S2AZZKMB 73 HDP0 PSCB08081A0S2AZZKMB 74 HD1 PSCB08081A0S2AZZKMB 75 HD2 PSCB08081A0S2AZZKMB 76 HD30 PSCB08081A0S2AZZKMB 77 HD4 PSCB08081A0S2AZZKMB 78 HD28 PSCB08081A0S2AZZKMB 79 HD7 PSCB08081A0S2AZZKMB 80 HD6 PSCB08081A0S2AZZKMB 81 HD31 PSCB08081A0S2AZZKMB 82 HD29 PSCB08081A0S2AZZKMB 83 HD14 PSCB08081A0S2AZZKMB 84 VSS GND 85 HD26 PSCB08081A0S2AZZKMB 86 HD16 PSCB08081A0S2AZZKMB 87 HD5 PSCB08081A0S2AZZKMB 88 HD27 PSCB08081A0S2AZZKMB 89 HDP2 PSCB08081A0S2AZZKMB 90 HD3 PSCB08081A0S2AZZKMB 91 HD25 PSCB08081A0S2AZZKMB 92 HD24 PSCB08081A0S2AZZKMB 93 HD12 PSCB08081A0S2AZZKMB 94 HD15 PSCB08081A0S2AZZKMB 95 HD8 PSCB08081A0S2AZZKMB 96 VSS GND 97 VDD POWER 98 HDP1 PSCB08081A0S2AZZKMB 99 HD10 PSCB08081A0S2AZZKMB 100 HD17 PSCB08081A0S2AZZKMB 101 HD13 PSCB08081A0S2AZZKMB 102 HD9 PSCB08081A0S2AZZKMB 103 HD18 PSCB08081A0S2AZZKMB 104 HD11 PSCB08081A0S2AZZKMB 105 HD21 PSCB08081A0S2AZZKMB 106 HD19 PSCB08081A0S2AZZKMB 107 HD22 PSCB08081A0S2AZZKMB 108 HD20 PSCB08081A0S2AZZKMB 109 HD23 PSCB08081A0S2AZZKMB 110 HDP3 PSCB08081A0S2AZZKMB 111 A20M# PSCB08080A0S2AZZKMB 112 AHOLD PSCB08080A0S2AZZKMB 113 CWE0# PSCB08080A0S2AZZKMB 114 VDD POWER 115 CWE1# PSCB08080A0S2AZZKMB 116 CLK2IN PSCI00000A0S2AZZNMC 117 MA0 PSCB12211A0S2AZZZZC 118 MA1 PSCB12211A0S2AZZZZC 119 VSS GND 120 MA2 PSCB12211A0S2AZZZZC 121 MA3 PSCB12211A0S2AZZZZC 122 MA4 PSCB12211A0S2AZZZZC 123 MA5 PSCB12211A0S2AZZZZC 124 MA6 PSCB12211A0S2AZZZZC 125 MA7 PSCB12211A0S2AZZZZC 126 MA8 PSCB12211A0S2AZZZZC 127 MA9 PSCB12211A0S2AZZZZC 128 VSS GND 129 MA10 PSCB12211A0S2AZZZZC 130 LBIDE# PSCB08081A0S2AZZKMB 131 SMIACT# PSCI00000A0S2AZKNUC 132 CI3E PSCB08080A0S2AZZKMB 133 CI3O2 PSCB08080A0S2AZZKMB 134 COE1# PSCB08080A0S2AZZKMB 135 COE0# PSCB08080A0S2AZZKMB 136 RAS0# PSCB16161A0S2AZZRUC 137 RAS1# PSCB16161A0S2AZZRUC 138 RAS2# PSCB16161A0S2AZZRUC 139 RAS3# PSCB16161A0S2AZZRUC 140 RAS4# PSCB16161A0S2AZZRUC 141 CAS0# PSCB16160A0S2AZZRUC 142 VSS GND 143 CAS4# PSCB16160A0S2AZZRUC 144 CAS1# PSCB16160A0S2AZZRUC 145 CAS5# PSCB16160A0S2AZZRUC 146 CAS2# PSCB16160A0S2AZZRUC 147 VDD POWER 148 CAS6# PSCB16160A0S2AZZRUC 149 CAS3# PSCB16160A0S2AZZRUC 150 CAS7# PSCB16160A0S2AZZRUC 151 WE# PSCB12211A0S2AZZZZC 152 PREQ1/HDEV# PSCI00000A0S2AZZNMC 153 PREQ0# PSCI00000A0S2AZZNMC 154 PGNT1/HRDY# PSCB08081A0S2AZZKMB 155 VSS GND 156 PGNT0# PSCB08080A0S2AZZKMB 157 AD31 PSCB12211A0S2AZZZZC 158 AD30 PSCB12211A0S2AZZZZC 159 AD29 PSCB12211A0S2AZZZZC 160 AD28 PSCB12211A0S2AZZZZC 161 AD27 PSCB12211A0S2AZZZZC 162 AD26 PSCB12211A0S2AZZZZC 163 AD25 PSCB12211A0S2AZZZZC 164 VSS GND 165 VDD POWER 166 AD24 PSCB12211A0S2AZZZZC 167 C/BE3# PSCB12211A0S2AZZZZC 168 AD23 PSCB12211A0S2AZZZZC 169 AD22 PSCB12211A0S2AZZZZC 170 AD21 PSCB12211A0S2AZZZZC 171 AD20 PSCB12211A0S2AZZZZC 172 VSS GND 173 AD19 PSCB12211A0S2AZZZZC 174 AD18 PSCB12211A0S2AZZZZC 175 AD17 PSCB12211A0S2AZZZZC 176 AD16 PSCB12211A0S2AZZZZC 177 C/BE2# PSCB12211A0S2AZZZZC 178 VSS GND 179 FRAME# PSCB12211A0S2AZZZZC 180 IRDY# PSCB12211A0S2AZZZZC 181 TRDY# PSCB12211A0S2AZZZZC 182 KBDRST# PSCI00000A0S2AZZNMC 183 DEVSEL# PSCB12211A0S2AZZZZC 184 STOP# PSCB12211A0S2AZZZZC 185 LOCK# PSCI00000A0S2AZZNMC 186 PAR PSCB12211A0S2AZZZZC 187 VSS GND 188 C/BE1# PSCB12211A0S2AZZZZC 189 AD15 PSCB12211A0S2AZZZZC 190 AD14 PSCB12211A0S2AZZZZC 191 AD13 PSCB12211A0S2AZZZZC 192 AD12 PSCB12211A0S2AZZZZC 193 VSS GND 194 AD11 PSCB12211A0S2AZZZZC 195 AD10 PSCB12211A0S2AZZZZC 196 AD9 PSCB12211A0S2AZZZZC 197 AD8 PSCB12211A0S2AZZZZC 198 C/BE0# PSCB12211A0S2AZZZZC 199 AD7 PSCB12211A0S2AZZZZC 200 VSS GND 201 VDD POWER 202 AD6 PSCB12211A0S2AZZZZC 203 AD5 PSCB12211A0S2AZZZZC 204 AD4 PSCB12211A0S2AZZZZC 205 AD3 PSCB12211A0S2AZZZZC 206 AD2 PSCB12211A0S2AZZZZC 207 AD1 PSCB12211A0S2AZZZZC 208 AD0 PSCB12211A0S2AZZZZC | |********************************************************************* | [Model] PSCB12211A0S2AZZZZC Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -890.71uA -742.99uA -1.06mA -4.50V -1.01mA -840.93uA -1.21mA -4.00V -1.17mA -968.91uA -1.40mA -3.50V -1.38mA -1.14mA -1.66mA -3.00V -1.70mA -1.39mA -2.05mA -2.50V -2.20mA -1.79mA -2.68mA -2.00V -3.11mA -2.50mA -3.86mA -1.50V -5.34mA -4.13mA -6.90mA -1.40V -6.22mA -4.74mA -8.17mA -1.30V -7.44mA -5.57mA -9.99mA -1.20V -9.25mA -6.74mA -12.88mA -1.10V -12.15mA -8.50mA -17.92mA -1.00V -17.48mA -11.42mA -28.66mA -900.00mV -29.53mA -16.99mA -60.56mA -800.00mV -63.92mA -29.97mA -139.05mA -700.00mV -100.16mA -58.60mA -140.48mA -600.00mV -91.61mA -68.58mA -123.09mA -500.00mV -77.85mA -59.44mA -104.65mA -400.00mV -63.42mA -48.42mA -85.43mA -300.00mV -48.44mA -36.93mA -65.40mA -200.00mV -32.89mA -25.03mA -44.53mA -100.00mV -16.75mA -12.72mA -22.74mA 0.00V 33.77pA 23.34pA 7.10nA 100.00mV 16.55mA 12.55mA 22.49mA 200.00mV 32.09mA 24.38mA 43.52mA 300.00mV 46.66mA 35.49mA 63.15mA 400.00mV 60.33mA 45.93mA 81.46mA 500.00mV 73.06mA 55.70mA 98.51mA 600.00mV 84.92mA 64.84mA 114.37mA 700.00mV 96.02mA 73.36mA 129.04mA 800.00mV 106.34mA 81.28mA 142.56mA 900.00mV 115.89mA 88.63mA 155.15mA 1.00V 124.72mA 95.42mA 166.73mA 1.10V 132.84mA 101.67mA 177.37mA 1.20V 140.29mA 107.39mA 187.10mA 1.30V 147.09mA 112.61mA 195.97mA 1.40V 153.26mA 117.34mA 204.00mA 1.50V 158.84mA 121.60mA 211.24mA 1.60V 163.87mA 125.36mA 217.71mA 1.70V 168.28mA 128.68mA 223.54mA 1.80V 172.14mA 131.59mA 228.58mA 1.90V 175.48mA 134.08mA 232.91mA 2.00V 178.32mA 136.17mA 236.64mA 2.10V 180.67mA 137.85mA 239.75mA 2.20V 182.55mA 139.16mA 242.26mA 2.30V 183.97mA 140.09mA 244.12mA 2.40V 184.90mA 140.56mA 244.90mA 2.50V 185.02mA 140.72mA 245.08mA 2.60V 185.14mA 140.80mA 245.26mA 2.70V 185.27mA 140.89mA 245.44mA 2.80V 185.39mA 140.98mA 245.62mA 2.90V 185.51mA 141.07mA 245.80mA 3.00V 185.63mA 141.15mA 245.98mA 3.10V 185.75mA 141.24mA 246.16mA 3.20V 185.88mA 141.33mA 246.34mA 3.30V 186.00mA 141.41mA 246.52mA 3.40V 186.12mA 141.50mA 246.70mA 3.50V 186.24mA 141.59mA 246.88mA 3.60V 186.36mA 141.68mA 247.06mA 3.70V 186.49mA 141.76mA 247.23mA 3.80V 186.61mA 141.85mA 247.41mA 3.90V 186.73mA 141.94mA 247.59mA 4.00V 186.85mA 142.03mA 247.77mA 4.10V 186.98mA 142.11mA 247.95mA 4.20V 187.10mA 142.20mA 248.13mA 4.30V 187.22mA 142.29mA 248.31mA 4.40V 187.34mA 142.38mA 248.49mA 4.50V 187.46mA 142.46mA 248.67mA 4.60V 187.59mA 142.55mA 248.85mA 4.70V 187.71mA 142.64mA 249.03mA 4.80V 187.83mA 142.73mA 249.21mA 4.90V 187.95mA 142.81mA 249.39mA 5.00V 188.07mA 142.90mA 249.57mA 10.00V 194.20mA 147.35mA 258.49mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -81.60A -78.35A -84.80A -4.80V -77.63A -74.58A -80.62A -4.60V -73.66A -70.81A -76.45A -4.40V -69.69A -67.05A -72.27A -4.20V -65.72A -63.28A -68.10A -4.00V -61.76A -59.52A -63.93A -3.80V -57.80A -55.76A -59.77A -3.60V -53.83A -52.00A -55.60A -3.40V -49.88A -48.25A -51.44A -3.20V -45.92A -44.50A -47.28A -3.00V -41.97A -40.75A -43.13A -2.80V -38.03A -37.01A -38.98A -2.60V -34.09A -33.28A -34.84A -2.40V -30.16A -29.55A -30.70A -2.20V -26.24A -25.83A -26.57A -2.00V -22.33A -22.13A -22.45A -1.95V -21.35A -21.20A -21.43A -1.90V -20.38A -20.28A -20.40A -1.85V -19.40A -19.36A -19.38A -1.80V -18.43A -18.44A -18.35A -1.75V -17.46A -17.52A -17.33A -1.70V -16.49A -16.60A -16.31A -1.65V -15.53A -15.69A -15.29A -1.60V -14.56A -14.77A -14.28A -1.55V -13.60A -13.86A -13.26A -1.50V -12.64A -12.95A -12.25A -1.45V -11.69A -12.05A -11.25A -1.40V -10.73A -11.14A -10.24A -1.35V -9.79A -10.25A -9.24A -1.30V -8.84A -9.35A -8.25A -1.25V -7.91A -8.47A -7.26A -1.20V -6.97A -7.58A -6.28A -1.15V -6.06A -6.71A -5.32A -1.10V -5.14A -5.84A -4.36A -1.05V -4.26A -4.99A -3.45A -1.00V -3.38A -4.15A -2.53A -950.00mV -2.56A -3.35A -1.73A -900.00mV -1.74A -2.55A -927.49mA -850.00mV -1.11A -1.84A -500.98mA -800.00mV -472.49mA -1.14A -74.47mA -750.00mV -250.71mA -682.11mA -37.85mA -700.00mV -28.92mA -226.02mA -1.24mA -650.00mV -14.88mA -120.15mA -629.67uA -600.00mV -843.55uA -14.28mA -18.43uA -550.00mV -433.74uA -7.47mA -9.37uA -500.00mV -23.92uA -655.44uA -313.92nA -450.00mV -12.32uA -342.67uA -160.86nA -400.00mV -726.43nA -29.90uA -7.80nA -350.00mV -376.22nA -15.66uA -4.00nA -300.00mV -26.00nA -1.42uA -207.47pA -250.00mV -13.56nA -743.98nA -71.11pA -200.00mV -1.11nA -72.29nA 65.24pA -150.00mV -533.58pA -38.32nA 78.38pA -100.00mV 42.86pA -4.34nA 91.51pA -50.00mV 52.35pA -2.39nA 81.72pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 293.26uA 237.10uA 363.79uA -4.50V 332.02uA 267.74uA 412.95uA -4.00V 382.75uA 307.61uA 477.63uA -3.50V 452.01uA 361.66uA 566.58uA -3.00V 552.25uA 439.11uA 696.63uA -2.50V 710.26uA 559.39uA 904.83uA -2.00V 996.14uA 771.61uA 1.29mA -1.50V 1.67mA 1.24mA 2.26mA -1.40V 1.93mA 1.42mA 2.65mA -1.30V 2.28mA 1.65mA 3.20mA -1.20V 2.79mA 1.97mA 4.06mA -1.10V 3.58mA 2.43mA 5.48mA -1.00V 4.95mA 3.16mA 8.33mA -900.00mV 7.80mA 4.47mA 15.88mA -800.00mV 15.45mA 7.27mA 39.75mA -700.00mV 30.04mA 14.11mA 47.11mA -600.00mV 29.55mA 20.76mA 40.75mA -500.00mV 24.78mA 18.56mA 34.01mA -400.00mV 19.84mA 14.91mA 27.24mA -300.00mV 14.89mA 11.19mA 20.44mA -200.00mV 9.92mA 7.46mA 13.63mA -100.00mV 4.96mA 3.72mA 6.81mA 0.00V -22.37pA -19.51pA -9.81pA 100.00mV -4.88mA -3.66mA -6.71mA 200.00mV -9.62mA -7.20mA -13.24mA 300.00mV -14.21mA -10.63mA -19.58mA 400.00mV -18.66mA -13.95mA -25.73mA 500.00mV -22.96mA -17.15mA -31.70mA 600.00mV -27.11mA -20.24mA -37.48mA 700.00mV -31.12mA -23.21mA -43.07mA 800.00mV -35.00mA -26.07mA -48.46mA 900.00mV -38.73mA -28.82mA -53.69mA 1.00V -42.32mA -31.45mA -58.72mA 1.10V -45.76mA -33.97mA -63.57mA 1.20V -49.06mA -36.37mA -68.24mA 1.30V -52.22mA -38.66mA -72.72mA 1.40V -55.23mA -40.84mA -77.01mA 1.50V -58.11mA -42.90mA -81.11mA 1.60V -60.85mA -44.84mA -85.03mA 1.70V -63.43mA -46.67mA -88.78mA 1.80V -65.87mA -48.39mA -92.33mA 1.90V -68.16mA -50.00mA -95.67mA 2.00V -70.32mA -51.49mA -98.85mA 2.10V -72.33mA -52.87mA -101.83mA 2.20V -74.20mA -54.14mA -104.63mA 2.30V -75.92mA -55.29mA -107.24mA 2.40V -77.50mA -56.33mA -109.67mA 2.50V -78.94mA -57.26mA -111.90mA 2.60V -80.24mA -58.07mA -113.96mA 2.70V -81.39mA -58.77mA -115.82mA 2.80V -82.40mA -59.36mA -117.50mA 2.90V -83.26mA -59.84mA -118.99mA 3.00V -83.99mA -60.20mA -120.30mA 3.10V -84.57mA -60.45mA -121.42mA 3.20V -85.01mA -60.66mA -122.35mA 3.30V -85.31mA -61.64mA -123.10mA 3.40V -85.89mA -62.14mA -123.66mA 3.50V -87.03mA -62.55mA -124.04mA 3.60V -87.71mA -62.91mA -125.15mA 3.70V -88.27mA -63.24mA -126.61mA 3.80V -88.76mA -63.54mA -127.55mA 3.90V -89.21mA -63.83mA -128.34mA 4.00V -89.63mA -64.11mA -129.04mA 4.10V -90.03mA -64.37mA -129.68mA 4.20V -90.41mA -64.63mA -130.27mA 4.30V -90.77mA -64.87mA -130.84mA 4.40V -91.12mA -65.12mA -131.38mA 4.50V -91.47mA -65.35mA -131.90mA 4.60V -91.80mA -65.58mA -132.40mA 4.70V -92.12mA -65.81mA -132.89mA 4.80V -92.44mA -66.03mA -133.36mA 4.90V -92.76mA -66.25mA -133.82mA 5.00V -93.06mA -66.47mA -134.28mA 10.00V -105.82mA -75.88mA -152.50mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 24.20A 23.26A 25.12A -4.80V 23.03A 22.15A 23.89A -4.60V 21.86A 21.05A 22.66A -4.40V 20.70A 19.94A 21.43A -4.20V 19.53A 18.83A 20.21A -4.00V 18.36A 17.72A 18.98A -3.80V 17.20A 16.62A 17.76A -3.60V 16.03A 15.51A 16.53A -3.40V 14.87A 14.41A 15.31A -3.20V 13.70A 13.30A 14.08A -3.00V 12.54A 12.20A 12.86A -2.80V 11.38A 11.10A 11.64A -2.60V 10.22A 10.00A 10.42A -2.40V 9.07A 8.91A 9.20A -2.20V 7.91A 7.81A 7.99A -2.00V 6.76A 6.72A 6.78A -1.95V 6.47A 6.45A 6.48A -1.90V 6.19A 6.18A 6.17A -1.85V 5.90A 5.91A 5.87A -1.80V 5.62A 5.64A 5.57A -1.75V 5.33A 5.37A 5.27A -1.70V 5.05A 5.09A 4.97A -1.65V 4.76A 4.83A 4.67A -1.60V 4.48A 4.56A 4.37A -1.55V 4.19A 4.29A 4.07A -1.50V 3.91A 4.02A 3.77A -1.45V 3.63A 3.75A 3.48A -1.40V 3.35A 3.49A 3.18A -1.35V 3.07A 3.22A 2.89A -1.30V 2.79A 2.96A 2.59A -1.25V 2.51A 2.70A 2.30A -1.20V 2.24A 2.43A 2.01A -1.15V 1.97A 2.18A 1.73A -1.10V 1.69A 1.92A 1.44A -1.05V 1.43A 1.67A 1.17A -1.00V 1.17A 1.41A 895.50mA -950.00mV 918.59mA 1.17A 645.93mA -900.00mV 669.94mA 929.86mA 396.35mA -850.00mV 457.92mA 708.53mA 227.19mA -800.00mV 245.89mA 487.19mA 58.03mA -750.00mV 135.93mA 316.35mA 29.63mA -700.00mV 25.96mA 145.51mA 1.22mA -650.00mV 13.40mA 79.52mA 620.48uA -600.00mV 834.22uA 13.53mA 17.66uA -550.00mV 428.67uA 7.09mA 8.96uA -500.00mV 23.11uA 648.26uA 252.35nA -450.00mV 11.88uA 338.64uA 127.94nA -400.00mV 637.26nA 29.02uA 3.54nA -350.00mV 327.37nA 15.16uA 1.74nA -300.00mV 17.49nA 1.30uA -54.07pA -250.00mV 8.95nA 676.73nA -58.87pA -200.00mV 410.14pA 58.39nA -63.67pA -150.00mV 173.54pA 30.81nA -81.84pA -100.00mV -63.06pA 3.23nA -100.01pA -50.00mV -64.85pA 1.98nA -79.19pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 1.95V/887.40ps 1.64V/1.29ns 2.27V/532.93ps dV/dt_f 2.61V/1.17ns 2.36V/1.39ns 2.84V/851.21ps | |********************************************************************* | [Model] PSCB08080A0S2AZZKMB Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 1.80pF 0.97pF 3.72pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -301.34uA -247.42uA -364.12uA -4.50V -340.96uA -279.12uA -413.24uA -4.00V -392.71uA -320.28uA -477.79uA -3.50V -463.18uA -375.87uA -566.43uA -3.00V -564.76uA -455.12uA -695.74uA -2.50V -723.96uA -577.24uA -902.04uA -2.00V -1.01mA -789.86uA -1.28mA -1.50V -1.66mA -1.25mA -2.22mA -1.40V -1.91mA -1.42mA -2.59mA -1.30V -2.24mA -1.63mA -3.12mA -1.20V -2.71mA -1.92mA -3.91mA -1.10V -3.42mA -2.34mA -5.22mA -1.00V -4.60mA -2.96mA -7.71mA -900.00mV -6.90mA -4.02mA -13.92mA -800.00mV -12.53mA -6.09mA -33.75mA -700.00mV -26.69mA -10.98mA -47.97mA -600.00mV -31.77mA -19.98mA -42.66mA -500.00mV -27.35mA -20.86mA -36.16mA -400.00mV -22.23mA -17.18mA -29.42mA -300.00mV -16.93mA -13.08mA -22.44mA -200.00mV -11.47mA -8.85mA -15.22mA -100.00mV -5.82mA -4.49mA -7.74mA 0.00V 3.09pA 10.15pA 3.80pA 100.00mV 5.76mA 4.43mA 7.67mA 200.00mV 11.21mA 8.63mA 14.91mA 300.00mV 16.36mA 12.61mA 21.75mA 400.00mV 21.23mA 16.36mA 28.19mA 500.00mV 25.80mA 19.89mA 34.25mA 600.00mV 30.09mA 23.22mA 39.93mA 700.00mV 34.13mA 26.34mA 45.25mA 800.00mV 37.91mA 29.25mA 50.19mA 900.00mV 41.44mA 31.97mA 54.82mA 1.00V 44.72mA 34.50mA 59.13mA 1.10V 47.76mA 36.84mA 63.12mA 1.20V 50.57mA 38.99mA 66.80mA 1.30V 53.15mA 40.97mA 70.18mA 1.40V 55.51mA 42.77mA 73.28mA 1.50V 57.66mA 44.41mA 76.09mA 1.60V 59.61mA 45.87mA 78.64mA 1.70V 61.35mA 47.16mA 80.96mA 1.80V 62.88mA 48.31mA 82.99mA 1.90V 64.23mA 49.31mA 84.76mA 2.00V 65.39mA 50.16mA 86.31mA 2.10V 66.37mA 50.86mA 87.64mA 2.20V 67.18mA 51.41mA 88.74mA 2.30V 67.81mA 51.83mA 89.63mA 2.40V 68.28mA 52.10mA 90.28mA 2.50V 68.51mA 52.22mA 90.50mA 2.60V 68.56mA 52.25mA 90.57mA 2.70V 68.60mA 52.28mA 90.63mA 2.80V 68.65mA 52.31mA 90.70mA 2.90V 68.69mA 52.35mA 90.76mA 3.00V 68.74mA 52.38mA 90.83mA 3.10V 68.78mA 52.41mA 90.90mA 3.20V 68.83mA 52.44mA 90.96mA 3.30V 68.87mA 52.48mA 91.03mA 3.40V 68.92mA 52.51mA 91.10mA 3.50V 68.96mA 52.54mA 91.16mA 3.60V 69.01mA 52.57mA 91.23mA 3.70V 69.05mA 52.61mA 91.30mA 3.80V 69.10mA 52.64mA 91.36mA 3.90V 69.14mA 52.67mA 91.43mA 4.00V 69.19mA 52.70mA 91.49mA 4.10V 69.23mA 52.74mA 91.56mA 4.20V 69.28mA 52.77mA 91.63mA 4.30V 69.32mA 52.80mA 91.69mA 4.40V 69.37mA 52.83mA 91.76mA 4.50V 69.41mA 52.87mA 91.83mA 4.60V 69.46mA 52.90mA 91.89mA 4.70V 69.50mA 52.93mA 91.96mA 4.80V 69.55mA 52.96mA 92.03mA 4.90V 69.60mA 53.00mA 92.09mA 5.00V 69.64mA 53.03mA 92.16mA 10.00V 71.91mA 54.68mA 95.45mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -4.47A -4.31A -4.64A -4.80V -4.26A -4.11A -4.41A -4.60V -4.05A -3.90A -4.19A -4.40V -3.83A -3.70A -3.96A -4.20V -3.62A -3.50A -3.74A -4.00V -3.41A -3.30A -3.51A -3.80V -3.19A -3.09A -3.29A -3.60V -2.98A -2.89A -3.07A -3.40V -2.77A -2.69A -2.84A -3.20V -2.56A -2.49A -2.62A -3.00V -2.34A -2.29A -2.40A -2.80V -2.13A -2.08A -2.17A -2.60V -1.92A -1.88A -1.95A -2.40V -1.71A -1.68A -1.73A -2.20V -1.50A -1.48A -1.50A -2.00V -1.29A -1.28A -1.28A -1.95V -1.23A -1.23A -1.23A -1.90V -1.18A -1.18A -1.17A -1.85V -1.13A -1.13A -1.12A -1.80V -1.08A -1.08A -1.06A -1.75V -1.02A -1.03A -1.01A -1.70V -971.55mA -985.28mA -952.38mA -1.65V -919.48mA -935.94mA -897.55mA -1.60V -867.42mA -886.60mA -842.73mA -1.55V -815.56mA -837.45mA -788.12mA -1.50V -763.70mA -788.30mA -733.51mA -1.45V -712.11mA -739.40mA -679.19mA -1.40V -660.52mA -690.50mA -624.86mA -1.35V -609.28mA -641.92mA -570.93mA -1.30V -558.04mA -593.33mA -516.99mA -1.25V -507.29mA -545.17mA -463.62mA -1.20V -456.53mA -497.01mA -410.25mA -1.15V -406.47mA -449.42mA -357.73mA -1.10V -356.42mA -401.84mA -305.20mA -1.05V -307.46mA -355.11mA -254.16mA -1.00V -258.51mA -308.38mA -203.12mA -950.00mV -211.51mA -263.03mA -155.16mA -900.00mV -164.51mA -217.68mA -107.20mA -850.00mV -121.74mA -174.82mA -68.12mA -800.00mV -78.97mA -131.96mA -29.03mA -750.00mV -48.06mA -94.61mA -15.11mA -700.00mV -17.16mA -57.25mA -1.18mA -650.00mV -8.99mA -33.91mA -601.34uA -600.00mV -818.15uA -10.58mA -17.93uA -550.00mV -420.77uA -5.61mA -9.10uA -500.00mV -23.40uA -640.06uA -275.26nA -450.00mV -12.03uA -334.69uA -140.21nA -400.00mV -670.52nA -29.32uA -5.15nA -350.00mV -345.62nA -15.33uA -2.62nA -300.00mV -20.71nA -1.34uA -81.81pA -250.00mV -10.70nA -701.69nA -18.64pA -200.00mV -681.14pA -63.45nA 44.53pA -150.00mV -331.74pA -33.47nA 52.73pA -100.00mV 17.65pA -3.48nA 60.94pA -50.00mV 38.19pA -1.99nA 53.48pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 194.09uA 155.64uA 242.16uA -4.50V 219.46uA 175.46uA 274.62uA -4.00V 252.56uA 201.16uA 317.22uA -3.50V 297.56uA 235.84uA 375.65uA -3.00V 362.36uA 285.22uA 460.71uA -2.50V 463.73uA 361.20uA 596.06uA -2.00V 644.73uA 493.26uA 844.93uA -1.50V 1.06mA 779.22uA 1.45mA -1.40V 1.21mA 881.38uA 1.69mA -1.30V 1.42mA 1.01mA 2.03mA -1.20V 1.72mA 1.19mA 2.53mA -1.10V 2.16mA 1.45mA 3.35mA -1.00V 2.90mA 1.84mA 4.90mA -900.00mV 4.31mA 2.49mA 8.65mA -800.00mV 7.76mA 3.76mA 20.91mA -700.00mV 16.68mA 6.77mA 31.41mA -600.00mV 19.97mA 12.32mA 27.59mA -500.00mV 16.94mA 12.65mA 23.02mA -400.00mV 13.57mA 10.27mA 18.43mA -300.00mV 10.18mA 7.71mA 13.83mA -200.00mV 6.78mA 5.13mA 9.22mA -100.00mV 3.39mA 2.56mA 4.60mA 0.00V -11.95pA -13.37pA -11.73pA 100.00mV -3.34mA -2.52mA -4.54mA 200.00mV -6.58mA -4.96mA -8.96mA 300.00mV -9.73mA -7.33mA -13.27mA 400.00mV -12.78mA -9.63mA -17.45mA 500.00mV -15.74mA -11.84mA -21.52mA 600.00mV -18.60mA -13.98mA -25.46mA 700.00mV -21.37mA -16.04mA -29.29mA 800.00mV -24.05mA -18.03mA -32.98mA 900.00mV -26.63mA -19.94mA -36.57mA 1.00V -29.11mA -21.77mA -40.03mA 1.10V -31.51mA -23.53mA -43.37mA 1.20V -33.80mA -25.21mA -46.59mA 1.30V -36.00mA -26.81mA -49.69mA 1.40V -38.10mA -28.34mA -52.67mA 1.50V -40.11mA -29.78mA -55.52mA 1.60V -42.03mA -31.15mA -58.25mA 1.70V -43.84mA -32.44mA -60.87mA 1.80V -45.56mA -33.65mA -63.35mA 1.90V -47.18mA -34.79mA -65.70mA 2.00V -48.70mA -35.85mA -67.93mA 2.10V -50.12mA -36.83mA -70.04mA 2.20V -51.45mA -37.73mA -72.02mA 2.30V -52.68mA -38.55mA -73.87mA 2.40V -53.81mA -39.30mA -75.60mA 2.50V -54.84mA -39.96mA -77.21mA 2.60V -55.77mA -40.55mA -78.68mA 2.70V -56.61mA -41.06mA -80.03mA 2.80V -57.35mA -41.49mA -81.25mA 2.90V -57.98mA -41.85mA -82.34mA 3.00V -58.52mA -42.12mA -83.31mA 3.10V -58.96mA -42.31mA -84.14mA 3.20V -59.30mA -42.44mA -84.85mA 3.30V -59.55mA -43.06mA -85.43mA 3.40V -59.69mA -43.45mA -85.88mA 3.50V -60.59mA -43.74mA -86.21mA 3.60V -61.11mA -44.00mA -86.40mA 3.70V -61.52mA -44.23mA -87.67mA 3.80V -61.87mA -44.45mA -88.42mA 3.90V -62.19mA -44.65mA -89.01mA 4.00V -62.49mA -44.84mA -89.51mA 4.10V -62.77mA -45.03mA -89.97mA 4.20V -63.03mA -45.21mA -90.39mA 4.30V -63.29mA -45.38mA -90.78mA 4.40V -63.53mA -45.55mA -91.16mA 4.50V -63.77mA -45.71mA -91.52mA 4.60V -64.00mA -45.88mA -91.87mA 4.70V -64.23mA -46.03mA -92.21mA 4.80V -64.45mA -46.19mA -92.54mA 4.90V -64.67mA -46.34mA -92.86mA 5.00V -64.88mA -46.49mA -93.17mA 10.00V -73.72mA -52.91mA -105.74mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 5.54A 5.33A 5.74A -4.80V 5.28A 5.08A 5.46A -4.60V 5.01A 4.83A 5.19A -4.40V 4.75A 4.58A 4.91A -4.20V 4.48A 4.33A 4.63A -4.00V 4.22A 4.08A 4.35A -3.80V 3.95A 3.83A 4.07A -3.60V 3.69A 3.58A 3.80A -3.40V 3.42A 3.33A 3.52A -3.20V 3.16A 3.08A 3.24A -3.00V 2.90A 2.83A 2.96A -2.80V 2.63A 2.58A 2.69A -2.60V 2.37A 2.33A 2.41A -2.40V 2.11A 2.08A 2.13A -2.20V 1.85A 1.83A 1.86A -2.00V 1.59A 1.58A 1.58A -1.95V 1.52A 1.52A 1.52A -1.90V 1.46A 1.46A 1.45A -1.85V 1.39A 1.40A 1.38A -1.80V 1.33A 1.34A 1.31A -1.75V 1.26A 1.27A 1.24A -1.70V 1.20A 1.21A 1.17A -1.65V 1.13A 1.15A 1.11A -1.60V 1.07A 1.09A 1.04A -1.55V 1.00A 1.03A 970.41mA -1.50V 939.30mA 969.08mA 902.71mA -1.45V 875.35mA 908.47mA 835.37mA -1.40V 811.40mA 847.86mA 768.03mA -1.35V 747.89mA 787.64mA 701.18mA -1.30V 684.39mA 727.43mA 634.33mA -1.25V 621.49mA 667.75mA 568.19mA -1.20V 558.60mA 608.07mA 502.05mA -1.15V 496.60mA 549.12mA 436.99mA -1.10V 434.59mA 490.18mA 371.93mA -1.05V 373.99mA 432.33mA 308.77mA -1.00V 313.40mA 374.48mA 245.61mA -950.00mV 255.32mA 318.40mA 186.44mA -900.00mV 197.25mA 262.31mA 127.27mA -850.00mV 144.71mA 209.48mA 79.83mA -800.00mV 92.17mA 156.64mA 32.38mA -750.00mV 55.33mA 111.07mA 16.79mA -700.00mV 18.49mA 65.49mA 1.19mA -650.00mV 9.65mA 38.30mA 604.77uA -600.00mV 820.15uA 11.11mA 17.65uA -550.00mV 421.62uA 5.87mA 8.95uA -500.00mV 23.10uA 640.43uA 252.29nA -450.00mV 11.87uA 334.72uA 127.92nA -400.00mV 637.19nA 29.00uA 3.56nA -350.00mV 327.35nA 15.15uA 1.77nA -300.00mV 17.52nA 1.29uA -18.28pA -250.00mV 8.97nA 676.52nA -32.21pA -200.00mV 422.20pA 58.24nA -46.13pA -150.00mV 194.60pA 30.65nA -55.98pA -100.00mV -32.99pA 3.06nA -65.82pA -50.00mV -44.74pA 1.83nA -54.23pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 1.59V/408.92ps 1.28V/563.27ps 1.95V/274.86ps dV/dt_f 1.89V/1.01ns 1.59V/1.26ns 2.21V/576.96ps | |********************************************************************* | [Model] PSCI00000A0S2AZZNMC Model_type Input | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -6.39A -6.15A -6.62A -4.80V -6.08A -5.86A -6.30A -4.60V -5.78A -5.57A -5.98A -4.40V -5.47A -5.28A -5.66A -4.20V -5.16A -4.99A -5.34A -4.00V -4.86A -4.70A -5.01A -3.80V -4.55A -4.41A -4.69A -3.60V -4.25A -4.12A -4.37A -3.40V -3.95A -3.83A -4.05A -3.20V -3.64A -3.54A -3.73A -3.00V -3.34A -3.25A -3.41A -2.80V -3.03A -2.97A -3.09A -2.60V -2.73A -2.68A -2.78A -2.40V -2.43A -2.39A -2.46A -2.20V -2.13A -2.10A -2.14A -2.00V -1.82A -1.82A -1.82A -1.95V -1.75A -1.75A -1.74A -1.90V -1.67A -1.68A -1.66A -1.85V -1.60A -1.61A -1.59A -1.80V -1.52A -1.54A -1.51A -1.75V -1.45A -1.46A -1.43A -1.70V -1.38A -1.39A -1.35A -1.65V -1.30A -1.32A -1.27A -1.60V -1.23A -1.25A -1.19A -1.55V -1.15A -1.18A -1.11A -1.50V -1.08A -1.11A -1.04A -1.45V -1.00A -1.04A -958.66mA -1.40V -930.38mA -971.89mA -880.98mA -1.35V -857.12mA -902.43mA -803.86mA -1.30V -783.87mA -832.98mA -726.75mA -1.25V -711.33mA -764.15mA -650.47mA -1.20V -638.80mA -695.32mA -574.19mA -1.15V -567.31mA -627.36mA -499.18mA -1.10V -495.81mA -559.39mA -424.16mA -1.05V -425.98mA -492.72mA -351.39mA -1.00V -356.14mA -426.04mA -278.61mA -950.00mV -289.30mA -361.45mA -210.58mA -900.00mV -222.46mA -296.86mA -142.54mA -850.00mV -162.24mA -236.15mA -88.64mA -800.00mV -102.02mA -175.43mA -34.73mA -750.00mV -60.69mA -123.46mA -17.96mA -700.00mV -19.37mA -71.48mA -1.20mA -650.00mV -10.10mA -41.47mA -609.84uA -600.00mV -825.82uA -11.45mA -18.06uA -550.00mV -424.68uA -6.05mA -9.17uA -500.00mV -23.54uA -644.61uA -285.57nA -450.00mV -12.11uA -337.04uA -145.72nA -400.00mV -685.43nA -29.48uA -5.87nA -350.00mV -353.78nA -15.42uA -2.99nA -300.00mV -22.13nA -1.36uA -115.62pA -250.00mV -11.46nA -712.97nA -35.62pA -200.00mV -792.68pA -65.82nA 44.37pA -150.00mV -388.82pA -34.76nA 56.65pA -100.00mV 15.04pA -3.71nA 68.92pA -50.00mV 38.87pA -2.10nA 58.18pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 5.54A 5.33A 5.74A -4.80V 5.28A 5.08A 5.46A -4.60V 5.01A 4.83A 5.19A -4.40V 4.75A 4.58A 4.91A -4.20V 4.48A 4.33A 4.63A -4.00V 4.22A 4.08A 4.35A -3.80V 3.95A 3.83A 4.07A -3.60V 3.69A 3.58A 3.80A -3.40V 3.42A 3.33A 3.52A -3.20V 3.16A 3.08A 3.24A -3.00V 2.90A 2.83A 2.96A -2.80V 2.63A 2.58A 2.69A -2.60V 2.37A 2.33A 2.41A -2.40V 2.11A 2.08A 2.13A -2.20V 1.85A 1.83A 1.86A -2.00V 1.59A 1.58A 1.58A -1.95V 1.52A 1.52A 1.52A -1.90V 1.46A 1.46A 1.45A -1.85V 1.39A 1.40A 1.38A -1.80V 1.33A 1.34A 1.31A -1.75V 1.26A 1.27A 1.24A -1.70V 1.20A 1.21A 1.17A -1.65V 1.13A 1.15A 1.11A -1.60V 1.07A 1.09A 1.04A -1.55V 1.00A 1.03A 970.41mA -1.50V 939.30mA 969.08mA 902.71mA -1.45V 875.35mA 908.47mA 835.37mA -1.40V 811.40mA 847.86mA 768.03mA -1.35V 747.89mA 787.64mA 701.18mA -1.30V 684.39mA 727.43mA 634.33mA -1.25V 621.49mA 667.75mA 568.19mA -1.20V 558.60mA 608.07mA 502.05mA -1.15V 496.60mA 549.12mA 436.99mA -1.10V 434.59mA 490.18mA 371.93mA -1.05V 373.99mA 432.33mA 308.77mA -1.00V 313.40mA 374.48mA 245.61mA -950.00mV 255.32mA 318.40mA 186.44mA -900.00mV 197.25mA 262.31mA 127.27mA -850.00mV 144.71mA 209.48mA 79.82mA -800.00mV 92.17mA 156.64mA 32.38mA -750.00mV 55.33mA 111.07mA 16.79mA -700.00mV 18.49mA 65.49mA 1.19mA -650.00mV 9.65mA 38.30mA 604.77uA -600.00mV 820.15uA 11.11mA 17.65uA -550.00mV 421.62uA 5.87mA 8.95uA -500.00mV 23.10uA 640.32uA 252.28nA -450.00mV 11.87uA 334.66uA 127.92nA -400.00mV 637.18nA 29.00uA 3.55nA -350.00mV 327.35nA 15.15uA 1.76nA -300.00mV 17.51nA 1.29uA -27.61pA -250.00mV 8.96nA 676.56nA -41.15pA -200.00mV 414.43pA 58.28nA -54.69pA -150.00mV 187.47pA 30.69nA -64.97pA -100.00mV -39.50pA 3.10nA -75.25pA -50.00mV -51.95pA 1.87nA -63.26pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Model] PSCB08081A0S2AZZKMB Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 1.80pF 0.97pF 3.72pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -301.34uA -247.42uA -364.12uA -4.50V -340.96uA -279.12uA -413.24uA -4.00V -392.71uA -320.28uA -477.79uA -3.50V -463.18uA -375.87uA -566.43uA -3.00V -564.76uA -455.12uA -695.74uA -2.50V -723.96uA -577.24uA -902.04uA -2.00V -1.01mA -789.86uA -1.28mA -1.50V -1.66mA -1.25mA -2.22mA -1.40V -1.91mA -1.42mA -2.59mA -1.30V -2.24mA -1.63mA -3.12mA -1.20V -2.71mA -1.92mA -3.91mA -1.10V -3.42mA -2.34mA -5.22mA -1.00V -4.60mA -2.96mA -7.71mA -900.00mV -6.90mA -4.02mA -13.92mA -800.00mV -12.53mA -6.09mA -33.75mA -700.00mV -26.69mA -10.98mA -47.97mA -600.00mV -31.77mA -19.98mA -42.66mA -500.00mV -27.35mA -20.86mA -36.16mA -400.00mV -22.23mA -17.18mA -29.42mA -300.00mV -16.93mA -13.08mA -22.44mA -200.00mV -11.47mA -8.85mA -15.22mA -100.00mV -5.82mA -4.49mA -7.74mA 0.00V 3.09pA 10.15pA 3.80pA 100.00mV 5.76mA 4.43mA 7.67mA 200.00mV 11.21mA 8.63mA 14.91mA 300.00mV 16.36mA 12.61mA 21.75mA 400.00mV 21.23mA 16.36mA 28.19mA 500.00mV 25.80mA 19.89mA 34.25mA 600.00mV 30.09mA 23.22mA 39.93mA 700.00mV 34.13mA 26.34mA 45.25mA 800.00mV 37.91mA 29.25mA 50.19mA 900.00mV 41.44mA 31.97mA 54.82mA 1.00V 44.72mA 34.50mA 59.13mA 1.10V 47.76mA 36.84mA 63.12mA 1.20V 50.57mA 38.99mA 66.80mA 1.30V 53.15mA 40.97mA 70.18mA 1.40V 55.51mA 42.77mA 73.28mA 1.50V 57.66mA 44.41mA 76.09mA 1.60V 59.61mA 45.87mA 78.64mA 1.70V 61.35mA 47.16mA 80.96mA 1.80V 62.89mA 48.31mA 82.99mA 1.90V 64.23mA 49.31mA 84.76mA 2.00V 65.40mA 50.16mA 86.31mA 2.10V 66.38mA 50.86mA 87.64mA 2.20V 67.18mA 51.41mA 88.74mA 2.30V 67.82mA 51.83mA 89.63mA 2.40V 68.29mA 52.10mA 90.28mA 2.50V 68.51mA 52.22mA 90.50mA 2.60V 68.56mA 52.25mA 90.57mA 2.70V 68.60mA 52.28mA 90.63mA 2.80V 68.65mA 52.31mA 90.70mA 2.90V 68.69mA 52.35mA 90.76mA 3.00V 68.74mA 52.38mA 90.83mA 3.10V 68.78mA 52.41mA 90.90mA 3.20V 68.83mA 52.44mA 90.96mA 3.30V 68.87mA 52.48mA 91.03mA 3.40V 68.92mA 52.51mA 91.10mA 3.50V 68.96mA 52.54mA 91.16mA 3.60V 69.01mA 52.57mA 91.23mA 3.70V 69.05mA 52.61mA 91.30mA 3.80V 69.10mA 52.64mA 91.36mA 3.90V 69.14mA 52.67mA 91.43mA 4.00V 69.19mA 52.70mA 91.49mA 4.10V 69.23mA 52.74mA 91.56mA 4.20V 69.28mA 52.77mA 91.63mA 4.30V 69.32mA 52.80mA 91.69mA 4.40V 69.37mA 52.83mA 91.76mA 4.50V 69.41mA 52.87mA 91.83mA 4.60V 69.46mA 52.90mA 91.89mA 4.70V 69.50mA 52.93mA 91.96mA 4.80V 69.55mA 52.96mA 92.03mA 4.90V 69.60mA 53.00mA 92.09mA 5.00V 69.64mA 53.03mA 92.16mA 10.00V 71.91mA 54.68mA 95.45mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -4.47A -4.31A -4.64A -4.80V -4.26A -4.11A -4.41A -4.60V -4.05A -3.90A -4.19A -4.40V -3.83A -3.70A -3.96A -4.20V -3.62A -3.50A -3.74A -4.00V -3.41A -3.30A -3.51A -3.80V -3.19A -3.09A -3.29A -3.60V -2.98A -2.89A -3.07A -3.40V -2.77A -2.69A -2.84A -3.20V -2.56A -2.49A -2.62A -3.00V -2.34A -2.29A -2.40A -2.80V -2.13A -2.08A -2.17A -2.60V -1.92A -1.88A -1.95A -2.40V -1.71A -1.68A -1.73A -2.20V -1.50A -1.48A -1.50A -2.00V -1.29A -1.28A -1.28A -1.95V -1.23A -1.23A -1.23A -1.90V -1.18A -1.18A -1.17A -1.85V -1.13A -1.13A -1.12A -1.80V -1.08A -1.08A -1.06A -1.75V -1.02A -1.03A -1.01A -1.70V -971.55mA -985.28mA -952.38mA -1.65V -919.48mA -935.94mA -897.55mA -1.60V -867.42mA -886.60mA -842.73mA -1.55V -815.56mA -837.45mA -788.12mA -1.50V -763.70mA -788.30mA -733.51mA -1.45V -712.11mA -739.40mA -679.19mA -1.40V -660.52mA -690.50mA -624.86mA -1.35V -609.28mA -641.92mA -570.93mA -1.30V -558.04mA -593.33mA -516.99mA -1.25V -507.29mA -545.17mA -463.62mA -1.20V -456.53mA -497.01mA -410.25mA -1.15V -406.47mA -449.42mA -357.73mA -1.10V -356.42mA -401.84mA -305.20mA -1.05V -307.46mA -355.11mA -254.16mA -1.00V -258.51mA -308.38mA -203.12mA -950.00mV -211.51mA -263.03mA -155.16mA -900.00mV -164.51mA -217.68mA -107.20mA -850.00mV -121.74mA -174.82mA -68.12mA -800.00mV -78.97mA -131.96mA -29.03mA -750.00mV -48.06mA -94.61mA -15.11mA -700.00mV -17.16mA -57.25mA -1.18mA -650.00mV -8.99mA -33.91mA -601.34uA -600.00mV -818.15uA -10.58mA -17.93uA -550.00mV -420.77uA -5.61mA -9.10uA -500.00mV -23.40uA -640.06uA -275.26nA -450.00mV -12.03uA -334.69uA -140.21nA -400.00mV -670.52nA -29.32uA -5.15nA -350.00mV -345.62nA -15.33uA -2.62nA -300.00mV -20.71nA -1.34uA -81.81pA -250.00mV -10.70nA -701.69nA -18.64pA -200.00mV -681.14pA -63.45nA 44.53pA -150.00mV -331.74pA -33.47nA 52.73pA -100.00mV 17.65pA -3.48nA 60.94pA -50.00mV 38.19pA -1.99nA 53.48pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 194.09uA 155.64uA 242.16uA -4.50V 219.46uA 175.46uA 274.62uA -4.00V 252.56uA 201.16uA 317.22uA -3.50V 297.56uA 235.84uA 375.65uA -3.00V 362.36uA 285.22uA 460.71uA -2.50V 463.73uA 361.20uA 596.06uA -2.00V 644.73uA 493.26uA 844.93uA -1.50V 1.06mA 779.22uA 1.45mA -1.40V 1.21mA 881.38uA 1.69mA -1.30V 1.42mA 1.01mA 2.03mA -1.20V 1.72mA 1.19mA 2.53mA -1.10V 2.16mA 1.45mA 3.35mA -1.00V 2.90mA 1.84mA 4.90mA -900.00mV 4.31mA 2.49mA 8.65mA -800.00mV 7.76mA 3.76mA 20.91mA -700.00mV 16.68mA 6.77mA 31.41mA -600.00mV 19.97mA 12.32mA 27.59mA -500.00mV 16.94mA 12.65mA 23.02mA -400.00mV 13.57mA 10.27mA 18.43mA -300.00mV 10.18mA 7.71mA 13.83mA -200.00mV 6.78mA 5.13mA 9.22mA -100.00mV 3.39mA 2.56mA 4.60mA 0.00V -11.95pA -13.37pA -11.73pA 100.00mV -3.34mA -2.52mA -4.54mA 200.00mV -6.58mA -4.96mA -8.96mA 300.00mV -9.73mA -7.33mA -13.27mA 400.00mV -12.78mA -9.63mA -17.45mA 500.00mV -15.74mA -11.84mA -21.52mA 600.00mV -18.60mA -13.98mA -25.46mA 700.00mV -21.37mA -16.04mA -29.29mA 800.00mV -24.05mA -18.03mA -32.98mA 900.00mV -26.63mA -19.94mA -36.57mA 1.00V -29.11mA -21.77mA -40.03mA 1.10V -31.51mA -23.53mA -43.37mA 1.20V -33.80mA -25.21mA -46.59mA 1.30V -36.00mA -26.81mA -49.69mA 1.40V -38.10mA -28.34mA -52.67mA 1.50V -40.11mA -29.78mA -55.52mA 1.60V -42.03mA -31.15mA -58.25mA 1.70V -43.84mA -32.44mA -60.87mA 1.80V -45.56mA -33.65mA -63.35mA 1.90V -47.18mA -34.79mA -65.70mA 2.00V -48.70mA -35.85mA -67.93mA 2.10V -50.13mA -36.83mA -70.04mA 2.20V -51.45mA -37.73mA -72.02mA 2.30V -52.68mA -38.55mA -73.87mA 2.40V -53.81mA -39.30mA -75.60mA 2.50V -54.84mA -39.96mA -77.21mA 2.60V -55.78mA -40.55mA -78.68mA 2.70V -56.61mA -41.06mA -80.03mA 2.80V -57.35mA -41.49mA -81.25mA 2.90V -57.99mA -41.85mA -82.34mA 3.00V -58.53mA -42.12mA -83.31mA 3.10V -58.97mA -42.31mA -84.14mA 3.20V -59.31mA -42.44mA -84.85mA 3.30V -59.55mA -43.06mA -85.43mA 3.40V -59.69mA -43.45mA -85.88mA 3.50V -60.59mA -43.74mA -86.21mA 3.60V -61.11mA -44.00mA -86.40mA 3.70V -61.52mA -44.23mA -87.68mA 3.80V -61.87mA -44.45mA -88.43mA 3.90V -62.19mA -44.65mA -89.01mA 4.00V -62.49mA -44.84mA -89.51mA 4.10V -62.77mA -45.03mA -89.97mA 4.20V -63.03mA -45.21mA -90.39mA 4.30V -63.29mA -45.38mA -90.78mA 4.40V -63.53mA -45.55mA -91.16mA 4.50V -63.77mA -45.71mA -91.52mA 4.60V -64.00mA -45.88mA -91.87mA 4.70V -64.23mA -46.03mA -92.21mA 4.80V -64.45mA -46.19mA -92.54mA 4.90V -64.67mA -46.34mA -92.86mA 5.00V -64.88mA -46.49mA -93.17mA 10.00V -73.72mA -52.91mA -105.74mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 5.54A 5.33A 5.74A -4.80V 5.28A 5.08A 5.46A -4.60V 5.01A 4.83A 5.19A -4.40V 4.75A 4.58A 4.91A -4.20V 4.48A 4.33A 4.63A -4.00V 4.22A 4.08A 4.35A -3.80V 3.95A 3.83A 4.07A -3.60V 3.69A 3.58A 3.80A -3.40V 3.42A 3.33A 3.52A -3.20V 3.16A 3.08A 3.24A -3.00V 2.90A 2.83A 2.96A -2.80V 2.63A 2.58A 2.69A -2.60V 2.37A 2.33A 2.41A -2.40V 2.11A 2.08A 2.13A -2.20V 1.85A 1.83A 1.86A -2.00V 1.59A 1.58A 1.58A -1.95V 1.52A 1.52A 1.52A -1.90V 1.46A 1.46A 1.45A -1.85V 1.39A 1.40A 1.38A -1.80V 1.33A 1.34A 1.31A -1.75V 1.26A 1.27A 1.24A -1.70V 1.20A 1.21A 1.17A -1.65V 1.13A 1.15A 1.11A -1.60V 1.07A 1.09A 1.04A -1.55V 1.00A 1.03A 970.41mA -1.50V 939.30mA 969.08mA 902.71mA -1.45V 875.35mA 908.47mA 835.37mA -1.40V 811.40mA 847.86mA 768.03mA -1.35V 747.89mA 787.64mA 701.18mA -1.30V 684.39mA 727.43mA 634.33mA -1.25V 621.49mA 667.75mA 568.19mA -1.20V 558.60mA 608.07mA 502.05mA -1.15V 496.60mA 549.12mA 436.99mA -1.10V 434.59mA 490.18mA 371.93mA -1.05V 373.99mA 432.33mA 308.77mA -1.00V 313.40mA 374.48mA 245.61mA -950.00mV 255.32mA 318.40mA 186.44mA -900.00mV 197.25mA 262.31mA 127.27mA -850.00mV 144.71mA 209.48mA 79.83mA -800.00mV 92.17mA 156.64mA 32.38mA -750.00mV 55.33mA 111.07mA 16.79mA -700.00mV 18.49mA 65.49mA 1.19mA -650.00mV 9.65mA 38.30mA 604.77uA -600.00mV 820.15uA 11.11mA 17.65uA -550.00mV 421.62uA 5.87mA 8.95uA -500.00mV 23.10uA 640.43uA 252.29nA -450.00mV 11.87uA 334.72uA 127.92nA -400.00mV 637.19nA 29.00uA 3.56nA -350.00mV 327.35nA 15.15uA 1.77nA -300.00mV 17.52nA 1.29uA -18.28pA -250.00mV 8.97nA 676.52nA -32.21pA -200.00mV 422.20pA 58.24nA -46.13pA -150.00mV 194.60pA 30.65nA -55.98pA -100.00mV -32.99pA 3.06nA -65.82pA -50.00mV -44.74pA 1.83nA -54.23pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 1.59V/1.16ns 1.28V/1.34ns 1.95V/953.37ps dV/dt_f 1.87V/1.32ns 1.54V/1.44ns 2.20V/1.15ns | |********************************************************************* | [Model] PSCI00000A0S2AZKNUC Model_type Input | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -6.39A -6.15A -6.62A -4.80V -6.08A -5.86A -6.30A -4.60V -5.78A -5.57A -5.98A -4.40V -5.47A -5.28A -5.66A -4.20V -5.16A -4.99A -5.34A -4.00V -4.86A -4.70A -5.02A -3.80V -4.55A -4.41A -4.69A -3.60V -4.25A -4.12A -4.37A -3.40V -3.95A -3.83A -4.05A -3.20V -3.64A -3.54A -3.73A -3.00V -3.34A -3.25A -3.41A -2.80V -3.03A -2.97A -3.09A -2.60V -2.73A -2.68A -2.78A -2.40V -2.43A -2.39A -2.46A -2.20V -2.13A -2.10A -2.14A -2.00V -1.82A -1.82A -1.82A -1.95V -1.75A -1.75A -1.74A -1.90V -1.67A -1.68A -1.66A -1.85V -1.60A -1.61A -1.59A -1.80V -1.52A -1.54A -1.51A -1.75V -1.45A -1.46A -1.43A -1.70V -1.38A -1.39A -1.35A -1.65V -1.30A -1.32A -1.27A -1.60V -1.23A -1.25A -1.19A -1.55V -1.15A -1.18A -1.11A -1.50V -1.08A -1.11A -1.04A -1.45V -1.00A -1.04A -958.89mA -1.40V -930.54mA -972.00mA -881.21mA -1.35V -857.28mA -902.55mA -804.10mA -1.30V -784.03mA -833.09mA -726.98mA -1.25V -711.49mA -764.27mA -650.70mA -1.20V -638.96mA -695.44mA -574.42mA -1.15V -567.47mA -627.47mA -499.41mA -1.10V -495.97mA -559.51mA -424.40mA -1.05V -426.14mA -492.83mA -351.62mA -1.00V -356.30mA -426.15mA -278.84mA -950.00mV -289.46mA -361.56mA -210.81mA -900.00mV -222.62mA -296.98mA -142.78mA -850.00mV -162.40mA -236.26mA -88.87mA -800.00mV -102.18mA -175.55mA -34.96mA -750.00mV -60.85mA -123.57mA -18.20mA -700.00mV -19.53mA -71.60mA -1.43mA -650.00mV -10.26mA -41.58mA -841.67uA -600.00mV -984.93uA -11.56mA -249.86uA -550.00mV -583.77uA -6.16mA -240.94uA -500.00mV -182.61uA -757.23uA -232.02uA -450.00mV -171.16uA -449.64uA -231.85uA -400.00mV -159.72uA -142.06uA -231.69uA -350.00mV -159.36uA -127.98uA -231.65uA -300.00mV -159.01uA -113.91uA -231.62uA -250.00mV -158.98uA -113.25uA -231.59uA -200.00mV -158.95uA -112.59uA -231.56uA -150.00mV -158.92uA -112.54uA -231.53uA -100.00mV -158.90uA -112.49uA -231.49uA -50.00mV -158.88uA -112.47uA -231.46uA 0.00V -158.86uA -112.46uA -231.43uA 5.00V 0.00nA 0.00uA 0.00uA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 11.08A 10.67A 11.48A -4.80V 10.55A 10.16A 10.93A -4.60V 10.02A 9.66A 10.37A -4.40V 9.49A 9.16A 9.81A -4.20V 8.96A 8.66A 9.26A -4.00V 8.43A 8.15A 8.70A -3.80V 7.91A 7.65A 8.15A -3.60V 7.38A 7.15A 7.59A -3.40V 6.85A 6.65A 7.04A -3.20V 6.32A 6.15A 6.48A -3.00V 5.79A 5.65A 5.93A -2.80V 5.27A 5.15A 5.37A -2.60V 4.74A 4.65A 4.82A -2.40V 4.22A 4.16A 4.27A -2.20V 3.70A 3.66A 3.72A -2.00V 3.17A 3.16A 3.17A -1.95V 3.04A 3.04A 3.03A -1.90V 2.91A 2.92A 2.89A -1.85V 2.78A 2.80A 2.76A -1.80V 2.65A 2.67A 2.62A -1.75V 2.52A 2.55A 2.48A -1.70V 2.39A 2.43A 2.35A -1.65V 2.26A 2.30A 2.21A -1.60V 2.14A 2.18A 2.08A -1.55V 2.01A 2.06A 1.94A -1.50V 1.88A 1.94A 1.81A -1.45V 1.75A 1.82A 1.67A -1.40V 1.62A 1.70A 1.54A -1.35V 1.50A 1.58A 1.40A -1.30V 1.37A 1.45A 1.27A -1.25V 1.24A 1.34A 1.14A -1.20V 1.12A 1.22A 1.00A -1.15V 993.20mA 1.10A 873.99mA -1.10V 869.19mA 980.36mA 743.87mA -1.05V 747.99mA 864.66mA 617.55mA -1.00V 626.80mA 748.96mA 491.23mA -950.00mV 510.66mA 636.80mA 372.89mA -900.00mV 394.51mA 524.63mA 254.55mA -850.00mV 289.44mA 418.96mA 159.68mA -800.00mV 184.36mA 313.30mA 64.81mA -750.00mV 110.69mA 222.15mA 33.64mA -700.00mV 37.02mA 131.01mA 2.48mA -650.00mV 19.36mA 76.63mA 1.30mA -600.00mV 1.70mA 22.24mA 117.42uA -550.00mV 897.16uA 11.78mA 93.27uA -500.00mV 95.90uA 1.32mA 69.12uA -450.00mV 68.51uA 702.53uA 62.05uA -400.00mV 41.12uA 87.81uA 54.98uA -350.00mV 35.53uA 56.40uA 48.13uA -300.00mV 29.94uA 24.98uA 41.27uA -250.00mV 24.94uA 20.01uA 34.40uA -200.00mV 19.94uA 15.04uA 27.53uA -150.00mV 14.95uA 11.25uA 20.64uA -100.00mV 9.96uA 7.46uA 13.76uA -50.00mV 4.98uA 3.73uA 6.88uA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Model] PSCI00000A0S2AZZVTC Model_type Input | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -12.16A -11.69A -12.61A -4.80V -11.57A -11.14A -11.99A -4.60V -10.99A -10.58A -11.38A -4.40V -10.40A -10.03A -10.77A -4.20V -9.82A -9.48A -10.15A -4.00V -9.24A -8.92A -9.54A -3.80V -8.65A -8.37A -8.93A -3.60V -8.07A -7.82A -8.32A -3.40V -7.49A -7.27A -7.70A -3.20V -6.91A -6.71A -7.09A -3.00V -6.33A -6.16A -6.48A -2.80V -5.75A -5.61A -5.87A -2.60V -5.17A -5.06A -5.26A -2.40V -4.59A -4.51A -4.65A -2.20V -4.01A -3.97A -4.04A -2.00V -3.44A -3.42A -3.44A -1.95V -3.29A -3.29A -3.29A -1.90V -3.15A -3.15A -3.14A -1.85V -3.01A -3.01A -2.99A -1.80V -2.86A -2.88A -2.83A -1.75V -2.72A -2.74A -2.68A -1.70V -2.58A -2.61A -2.53A -1.65V -2.44A -2.47A -2.38A -1.60V -2.29A -2.34A -2.23A -1.55V -2.15A -2.20A -2.09A -1.50V -2.01A -2.07A -1.94A -1.45V -1.87A -1.94A -1.79A -1.40V -1.73A -1.80A -1.64A -1.35V -1.59A -1.67A -1.49A -1.30V -1.45A -1.54A -1.34A -1.25V -1.31A -1.41A -1.20A -1.20V -1.17A -1.27A -1.05A -1.15V -1.04A -1.15A -910.69mA -1.10V -899.14mA -1.02A -767.78mA -1.05V -766.41mA -889.04mA -629.59mA -1.00V -633.68mA -762.23mA -491.40mA -950.00mV -507.43mA -639.92mA -363.65mA -900.00mV -381.19mA -517.60mA -235.90mA -850.00mV -270.00mA -403.89mA -140.95mA -800.00mV -158.81mA -290.19mA -46.00mA -750.00mV -90.91mA -196.83mA -23.61mA -700.00mV -23.01mA -103.47mA -1.22mA -650.00mV -11.92mA -58.08mA -621.29uA -600.00mV -836.80uA -12.69mA -18.49uA -550.00mV -430.39uA -6.67mA -9.40uA -500.00mV -23.98uA -651.88uA -318.99nA -450.00mV -12.36uA -340.92uA -163.57nA -400.00mV -733.79nA -29.96uA -8.15nA -350.00mV -380.25nA -15.69uA -4.17nA -300.00mV -26.71nA -1.43uA -187.16pA -250.00mV -13.92nA -749.57nA -58.24pA -200.00mV -1.12nA -73.46nA 70.68pA -150.00mV -540.37pA -38.94nA 100.97pA -100.00mV 38.58pA -4.43nA 131.25pA -50.00mV 73.40pA -2.43nA 103.94pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 10.88A 10.47A 11.29A -4.80V 10.36A 9.98A 10.74A -4.60V 9.84A 9.48A 10.19A -4.40V 9.32A 8.98A 9.64A -4.20V 8.80A 8.49A 9.09A -4.00V 8.27A 7.99A 8.54A -3.80V 7.75A 7.50A 8.00A -3.60V 7.23A 7.00A 7.45A -3.40V 6.71A 6.51A 6.90A -3.20V 6.19A 6.02A 6.35A -3.00V 5.67A 5.52A 5.81A -2.80V 5.15A 5.03A 5.26A -2.60V 4.63A 4.54A 4.71A -2.40V 4.11A 4.05A 4.17A -2.20V 3.60A 3.56A 3.63A -2.00V 3.08A 3.07A 3.08A -1.95V 2.95A 2.95A 2.95A -1.90V 2.83A 2.83A 2.81A -1.85V 2.70A 2.71A 2.68A -1.80V 2.57A 2.58A 2.54A -1.75V 2.44A 2.46A 2.41A -1.70V 2.31A 2.34A 2.27A -1.65V 2.19A 2.22A 2.14A -1.60V 2.06A 2.10A 2.01A -1.55V 1.93A 1.98A 1.87A -1.50V 1.81A 1.86A 1.74A -1.45V 1.68A 1.74A 1.61A -1.40V 1.55A 1.62A 1.47A -1.35V 1.43A 1.50A 1.34A -1.30V 1.30A 1.38A 1.21A -1.25V 1.18A 1.27A 1.08A -1.20V 1.06A 1.15A 949.45mA -1.15V 933.90mA 1.03A 821.50mA -1.10V 811.95mA 917.10mA 693.56mA -1.05V 693.06mA 803.54mA 569.76mA -1.00V 574.18mA 689.98mA 445.96mA -950.00mV 460.97mA 580.35mA 331.28mA -900.00mV 347.76mA 470.72mA 216.59mA -850.00mV 247.62mA 368.59mA 130.29mA -800.00mV 147.47mA 266.46mA 43.99mA -750.00mV 84.94mA 181.92mA 22.60mA -700.00mV 22.40mA 97.38mA 1.21mA -650.00mV 11.62mA 54.93mA 615.47uA -600.00mV 829.14uA 12.49mA 17.66uA -550.00mV 426.12uA 6.57mA 8.96uA -500.00mV 23.11uA 645.42uA 252.42nA -450.00mV 11.88uA 337.21uA 127.97nA -400.00mV 637.31nA 29.01uA 3.52nA -350.00mV 327.39nA 15.15uA 1.71nA -300.00mV 17.47nA 1.30uA -95.63pA -250.00mV 8.92nA 676.75nA -87.56pA -200.00mV 371.68pA 58.39nA -79.49pA -150.00mV 145.37pA 30.80nA -109.14pA -100.00mV -80.95pA 3.21nA -138.80pA -50.00mV -91.22pA 1.98nA -105.01pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Model] PSCB04041A0S2AZZHIB Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 1.80pF 0.97pF 3.72pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -164.38uA -134.39uA -199.41uA -4.50V -185.87uA -151.49uA -226.18uA -4.00V -213.91uA -173.67uA -261.33uA -3.50V -252.02uA -203.56uA -309.52uA -3.00V -306.83uA -246.05uA -379.66uA -2.50V -392.39uA -311.29uA -491.21uA -2.00V -544.65uA -424.11uA -695.96uA -1.50V -889.90uA -665.66uA -1.19mA -1.40V -1.02mA -751.11uA -1.39mA -1.30V -1.19mA -861.49uA -1.66mA -1.20V -1.43mA -1.01mA -2.07mA -1.10V -1.79mA -1.22mA -2.73mA -1.00V -2.38mA -1.53mA -3.96mA -900.00mV -3.48mA -2.05mA -6.89mA -800.00mV -6.07mA -3.02mA -16.26mA -700.00mV -13.04mA -5.24mA -26.28mA -600.00mV -17.44mA -9.97mA -23.72mA -500.00mV -15.20mA -11.46mA -20.11mA -400.00mV -12.36mA -9.55mA -16.36mA -300.00mV -9.42mA -7.27mA -12.48mA -200.00mV -6.38mA -4.92mA -8.47mA -100.00mV -3.24mA -2.50mA -4.31mA 0.00V 1.38pA 4.12pA -5.91pA 100.00mV 3.20mA 2.47mA 4.27mA 200.00mV 6.24mA 4.80mA 8.30mA 300.00mV 9.10mA 7.01mA 12.10mA 400.00mV 11.81mA 9.10mA 15.68mA 500.00mV 14.35mA 11.06mA 19.05mA 600.00mV 16.73mA 12.91mA 22.21mA 700.00mV 18.98mA 14.64mA 25.16mA 800.00mV 21.08mA 16.26mA 27.91mA 900.00mV 23.04mA 17.77mA 30.49mA 1.00V 24.86mA 19.18mA 32.88mA 1.10V 26.55mA 20.48mA 35.10mA 1.20V 28.11mA 21.67mA 37.14mA 1.30V 29.54mA 22.77mA 39.02mA 1.40V 30.86mA 23.77mA 40.74mA 1.50V 32.05mA 24.68mA 42.30mA 1.60V 33.14mA 25.49mA 43.72mA 1.70V 34.10mA 26.21mA 45.00mA 1.80V 34.95mA 26.85mA 46.13mA 1.90V 35.70mA 27.40mA 47.12mA 2.00V 36.35mA 27.87mA 47.98mA 2.10V 36.89mA 28.26mA 48.71mA 2.20V 37.34mA 28.57mA 49.32mA 2.30V 37.69mA 28.80mA 49.82mA 2.40V 37.95mA 28.96mA 50.18mA 2.50V 38.07mA 29.02mA 50.30mA 2.60V 38.10mA 29.04mA 50.33mA 2.70V 38.12mA 29.05mA 50.37mA 2.80V 38.15mA 29.07mA 50.41mA 2.90V 38.17mA 29.09mA 50.44mA 3.00V 38.20mA 29.11mA 50.48mA 3.10V 38.22mA 29.13mA 50.52mA 3.20V 38.25mA 29.14mA 50.55mA 3.30V 38.27mA 29.16mA 50.59mA 3.40V 38.30mA 29.18mA 50.63mA 3.50V 38.32mA 29.20mA 50.67mA 3.60V 38.35mA 29.22mA 50.70mA 3.70V 38.37mA 29.23mA 50.74mA 3.80V 38.40mA 29.25mA 50.78mA 3.90V 38.42mA 29.27mA 50.81mA 4.00V 38.45mA 29.29mA 50.85mA 4.10V 38.48mA 29.31mA 50.89mA 4.20V 38.50mA 29.32mA 50.92mA 4.30V 38.53mA 29.34mA 50.96mA 4.40V 38.55mA 29.36mA 51.00mA 4.50V 38.58mA 29.38mA 51.03mA 4.60V 38.60mA 29.40mA 51.07mA 4.70V 38.63mA 29.41mA 51.11mA 4.80V 38.65mA 29.43mA 51.14mA 4.90V 38.68mA 29.45mA 51.18mA 5.00V 38.70mA 29.47mA 51.22mA 10.00V 39.96mA 30.38mA 53.05mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -2.52A -2.42A -2.61A -4.80V -2.40A -2.31A -2.48A -4.60V -2.28A -2.20A -2.35A -4.40V -2.16A -2.08A -2.23A -4.20V -2.04A -1.97A -2.10A -4.00V -1.92A -1.86A -1.98A -3.80V -1.80A -1.74A -1.85A -3.60V -1.68A -1.63A -1.73A -3.40V -1.56A -1.52A -1.60A -3.20V -1.44A -1.40A -1.48A -3.00V -1.32A -1.29A -1.35A -2.80V -1.20A -1.18A -1.23A -2.60V -1.08A -1.07A -1.10A -2.40V -966.08mA -953.21mA -975.97mA -2.20V -847.79mA -841.05mA -851.49mA -2.00V -729.82mA -729.22mA -727.33mA -1.95V -700.41mA -701.34mA -696.37mA -1.90V -670.99mA -673.45mA -665.41mA -1.85V -641.64mA -645.63mA -634.50mA -1.80V -612.29mA -617.81mA -603.60mA -1.75V -583.01mA -590.06mA -572.78mA -1.70V -553.73mA -562.31mA -541.95mA -1.65V -524.55mA -534.65mA -511.22mA -1.60V -495.36mA -506.99mA -480.49mA -1.55V -466.29mA -479.44mA -449.88mA -1.50V -437.21mA -451.88mA -419.27mA -1.45V -408.28mA -424.46mA -388.81mA -1.40V -379.35mA -397.03mA -358.35mA -1.35V -350.61mA -369.78mA -328.10mA -1.30V -321.87mA -342.52mA -297.85mA -1.25V -293.38mA -315.49mA -267.90mA -1.20V -264.90mA -288.45mA -237.95mA -1.15V -236.78mA -261.73mA -208.44mA -1.10V -208.66mA -235.00mA -178.94mA -1.05V -181.11mA -208.71mA -150.19mA -1.00V -153.56mA -182.43mA -121.45mA -950.00mV -127.00mA -156.84mA -94.25mA -900.00mV -100.44mA -131.26mA -67.05mA -850.00mV -75.94mA -106.91mA -44.05mA -800.00mV -51.43mA -82.56mA -21.05mA -750.00mV -32.50mA -60.83mA -11.10mA -700.00mV -13.56mA -39.09mA -1.15mA -650.00mV -7.18mA -24.03mA -581.73uA -600.00mV -800.60uA -8.97mA -17.79uA -550.00mV -411.92uA -4.80mA -9.03uA -500.00mV -23.25uA -629.79uA -264.95nA -450.00mV -11.95uA -329.47uA -134.69nA -400.00mV -655.61nA -29.15uA -4.44nA -350.00mV -337.45nA -15.24uA -2.24nA -300.00mV -19.29nA -1.32uA -44.82pA -250.00mV -9.93nA -690.39nA 2.19pA -200.00mV -567.12pA -61.08nA 49.20pA -150.00mV -271.09pA -32.16nA 52.45pA -100.00mV 24.94pA -3.25nA 55.69pA -50.00mV 40.87pA -1.87nA 52.21pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 111.98uA 89.44uA 140.21uA -4.50V 126.55uA 100.77uA 158.92uA -4.00V 145.53uA 115.43uA 183.46uA -3.50V 171.31uA 135.19uA 217.08uA -3.00V 208.34uA 163.25uA 265.92uA -2.50V 266.09uA 206.29uA 343.43uA -2.00V 368.67uA 280.68uA 485.24uA -1.50V 600.79uA 439.94uA 826.83uA -1.40V 687.18uA 496.29uA 961.76uA -1.30V 802.22uA 569.07uA 1.15mA -1.20V 963.88uA 667.13uA 1.43mA -1.10V 1.20mA 804.64uA 1.87mA -1.00V 1.59mA 1.01mA 2.69mA -900.00mV 2.33mA 1.35mA 4.60mA -800.00mV 4.04mA 2.00mA 10.76mA -700.00mV 8.73mA 3.48mA 18.20mA -600.00mV 11.61mA 6.60mA 16.22mA -500.00mV 9.96mA 7.38mA 13.54mA -400.00mV 7.98mA 6.04mA 10.84mA -300.00mV 5.99mA 4.53mA 8.13mA -200.00mV 3.99mA 3.02mA 5.42mA -100.00mV 1.99mA 1.51mA 2.71mA 0.00V -6.81pA -7.29pA -2.10pA 100.00mV -1.96mA -1.48mA -2.67mA 200.00mV -3.87mA -2.92mA -5.27mA 300.00mV -5.72mA -4.31mA -7.80mA 400.00mV -7.52mA -5.66mA -10.26mA 500.00mV -9.26mA -6.96mA -12.66mA 600.00mV -10.94mA -8.22mA -14.98mA 700.00mV -12.57mA -9.44mA -17.23mA 800.00mV -14.14mA -10.61mA -19.40mA 900.00mV -15.66mA -11.73mA -21.51mA 1.00V -17.12mA -12.81mA -23.54mA 1.10V -18.53mA -13.84mA -25.51mA 1.20V -19.88mA -14.83mA -27.40mA 1.30V -21.17mA -15.77mA -29.22mA 1.40V -22.41mA -16.66mA -30.97mA 1.50V -23.59mA -17.52mA -32.65mA 1.60V -24.72mA -18.32mA -34.25mA 1.70V -25.78mA -19.07mA -35.79mA 1.80V -26.79mA -19.79mA -37.25mA 1.90V -27.74mA -20.46mA -38.63mA 2.00V -28.64mA -21.08mA -39.94mA 2.10V -29.47mA -21.65mA -41.18mA 2.20V -30.25mA -22.18mA -42.35mA 2.30V -30.98mA -22.67mA -43.43mA 2.40V -31.64mA -23.11mA -44.45mA 2.50V -32.25mA -23.50mA -45.39mA 2.60V -32.79mA -23.84mA -46.26mA 2.70V -33.28mA -24.14mA -47.05mA 2.80V -33.72mA -24.40mA -47.76mA 2.90V -34.09mA -24.60mA -48.41mA 3.00V -34.41mA -24.76mA -48.97mA 3.10V -34.66mA -24.88mA -49.46mA 3.20V -34.86mA -24.95mA -49.88mA 3.30V -35.00mA -25.32mA -50.22mA 3.40V -35.09mA -25.54mA -50.48mA 3.50V -35.62mA -25.72mA -50.67mA 3.60V -35.93mA -25.87mA -50.78mA 3.70V -36.16mA -26.00mA -51.54mA 3.80V -36.37mA -26.13mA -51.97mA 3.90V -36.56mA -26.25mA -52.32mA 4.00V -36.73mA -26.36mA -52.61mA 4.10V -36.90mA -26.47mA -52.88mA 4.20V -37.05mA -26.58mA -53.13mA 4.30V -37.20mA -26.68mA -53.36mA 4.40V -37.35mA -26.78mA -53.58mA 4.50V -37.49mA -26.87mA -53.79mA 4.60V -37.62mA -26.97mA -54.00mA 4.70V -37.76mA -27.06mA -54.19mA 4.80V -37.89mA -27.15mA -54.39mA 4.90V -38.01mA -27.24mA -54.58mA 5.00V -38.14mA -27.33mA -54.76mA 10.00V -43.33mA -31.11mA -62.14mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 3.36A 3.24A 3.48A -4.80V 3.20A 3.09A 3.31A -4.60V 3.04A 2.93A 3.15A -4.40V 2.88A 2.78A 2.98A -4.20V 2.72A 2.63A 2.81A -4.00V 2.56A 2.48A 2.64A -3.80V 2.40A 2.33A 2.47A -3.60V 2.24A 2.18A 2.31A -3.40V 2.08A 2.02A 2.14A -3.20V 1.92A 1.87A 1.97A -3.00V 1.76A 1.72A 1.80A -2.80V 1.60A 1.57A 1.63A -2.60V 1.45A 1.42A 1.47A -2.40V 1.29A 1.27A 1.30A -2.20V 1.13A 1.12A 1.13A -2.00V 970.62mA 969.20mA 967.99mA -1.95V 931.25mA 931.88mA 926.54mA -1.90V 891.87mA 894.56mA 885.10mA -1.85V 852.59mA 857.33mA 843.74mA -1.80V 813.30mA 820.09mA 802.38mA -1.75V 774.11mA 782.95mA 761.12mA -1.70V 734.93mA 745.82mA 719.86mA -1.65V 695.87mA 708.80mA 678.73mA -1.60V 656.81mA 671.78mA 637.60mA -1.55V 617.90mA 634.91mA 596.63mA -1.50V 578.99mA 598.03mA 555.67mA -1.45V 540.28mA 561.34mA 514.91mA -1.40V 501.57mA 524.64mA 474.15mA -1.35V 463.12mA 488.18mA 433.67mA -1.30V 424.66mA 451.71mA 393.20mA -1.25V 386.56mA 415.56mA 353.13mA -1.20V 348.46mA 379.40mA 313.07mA -1.15V 310.87mA 343.67mA 273.63mA -1.10V 273.28mA 307.93mA 234.18mA -1.05V 236.48mA 272.81mA 195.80mA -1.00V 199.68mA 237.70mA 157.42mA -950.00mV 164.27mA 203.56mA 121.22mA -900.00mV 128.87mA 169.42mA 85.02mA -850.00mV 96.41mA 137.05mA 54.94mA -800.00mV 63.95mA 104.67mA 24.85mA -750.00mV 39.65mA 76.10mA 13.01mA -700.00mV 15.35mA 47.52mA 1.17mA -650.00mV 8.08mA 28.66mA 591.56uA -600.00mV 808.76uA 9.80mA 17.64uA -550.00mV 415.93uA 5.22mA 8.95uA -500.00mV 23.09uA 634.03uA 252.20nA -450.00mV 11.86uA 331.51uA 127.87nA -400.00mV 637.10nA 28.98uA 3.55nA -350.00mV 327.31nA 15.14uA 1.77nA -300.00mV 17.51nA 1.29uA -11.87pA -250.00mV 8.97nA 676.42nA -30.77pA -200.00mV 421.92pA 58.19nA -49.66pA -150.00mV 194.51pA 30.60nA -54.56pA -100.00mV -32.90pA 3.01nA -59.45pA -50.00mV -44.86pA 1.78nA -52.90pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 1.05V/1.03ns 806.82mV/1.22ns 1.39V/611.61ps dV/dt_f 1.13V/1.24ns 903.35mV/1.41ns 1.42V/939.33ps | |********************************************************************* | [Model] PSCB16161A0S2AZZRUC Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -602.67uA -494.84uA -728.25uA -4.50V -681.93uA -558.25uA -826.48uA -4.00V -785.43uA -640.56uA -955.57uA -3.50V -926.35uA -751.74uA -1.13mA -3.00V -1.13mA -910.23uA -1.39mA -2.50V -1.45mA -1.15mA -1.80mA -2.00V -2.02mA -1.58mA -2.57mA -1.50V -3.33mA -2.50mA -4.44mA -1.40V -3.82mA -2.83mA -5.19mA -1.30V -4.48mA -3.26mA -6.24mA -1.20V -5.43mA -3.84mA -7.83mA -1.10V -6.84mA -4.67mA -10.43mA -1.00V -9.21mA -5.93mA -15.43mA -900.00mV -13.79mA -8.05mA -27.84mA -800.00mV -25.05mA -12.19mA -67.49mA -700.00mV -53.38mA -21.96mA -95.94mA -600.00mV -63.55mA -39.96mA -85.32mA -500.00mV -54.69mA -41.71mA -72.32mA -400.00mV -44.46mA -34.36mA -58.84mA -300.00mV -33.87mA -26.17mA -44.88mA -200.00mV -22.93mA -17.70mA -30.44mA -100.00mV -11.65mA -8.98mA -15.49mA 0.00V 6.19pA 20.31pA 7.59pA 100.00mV 11.52mA 8.87mA 15.33mA 200.00mV 22.42mA 17.27mA 29.82mA 300.00mV 32.73mA 25.21mA 43.50mA 400.00mV 42.46mA 32.72mA 56.38mA 500.00mV 51.61mA 39.79mA 68.49mA 600.00mV 60.18mA 46.44mA 79.87mA 700.00mV 68.26mA 52.67mA 90.49mA 800.00mV 75.82mA 58.50mA 100.38mA 900.00mV 82.88mA 63.94mA 109.65mA 1.00V 89.44mA 68.99mA 118.26mA 1.10V 95.52mA 73.67mA 126.24mA 1.20V 101.13mA 77.98mA 133.60mA 1.30V 106.29mA 81.94mA 140.37mA 1.40V 111.01mA 85.55mA 146.56mA 1.50V 115.31mA 88.81mA 152.19mA 1.60V 119.23mA 91.73mA 157.28mA 1.70V 122.70mA 94.33mA 161.91mA 1.80V 125.76mA 96.63mA 165.97mA 1.90V 128.46mA 98.62mA 169.52mA 2.00V 130.78mA 100.31mA 172.63mA 2.10V 132.74mA 101.71mA 175.27mA 2.20V 134.36mA 102.83mA 177.48mA 2.30V 135.63mA 103.66mA 179.26mA 2.40V 136.55mA 104.21mA 180.55mA 2.50V 137.02mA 104.44mA 181.00mA 2.60V 137.11mA 104.50mA 181.13mA 2.70V 137.20mA 104.56mA 181.26mA 2.80V 137.29mA 104.63mA 181.40mA 2.90V 137.38mA 104.69mA 181.53mA 3.00V 137.47mA 104.76mA 181.66mA 3.10V 137.56mA 104.82mA 181.80mA 3.20V 137.65mA 104.89mA 181.93mA 3.30V 137.74mA 104.95mA 182.06mA 3.40V 137.83mA 105.02mA 182.19mA 3.50V 137.92mA 105.08mA 182.33mA 3.60V 138.01mA 105.15mA 182.46mA 3.70V 138.11mA 105.21mA 182.59mA 3.80V 138.20mA 105.28mA 182.72mA 3.90V 138.29mA 105.34mA 182.86mA 4.00V 138.38mA 105.41mA 182.99mA 4.10V 138.47mA 105.47mA 183.12mA 4.20V 138.56mA 105.54mA 183.26mA 4.30V 138.65mA 105.60mA 183.39mA 4.40V 138.74mA 105.67mA 183.52mA 4.50V 138.83mA 105.73mA 183.65mA 4.60V 138.92mA 105.80mA 183.79mA 4.70V 139.01mA 105.86mA 183.92mA 4.80V 139.10mA 105.93mA 184.05mA 4.90V 139.19mA 105.99mA 184.18mA 5.00V 139.28mA 106.06mA 184.31mA 10.00V 143.82mA 109.35mA 190.91mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -8.95A -8.62A -9.27A -4.80V -8.52A -8.21A -8.82A -4.60V -8.09A -7.80A -8.37A -4.40V -7.67A -7.40A -7.93A -4.20V -7.24A -6.99A -7.48A -4.00V -6.81A -6.59A -7.03A -3.80V -6.39A -6.19A -6.58A -3.60V -5.96A -5.78A -6.13A -3.40V -5.54A -5.38A -5.69A -3.20V -5.11A -4.97A -5.24A -3.00V -4.69A -4.57A -4.79A -2.80V -4.26A -4.17A -4.34A -2.60V -3.84A -3.77A -3.90A -2.40V -3.41A -3.37A -3.45A -2.20V -2.99A -2.97A -3.01A -2.00V -2.57A -2.57A -2.57A -1.95V -2.47A -2.47A -2.46A -1.90V -2.36A -2.37A -2.35A -1.85V -2.26A -2.27A -2.24A -1.80V -2.15A -2.17A -2.12A -1.75V -2.05A -2.07A -2.01A -1.70V -1.94A -1.97A -1.90A -1.65V -1.84A -1.87A -1.80A -1.60V -1.73A -1.77A -1.69A -1.55V -1.63A -1.67A -1.58A -1.50V -1.53A -1.58A -1.47A -1.45V -1.42A -1.48A -1.36A -1.40V -1.32A -1.38A -1.25A -1.35V -1.22A -1.28A -1.14A -1.30V -1.12A -1.19A -1.03A -1.25V -1.01A -1.09A -927.24mA -1.20V -913.06mA -994.01mA -820.49mA -1.15V -812.95mA -898.85mA -715.45mA -1.10V -712.84mA -803.68mA -610.41mA -1.05V -614.93mA -710.22mA -508.33mA -1.00V -517.02mA -616.77mA -406.24mA -950.00mV -423.02mA -526.06mA -310.33mA -900.00mV -329.03mA -435.35mA -214.41mA -850.00mV -243.48mA -349.64mA -136.23mA -800.00mV -157.94mA -263.93mA -58.06mA -750.00mV -96.13mA -189.21mA -30.21mA -700.00mV -34.32mA -114.50mA -2.37mA -650.00mV -17.98mA -67.83mA -1.20mA -600.00mV -1.64mA -21.16mA -35.86uA -550.00mV -841.55uA -11.22mA -18.20uA -500.00mV -46.79uA -1.28mA -550.53nA -450.00mV -24.07uA -669.38uA -280.43nA -400.00mV -1.34uA -58.64uA -10.32nA -350.00mV -691.24nA -30.66uA -5.24nA -300.00mV -41.44nA -2.68uA -171.96pA -250.00mV -21.40nA -1.40uA -45.52pA -200.00mV -1.37nA -126.91nA 80.91pA -150.00mV -671.24pA -66.94nA 97.41pA -100.00mV 27.63pA -6.96nA 113.90pA -50.00mV 68.77pA -3.98nA 99.05pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 388.20uA 311.29uA 484.34uA -4.50V 438.92uA 350.92uA 549.23uA -4.00V 505.10uA 402.32uA 634.44uA -3.50V 595.13uA 471.67uA 751.28uA -3.00V 724.73uA 570.44uA 921.41uA -2.50V 927.46uA 722.40uA 1.19mA -2.00V 1.29mA 986.53uA 1.69mA -1.50V 2.12mA 1.56mA 2.90mA -1.40V 2.43mA 1.76mA 3.38mA -1.30V 2.85mA 2.03mA 4.06mA -1.20V 3.44mA 2.39mA 5.07mA -1.10V 4.32mA 2.90mA 6.71mA -1.00V 5.79mA 3.67mA 9.81mA -900.00mV 8.62mA 4.98mA 17.30mA -800.00mV 15.51mA 7.53mA 41.83mA -700.00mV 33.37mA 13.55mA 62.81mA -600.00mV 39.93mA 24.64mA 55.18mA -500.00mV 33.88mA 25.31mA 46.05mA -400.00mV 27.14mA 20.53mA 36.86mA -300.00mV 20.36mA 15.41mA 27.65mA -200.00mV 13.57mA 10.27mA 18.43mA -100.00mV 6.78mA 5.13mA 9.21mA 0.00V -23.91pA -26.73pA -23.46pA 100.00mV -6.67mA -5.04mA -9.08mA 200.00mV -13.16mA -9.93mA -17.92mA 300.00mV -19.45mA -14.67mA -26.53mA 400.00mV -25.56mA -19.25mA -34.90mA 500.00mV -31.48mA -23.68mA -43.03mA 600.00mV -37.20mA -27.96mA -50.93mA 700.00mV -42.74mA -32.09mA -58.57mA 800.00mV -48.09mA -36.06mA -65.96mA 900.00mV -53.26mA -39.88mA -73.13mA 1.00V -58.23mA -43.55mA -80.06mA 1.10V -63.01mA -47.06mA -86.75mA 1.20V -67.60mA -50.42mA -93.19mA 1.30V -72.00mA -53.62mA -99.38mA 1.40V -76.21mA -56.67mA -105.34mA 1.50V -80.22mA -59.57mA -111.04mA 1.60V -84.06mA -62.30mA -116.50mA 1.70V -87.69mA -64.87mA -121.74mA 1.80V -91.11mA -67.30mA -126.70mA 1.90V -94.35mA -69.57mA -131.40mA 2.00V -97.40mA -71.69mA -135.86mA 2.10V -100.24mA -73.65mA -140.08mA 2.20V -102.90mA -75.46mA -144.04mA 2.30V -105.35mA -77.10mA -147.75mA 2.40V -107.62mA -78.59mA -151.21mA 2.50V -109.68mA -79.93mA -154.41mA 2.60V -111.55mA -81.11mA -157.36mA 2.70V -113.22mA -82.13mA -160.06mA 2.80V -114.69mA -82.99mA -162.50mA 2.90V -115.97mA -83.69mA -164.69mA 3.00V -117.05mA -84.24mA -166.62mA 3.10V -117.93mA -84.63mA -168.29mA 3.20V -118.61mA -84.88mA -169.70mA 3.30V -119.09mA -86.12mA -170.86mA 3.40V -119.38mA -86.89mA -171.76mA 3.50V -121.19mA -87.48mA -172.42mA 3.60V -122.22mA -88.00mA -172.80mA 3.70V -123.04mA -88.46mA -175.37mA 3.80V -123.74mA -88.89mA -176.86mA 3.90V -124.38mA -89.30mA -178.02mA 4.00V -124.97mA -89.68mA -179.03mA 4.10V -125.53mA -90.06mA -179.93mA 4.20V -126.06mA -90.41mA -180.78mA 4.30V -126.57mA -90.76mA -181.57mA 4.40V -127.07mA -91.10mA -182.32mA 4.50V -127.54mA -91.43mA -183.05mA 4.60V -128.01mA -91.75mA -183.74mA 4.70V -128.46mA -92.07mA -184.42mA 4.80V -128.90mA -92.38mA -185.08mA 4.90V -129.34mA -92.69mA -185.72mA 5.00V -129.77mA -92.99mA -186.34mA 10.00V -147.44mA -105.83mA -211.47mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 11.08A 10.67A 11.48A -4.80V 10.55A 10.16A 10.93A -4.60V 10.02A 9.66A 10.37A -4.40V 9.49A 9.16A 9.81A -4.20V 8.96A 8.66A 9.26A -4.00V 8.43A 8.15A 8.70A -3.80V 7.91A 7.65A 8.15A -3.60V 7.38A 7.15A 7.59A -3.40V 6.85A 6.65A 7.04A -3.20V 6.32A 6.15A 6.48A -3.00V 5.79A 5.65A 5.93A -2.80V 5.27A 5.15A 5.37A -2.60V 4.74A 4.65A 4.82A -2.40V 4.22A 4.16A 4.27A -2.20V 3.70A 3.66A 3.72A -2.00V 3.17A 3.16A 3.17A -1.95V 3.04A 3.04A 3.03A -1.90V 2.91A 2.92A 2.89A -1.85V 2.78A 2.80A 2.76A -1.80V 2.65A 2.67A 2.62A -1.75V 2.52A 2.55A 2.48A -1.70V 2.39A 2.43A 2.35A -1.65V 2.26A 2.30A 2.21A -1.60V 2.14A 2.18A 2.08A -1.55V 2.01A 2.06A 1.94A -1.50V 1.88A 1.94A 1.81A -1.45V 1.75A 1.82A 1.67A -1.40V 1.62A 1.70A 1.54A -1.35V 1.50A 1.58A 1.40A -1.30V 1.37A 1.45A 1.27A -1.25V 1.24A 1.34A 1.14A -1.20V 1.12A 1.22A 1.00A -1.15V 993.19mA 1.10A 873.98mA -1.10V 869.18mA 980.36mA 743.87mA -1.05V 747.99mA 864.66mA 617.54mA -1.00V 626.79mA 748.96mA 491.22mA -950.00mV 510.65mA 636.79mA 372.88mA -900.00mV 394.50mA 524.62mA 254.54mA -850.00mV 289.42mA 418.96mA 159.65mA -800.00mV 184.34mA 313.29mA 64.76mA -750.00mV 110.65mA 222.14mA 33.57mA -700.00mV 36.97mA 130.99mA 2.38mA -650.00mV 19.31mA 76.60mA 1.21mA -600.00mV 1.64mA 22.21mA 35.30uA -550.00mV 843.25uA 11.75mA 17.90uA -500.00mV 46.20uA 1.28mA 504.59nA -450.00mV 23.74uA 669.43uA 255.86nA -400.00mV 1.27uA 58.00uA 7.12nA -350.00mV 654.72nA 30.29uA 3.55nA -300.00mV 35.04nA 2.59uA -28.28pA -250.00mV 17.95nA 1.35uA -56.19pA -200.00mV 852.22pA 116.48nA -84.09pA -150.00mV 396.98pA 61.30nA -103.81pA -100.00mV -58.25pA 6.13nA -123.54pA -50.00mV -81.77pA 3.67nA -100.39pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 2.20V/1.03ns 1.92V/1.28ns 2.49V/617.51ps dV/dt_f 2.46V/1.21ns 2.20V/1.42ns 2.70V/770.73ps | |********************************************************************* | [Model] PSCB16160A0S2AZZRUC Model_type I/O | Vinl = 0.80V Vinh = 2.00V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -602.67uA -494.84uA -728.25uA -4.50V -681.93uA -558.25uA -826.48uA -4.00V -785.43uA -640.56uA -955.57uA -3.50V -926.35uA -751.74uA -1.13mA -3.00V -1.13mA -910.23uA -1.39mA -2.50V -1.45mA -1.15mA -1.80mA -2.00V -2.02mA -1.58mA -2.57mA -1.50V -3.33mA -2.50mA -4.44mA -1.40V -3.82mA -2.83mA -5.19mA -1.30V -4.48mA -3.26mA -6.24mA -1.20V -5.43mA -3.84mA -7.83mA -1.10V -6.84mA -4.67mA -10.43mA -1.00V -9.21mA -5.93mA -15.43mA -900.00mV -13.79mA -8.05mA -27.84mA -800.00mV -25.05mA -12.19mA -67.49mA -700.00mV -53.38mA -21.96mA -95.94mA -600.00mV -63.55mA -39.96mA -85.32mA -500.00mV -54.69mA -41.71mA -72.32mA -400.00mV -44.46mA -34.36mA -58.84mA -300.00mV -33.87mA -26.17mA -44.88mA -200.00mV -22.93mA -17.70mA -30.44mA -100.00mV -11.65mA -8.98mA -15.49mA 0.00V 6.19pA 20.31pA 7.59pA 100.00mV 11.52mA 8.87mA 15.33mA 200.00mV 22.42mA 17.27mA 29.82mA 300.00mV 32.73mA 25.21mA 43.50mA 400.00mV 42.46mA 32.72mA 56.38mA 500.00mV 51.61mA 39.79mA 68.49mA 600.00mV 60.18mA 46.44mA 79.87mA 700.00mV 68.26mA 52.67mA 90.49mA 800.00mV 75.82mA 58.50mA 100.38mA 900.00mV 82.88mA 63.94mA 109.65mA 1.00V 89.44mA 68.99mA 118.26mA 1.10V 95.52mA 73.67mA 126.24mA 1.20V 101.13mA 77.98mA 133.60mA 1.30V 106.29mA 81.94mA 140.37mA 1.40V 111.01mA 85.55mA 146.56mA 1.50V 115.31mA 88.81mA 152.19mA 1.60V 119.23mA 91.73mA 157.28mA 1.70V 122.70mA 94.33mA 161.91mA 1.80V 125.76mA 96.63mA 165.97mA 1.90V 128.46mA 98.62mA 169.52mA 2.00V 130.78mA 100.31mA 172.63mA 2.10V 132.74mA 101.71mA 175.27mA 2.20V 134.36mA 102.83mA 177.48mA 2.30V 135.63mA 103.66mA 179.26mA 2.40V 136.55mA 104.21mA 180.55mA 2.50V 137.02mA 104.44mA 181.00mA 2.60V 137.11mA 104.50mA 181.13mA 2.70V 137.20mA 104.57mA 181.26mA 2.80V 137.29mA 104.63mA 181.40mA 2.90V 137.38mA 104.69mA 181.53mA 3.00V 137.47mA 104.76mA 181.66mA 3.10V 137.56mA 104.82mA 181.80mA 3.20V 137.65mA 104.89mA 181.93mA 3.30V 137.74mA 104.95mA 182.06mA 3.40V 137.83mA 105.02mA 182.19mA 3.50V 137.92mA 105.08mA 182.33mA 3.60V 138.01mA 105.15mA 182.46mA 3.70V 138.11mA 105.21mA 182.59mA 3.80V 138.20mA 105.28mA 182.72mA 3.90V 138.29mA 105.34mA 182.86mA 4.00V 138.38mA 105.41mA 182.99mA 4.10V 138.47mA 105.47mA 183.12mA 4.20V 138.56mA 105.54mA 183.26mA 4.30V 138.65mA 105.60mA 183.39mA 4.40V 138.74mA 105.67mA 183.52mA 4.50V 138.83mA 105.73mA 183.65mA 4.60V 138.92mA 105.80mA 183.79mA 4.70V 139.01mA 105.86mA 183.92mA 4.80V 139.10mA 105.93mA 184.05mA 4.90V 139.19mA 105.99mA 184.18mA 5.00V 139.28mA 106.06mA 184.31mA 10.00V 143.82mA 109.35mA 190.91mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -8.95A -8.62A -9.27A -4.80V -8.52A -8.21A -8.82A -4.60V -8.09A -7.80A -8.37A -4.40V -7.67A -7.40A -7.93A -4.20V -7.24A -6.99A -7.48A -4.00V -6.81A -6.59A -7.03A -3.80V -6.39A -6.19A -6.58A -3.60V -5.96A -5.78A -6.13A -3.40V -5.54A -5.38A -5.69A -3.20V -5.11A -4.97A -5.24A -3.00V -4.69A -4.57A -4.79A -2.80V -4.26A -4.17A -4.34A -2.60V -3.84A -3.77A -3.90A -2.40V -3.41A -3.37A -3.45A -2.20V -2.99A -2.97A -3.01A -2.00V -2.57A -2.57A -2.57A -1.95V -2.47A -2.47A -2.46A -1.90V -2.36A -2.37A -2.35A -1.85V -2.26A -2.27A -2.24A -1.80V -2.15A -2.17A -2.12A -1.75V -2.05A -2.07A -2.01A -1.70V -1.94A -1.97A -1.90A -1.65V -1.84A -1.87A -1.80A -1.60V -1.73A -1.77A -1.69A -1.55V -1.63A -1.67A -1.58A -1.50V -1.53A -1.58A -1.47A -1.45V -1.42A -1.48A -1.36A -1.40V -1.32A -1.38A -1.25A -1.35V -1.22A -1.28A -1.14A -1.30V -1.12A -1.19A -1.03A -1.25V -1.01A -1.09A -927.24mA -1.20V -913.06mA -994.01mA -820.49mA -1.15V -812.95mA -898.85mA -715.45mA -1.10V -712.84mA -803.68mA -610.41mA -1.05V -614.93mA -710.22mA -508.33mA -1.00V -517.02mA -616.77mA -406.24mA -950.00mV -423.02mA -526.06mA -310.33mA -900.00mV -329.03mA -435.35mA -214.41mA -850.00mV -243.48mA -349.64mA -136.23mA -800.00mV -157.94mA -263.93mA -58.06mA -750.00mV -96.13mA -189.21mA -30.21mA -700.00mV -34.32mA -114.50mA -2.37mA -650.00mV -17.98mA -67.83mA -1.20mA -600.00mV -1.64mA -21.16mA -35.86uA -550.00mV -841.55uA -11.22mA -18.20uA -500.00mV -46.79uA -1.28mA -550.53nA -450.00mV -24.07uA -669.38uA -280.43nA -400.00mV -1.34uA -58.64uA -10.32nA -350.00mV -691.24nA -30.66uA -5.24nA -300.00mV -41.44nA -2.68uA -171.96pA -250.00mV -21.40nA -1.40uA -45.52pA -200.00mV -1.37nA -126.91nA 80.91pA -150.00mV -671.24pA -66.94nA 97.41pA -100.00mV 27.63pA -6.96nA 113.90pA -50.00mV 68.77pA -3.98nA 99.05pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 388.20uA 311.29uA 484.34uA -4.50V 438.92uA 350.92uA 549.23uA -4.00V 505.10uA 402.32uA 634.44uA -3.50V 595.13uA 471.67uA 751.28uA -3.00V 724.73uA 570.44uA 921.41uA -2.50V 927.46uA 722.40uA 1.19mA -2.00V 1.29mA 986.53uA 1.69mA -1.50V 2.12mA 1.56mA 2.90mA -1.40V 2.43mA 1.76mA 3.38mA -1.30V 2.85mA 2.03mA 4.06mA -1.20V 3.44mA 2.39mA 5.07mA -1.10V 4.32mA 2.90mA 6.71mA -1.00V 5.79mA 3.67mA 9.81mA -900.00mV 8.62mA 4.98mA 17.30mA -800.00mV 15.51mA 7.53mA 41.83mA -700.00mV 33.37mA 13.55mA 62.81mA -600.00mV 39.93mA 24.64mA 55.18mA -500.00mV 33.88mA 25.31mA 46.05mA -400.00mV 27.14mA 20.53mA 36.86mA -300.00mV 20.36mA 15.41mA 27.65mA -200.00mV 13.57mA 10.27mA 18.43mA -100.00mV 6.78mA 5.13mA 9.21mA 0.00V -23.90pA -26.73pA -23.46pA 100.00mV -6.67mA -5.04mA -9.08mA 200.00mV -13.16mA -9.93mA -17.92mA 300.00mV -19.45mA -14.67mA -26.53mA 400.00mV -25.56mA -19.25mA -34.90mA 500.00mV -31.48mA -23.68mA -43.03mA 600.00mV -37.20mA -27.96mA -50.93mA 700.00mV -42.74mA -32.09mA -58.57mA 800.00mV -48.09mA -36.06mA -65.96mA 900.00mV -53.26mA -39.88mA -73.13mA 1.00V -58.23mA -43.55mA -80.06mA 1.10V -63.01mA -47.06mA -86.75mA 1.20V -67.60mA -50.42mA -93.19mA 1.30V -72.00mA -53.62mA -99.38mA 1.40V -76.21mA -56.67mA -105.34mA 1.50V -80.22mA -59.57mA -111.04mA 1.60V -84.06mA -62.30mA -116.50mA 1.70V -87.69mA -64.87mA -121.74mA 1.80V -91.11mA -67.30mA -126.70mA 1.90V -94.35mA -69.57mA -131.40mA 2.00V -97.40mA -71.69mA -135.86mA 2.10V -100.24mA -73.65mA -140.08mA 2.20V -102.90mA -75.46mA -144.04mA 2.30V -105.35mA -77.10mA -147.75mA 2.40V -107.62mA -78.59mA -151.21mA 2.50V -109.68mA -79.93mA -154.41mA 2.60V -111.55mA -81.11mA -157.36mA 2.70V -113.22mA -82.13mA -160.06mA 2.80V -114.69mA -82.99mA -162.50mA 2.90V -115.97mA -83.69mA -164.69mA 3.00V -117.05mA -84.24mA -166.62mA 3.10V -117.93mA -84.63mA -168.29mA 3.20V -118.61mA -84.88mA -169.70mA 3.30V -119.09mA -86.12mA -170.86mA 3.40V -119.38mA -86.89mA -171.76mA 3.50V -121.19mA -87.48mA -172.42mA 3.60V -122.22mA -88.00mA -172.80mA 3.70V -123.04mA -88.46mA -175.33mA 3.80V -123.74mA -88.89mA -176.84mA 3.90V -124.38mA -89.30mA -178.01mA 4.00V -124.97mA -89.68mA -179.02mA 4.10V -125.53mA -90.06mA -179.93mA 4.20V -126.06mA -90.41mA -180.77mA 4.30V -126.57mA -90.76mA -181.57mA 4.40V -127.07mA -91.10mA -182.32mA 4.50V -127.54mA -91.43mA -183.05mA 4.60V -128.01mA -91.75mA -183.74mA 4.70V -128.46mA -92.07mA -184.42mA 4.80V -128.91mA -92.38mA -185.08mA 4.90V -129.34mA -92.69mA -185.72mA 5.00V -129.77mA -92.99mA -186.35mA 10.00V -147.44mA -105.83mA -211.47mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 11.08A 10.67A 11.48A -4.80V 10.55A 10.16A 10.93A -4.60V 10.02A 9.66A 10.37A -4.40V 9.49A 9.16A 9.81A -4.20V 8.96A 8.66A 9.26A -4.00V 8.43A 8.15A 8.70A -3.80V 7.91A 7.65A 8.15A -3.60V 7.38A 7.15A 7.59A -3.40V 6.85A 6.65A 7.04A -3.20V 6.32A 6.15A 6.48A -3.00V 5.79A 5.65A 5.93A -2.80V 5.27A 5.15A 5.37A -2.60V 4.74A 4.65A 4.82A -2.40V 4.22A 4.16A 4.27A -2.20V 3.70A 3.66A 3.72A -2.00V 3.17A 3.16A 3.17A -1.95V 3.04A 3.04A 3.03A -1.90V 2.91A 2.92A 2.89A -1.85V 2.78A 2.80A 2.76A -1.80V 2.65A 2.67A 2.62A -1.75V 2.52A 2.55A 2.48A -1.70V 2.39A 2.43A 2.35A -1.65V 2.26A 2.30A 2.21A -1.60V 2.14A 2.18A 2.08A -1.55V 2.01A 2.06A 1.94A -1.50V 1.88A 1.94A 1.81A -1.45V 1.75A 1.82A 1.67A -1.40V 1.62A 1.70A 1.54A -1.35V 1.50A 1.58A 1.40A -1.30V 1.37A 1.45A 1.27A -1.25V 1.24A 1.34A 1.14A -1.20V 1.12A 1.22A 1.00A -1.15V 993.19mA 1.10A 873.98mA -1.10V 869.18mA 980.36mA 743.87mA -1.05V 747.99mA 864.66mA 617.54mA -1.00V 626.79mA 748.96mA 491.22mA -950.00mV 510.65mA 636.79mA 372.88mA -900.00mV 394.50mA 524.62mA 254.54mA -850.00mV 289.42mA 418.96mA 159.65mA -800.00mV 184.34mA 313.29mA 64.76mA -750.00mV 110.65mA 222.14mA 33.57mA -700.00mV 36.97mA 130.99mA 2.38mA -650.00mV 19.31mA 76.60mA 1.21mA -600.00mV 1.64mA 22.21mA 35.30uA -550.00mV 843.25uA 11.75mA 17.90uA -500.00mV 46.20uA 1.28mA 504.59nA -450.00mV 23.74uA 669.43uA 255.86nA -400.00mV 1.27uA 58.00uA 7.12nA -350.00mV 654.72nA 30.29uA 3.55nA -300.00mV 35.04nA 2.59uA -28.28pA -250.00mV 17.95nA 1.35uA -56.18pA -200.00mV 852.22pA 116.48nA -84.09pA -150.00mV 396.98pA 61.30nA -103.81pA -100.00mV -58.25pA 6.13nA -123.54pA -50.00mV -81.77pA 3.67nA -100.39pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 2.20V/321.13ps 1.92V/475.06ps 2.49V/206.19ps dV/dt_f 2.46V/509.92ps 2.22V/878.01ps 2.70V/293.50ps | |********************************************************************* | [Model] PSCI00000A1K3KZZNMC Model_type Input | Vinl = 1.50V Vinh = 3.50V | | typ min max | C_comp 2.30pF 1.24pF 4.28pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -6.39A -6.15A -6.62A -4.80V -6.08A -5.86A -6.30A -4.60V -5.78A -5.57A -5.98A -4.40V -5.47A -5.28A -5.66A -4.20V -5.16A -4.99A -5.34A -4.00V -4.86A -4.70A -5.01A -3.80V -4.55A -4.41A -4.69A -3.60V -4.25A -4.12A -4.37A -3.40V -3.95A -3.83A -4.05A -3.20V -3.64A -3.54A -3.73A -3.00V -3.34A -3.25A -3.41A -2.80V -3.03A -2.97A -3.09A -2.60V -2.73A -2.68A -2.78A -2.40V -2.43A -2.39A -2.46A -2.20V -2.13A -2.10A -2.14A -2.00V -1.82A -1.82A -1.82A -1.95V -1.75A -1.75A -1.74A -1.90V -1.67A -1.68A -1.66A -1.85V -1.60A -1.61A -1.59A -1.80V -1.52A -1.54A -1.51A -1.75V -1.45A -1.46A -1.43A -1.70V -1.38A -1.39A -1.35A -1.65V -1.30A -1.32A -1.27A -1.60V -1.23A -1.25A -1.19A -1.55V -1.15A -1.18A -1.11A -1.50V -1.08A -1.11A -1.04A -1.45V -1.00A -1.04A -958.66mA -1.40V -930.38mA -971.89mA -880.98mA -1.35V -857.12mA -902.43mA -803.86mA -1.30V -783.87mA -832.98mA -726.75mA -1.25V -711.33mA -764.15mA -650.47mA -1.20V -638.80mA -695.32mA -574.19mA -1.15V -567.31mA -627.36mA -499.18mA -1.10V -495.81mA -559.39mA -424.16mA -1.05V -425.98mA -492.72mA -351.39mA -1.00V -356.14mA -426.04mA -278.61mA -950.00mV -289.30mA -361.45mA -210.58mA -900.00mV -222.46mA -296.86mA -142.54mA -850.00mV -162.24mA -236.15mA -88.64mA -800.00mV -102.02mA -175.43mA -34.73mA -750.00mV -60.69mA -123.46mA -17.96mA -700.00mV -19.37mA -71.48mA -1.20mA -650.00mV -10.10mA -41.47mA -609.84uA -600.00mV -825.82uA -11.45mA -18.06uA -550.00mV -424.68uA -6.05mA -9.17uA -500.00mV -23.54uA -644.61uA -285.58nA -450.00mV -12.11uA -337.04uA -145.73nA -400.00mV -685.44nA -29.48uA -5.87nA -350.00mV -353.79nA -15.42uA -3.00nA -300.00mV -22.14nA -1.36uA -122.32pA -250.00mV -11.47nA -712.97nA -42.15pA -200.00mV -798.90pA -65.82nA 38.02pA -150.00mV -394.88pA -34.77nA 50.44pA -100.00mV 9.13pA -3.71nA 62.87pA -50.00mV 33.09pA -2.10nA 52.25pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 5.54A 5.33A 5.74A -4.80V 5.28A 5.08A 5.46A -4.60V 5.01A 4.83A 5.19A -4.40V 4.75A 4.58A 4.91A -4.20V 4.48A 4.33A 4.63A -4.00V 4.22A 4.08A 4.35A -3.80V 3.95A 3.83A 4.07A -3.60V 3.69A 3.58A 3.80A -3.40V 3.42A 3.33A 3.52A -3.20V 3.16A 3.08A 3.24A -3.00V 2.90A 2.83A 2.96A -2.80V 2.63A 2.58A 2.69A -2.60V 2.37A 2.33A 2.41A -2.40V 2.11A 2.08A 2.13A -2.20V 1.85A 1.83A 1.86A -2.00V 1.59A 1.58A 1.58A -1.95V 1.52A 1.52A 1.52A -1.90V 1.46A 1.46A 1.45A -1.85V 1.39A 1.40A 1.38A -1.80V 1.33A 1.34A 1.31A -1.75V 1.26A 1.27A 1.24A -1.70V 1.20A 1.21A 1.17A -1.65V 1.13A 1.15A 1.11A -1.60V 1.07A 1.09A 1.04A -1.55V 1.00A 1.03A 970.41mA -1.50V 939.30mA 969.08mA 902.71mA -1.45V 875.35mA 908.47mA 835.37mA -1.40V 811.40mA 847.86mA 768.03mA -1.35V 747.89mA 787.64mA 701.18mA -1.30V 684.39mA 727.43mA 634.33mA -1.25V 621.49mA 667.75mA 568.19mA -1.20V 558.60mA 608.07mA 502.05mA -1.15V 496.60mA 549.12mA 436.99mA -1.10V 434.59mA 490.18mA 371.93mA -1.05V 373.99mA 432.33mA 308.77mA -1.00V 313.40mA 374.48mA 245.61mA -950.00mV 255.32mA 318.40mA 186.44mA -900.00mV 197.25mA 262.31mA 127.27mA -850.00mV 144.71mA 209.48mA 79.82mA -800.00mV 92.17mA 156.64mA 32.38mA -750.00mV 55.33mA 111.07mA 16.79mA -700.00mV 18.49mA 65.49mA 1.19mA -650.00mV 9.65mA 38.30mA 604.77uA -600.00mV 820.15uA 11.11mA 17.65uA -550.00mV 421.62uA 5.87mA 8.95uA -500.00mV 23.10uA 640.32uA 252.29nA -450.00mV 11.87uA 334.66uA 127.93nA -400.00mV 637.19nA 29.00uA 3.56nA -350.00mV 327.36nA 15.15uA 1.77nA -300.00mV 17.52nA 1.29uA -16.34pA -250.00mV 8.97nA 676.57nA -29.85pA -200.00mV 425.20pA 58.29nA -43.37pA -150.00mV 198.26pA 30.70nA -53.63pA -100.00mV -28.69pA 3.11nA -63.89pA -50.00mV -41.12pA 1.88nA -51.88pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Model] PSCB08080A1K3KZZKMB Model_type I/O | Vinl = 1.50V Vinh = 3.50V | | typ min max | C_comp 1.80pF 0.97pF 3.35pF [Voltage range] 5.000V 4.750V 5.250V | |********************************************************************* | [Pulldown] | | Voltage I(typ) I(min) I(max) | -5.00V -301.34uA -247.42uA -364.12uA -4.50V -340.96uA -279.12uA -413.24uA -4.00V -392.71uA -320.28uA -477.79uA -3.50V -463.18uA -375.87uA -566.43uA -3.00V -564.76uA -455.12uA -695.74uA -2.50V -723.96uA -577.24uA -902.04uA -2.00V -1.01mA -789.86uA -1.28mA -1.50V -1.66mA -1.25mA -2.22mA -1.40V -1.91mA -1.42mA -2.59mA -1.30V -2.24mA -1.63mA -3.12mA -1.20V -2.71mA -1.92mA -3.91mA -1.10V -3.42mA -2.34mA -5.22mA -1.00V -4.60mA -2.96mA -7.71mA -900.00mV -6.90mA -4.02mA -13.92mA -800.00mV -12.53mA -6.09mA -33.75mA -700.00mV -26.69mA -10.98mA -47.97mA -600.00mV -31.77mA -19.98mA -42.66mA -500.00mV -27.35mA -20.86mA -36.16mA -400.00mV -22.23mA -17.18mA -29.42mA -300.00mV -16.93mA -13.08mA -22.44mA -200.00mV -11.47mA -8.85mA -15.22mA -100.00mV -5.82mA -4.49mA -7.74mA 0.00V 3.09pA 10.15pA 3.80pA 100.00mV 5.76mA 4.43mA 7.67mA 200.00mV 11.21mA 8.63mA 14.91mA 300.00mV 16.37mA 12.61mA 21.75mA 400.00mV 21.23mA 16.36mA 28.19mA 500.00mV 25.81mA 19.89mA 34.25mA 600.00mV 30.12mA 23.22mA 39.93mA 700.00mV 34.16mA 26.34mA 45.26mA 800.00mV 37.94mA 29.25mA 50.23mA 900.00mV 41.47mA 31.97mA 54.86mA 1.00V 44.75mA 34.50mA 59.17mA 1.10V 47.79mA 36.84mA 63.16mA 1.20V 50.59mA 38.99mA 66.84mA 1.30V 53.17mA 40.97mA 70.22mA 1.40V 55.53mA 42.77mA 73.31mA 1.50V 57.68mA 44.41mA 76.13mA 1.60V 59.61mA 45.88mA 78.67mA 1.70V 61.35mA 47.18mA 80.96mA 1.80V 62.89mA 48.33mA 82.99mA 1.90V 64.24mA 49.33mA 84.77mA 2.00V 65.40mA 50.17mA 86.33mA 2.10V 66.38mA 50.87mA 87.65mA 2.20V 67.18mA 51.43mA 88.75mA 2.30V 67.82mA 51.85mA 89.64mA 2.40V 68.29mA 52.11mA 90.32mA 2.50V 68.51mA 52.22mA 90.50mA 2.60V 68.56mA 52.25mA 90.57mA 2.70V 68.60mA 52.28mA 90.63mA 2.80V 68.65mA 52.31mA 90.70mA 2.90V 68.69mA 52.35mA 90.76mA 3.00V 68.74mA 52.38mA 90.83mA 3.10V 68.78mA 52.41mA 90.90mA 3.20V 68.83mA 52.44mA 90.96mA 3.30V 68.87mA 52.48mA 91.03mA 3.40V 68.92mA 52.51mA 91.10mA 3.50V 68.96mA 52.54mA 91.16mA 3.60V 69.01mA 52.57mA 91.23mA 3.70V 69.05mA 52.61mA 91.30mA 3.80V 69.10mA 52.64mA 91.36mA 3.90V 69.14mA 52.67mA 91.43mA 4.00V 69.19mA 52.70mA 91.49mA 4.10V 69.23mA 52.74mA 91.56mA 4.20V 69.28mA 52.77mA 91.63mA 4.30V 69.32mA 52.80mA 91.69mA 4.40V 69.37mA 52.83mA 91.76mA 4.50V 69.41mA 52.87mA 91.83mA 4.60V 69.46mA 52.90mA 91.89mA 4.70V 69.50mA 52.93mA 91.96mA 4.80V 69.55mA 52.96mA 92.03mA 4.90V 69.60mA 53.00mA 92.09mA 5.00V 69.64mA 53.03mA 92.16mA 10.00V 71.91mA 54.65mA 95.45mA | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V -4.47A -4.31A -4.64A -4.80V -4.26A -4.11A -4.41A -4.60V -4.05A -3.90A -4.19A -4.40V -3.83A -3.70A -3.96A -4.20V -3.62A -3.50A -3.74A -4.00V -3.41A -3.30A -3.51A -3.80V -3.19A -3.09A -3.29A -3.60V -2.98A -2.89A -3.07A -3.40V -2.77A -2.69A -2.84A -3.20V -2.56A -2.49A -2.62A -3.00V -2.34A -2.29A -2.40A -2.80V -2.13A -2.08A -2.17A -2.60V -1.92A -1.88A -1.95A -2.40V -1.71A -1.68A -1.73A -2.20V -1.50A -1.48A -1.50A -2.00V -1.29A -1.28A -1.28A -1.95V -1.23A -1.23A -1.23A -1.90V -1.18A -1.18A -1.17A -1.85V -1.13A -1.13A -1.12A -1.80V -1.08A -1.08A -1.06A -1.75V -1.02A -1.03A -1.01A -1.70V -971.55mA -985.28mA -952.38mA -1.65V -919.48mA -935.94mA -897.55mA -1.60V -867.42mA -886.60mA -842.73mA -1.55V -815.56mA -837.45mA -788.12mA -1.50V -763.70mA -788.30mA -733.51mA -1.45V -712.11mA -739.40mA -679.19mA -1.40V -660.52mA -690.50mA -624.86mA -1.35V -609.28mA -641.92mA -570.93mA -1.30V -558.04mA -593.33mA -516.99mA -1.25V -507.29mA -545.17mA -463.62mA -1.20V -456.53mA -497.01mA -410.25mA -1.15V -406.47mA -449.42mA -357.73mA -1.10V -356.42mA -401.84mA -305.20mA -1.05V -307.46mA -355.11mA -254.16mA -1.00V -258.51mA -308.38mA -203.12mA -950.00mV -211.51mA -263.03mA -155.16mA -900.00mV -164.51mA -217.68mA -107.20mA -850.00mV -121.74mA -174.82mA -68.12mA -800.00mV -78.97mA -131.96mA -29.03mA -750.00mV -48.06mA -94.61mA -15.11mA -700.00mV -17.16mA -57.25mA -1.18mA -650.00mV -8.99mA -33.91mA -601.34uA -600.00mV -818.15uA -10.58mA -17.93uA -550.00mV -420.77uA -5.61mA -9.10uA -500.00mV -23.40uA -640.06uA -275.27nA -450.00mV -12.03uA -334.69uA -140.21nA -400.00mV -670.52nA -29.32uA -5.16nA -350.00mV -345.62nA -15.33uA -2.62nA -300.00mV -20.72nA -1.34uA -84.05pA -250.00mV -10.70nA -701.69nA -20.83pA -200.00mV -683.21pA -63.46nA 42.40pA -150.00mV -333.77pA -33.47nA 50.65pA -100.00mV 15.67pA -3.48nA 58.90pA -50.00mV 36.24pA -1.99nA 51.47pA 0.00V 0.00pA 0.00pA 0.00pA 5.00V 0.00pA 0.00nA 0.00pA | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.00V 194.09uA 155.64uA 242.16uA -4.50V 219.46uA 175.46uA 274.62uA -4.00V 252.56uA 201.16uA 317.22uA -3.50V 297.56uA 235.84uA 375.65uA -3.00V 362.36uA 285.22uA 460.71uA -2.50V 463.73uA 361.20uA 596.06uA -2.00V 644.73uA 493.26uA 844.93uA -1.50V 1.06mA 779.22uA 1.45mA -1.40V 1.21mA 881.38uA 1.69mA -1.30V 1.42mA 1.01mA 2.03mA -1.20V 1.72mA 1.19mA 2.53mA -1.10V 2.16mA 1.45mA 3.35mA -1.00V 2.90mA 1.84mA 4.90mA -900.00mV 4.31mA 2.49mA 8.65mA -800.00mV 7.76mA 3.76mA 20.91mA -700.00mV 16.68mA 6.77mA 31.41mA -600.00mV 19.97mA 12.32mA 27.59mA -500.00mV 16.94mA 12.65mA 23.02mA -400.00mV 13.57mA 10.27mA 18.43mA -300.00mV 10.18mA 7.71mA 13.83mA -200.00mV 6.78mA 5.13mA 9.22mA -100.00mV 3.39mA 2.56mA 4.60mA 0.00V -11.95pA -13.37pA -11.73pA 100.00mV -3.34mA -2.52mA -4.54mA 200.00mV -6.58mA -4.96mA -8.96mA 300.00mV -9.73mA -7.33mA -13.27mA 400.00mV -12.78mA -9.63mA -17.45mA 500.00mV -15.74mA -11.84mA -21.52mA 600.00mV -18.61mA -13.98mA -25.46mA 700.00mV -21.38mA -16.04mA -29.29mA 800.00mV -24.06mA -18.03mA -33.00mA 900.00mV -26.64mA -19.94mA -36.58mA 1.00V -29.13mA -21.77mA -40.05mA 1.10V -31.52mA -23.53mA -43.39mA 1.20V -33.81mA -25.21mA -46.61mA 1.30V -36.01mA -26.81mA -49.71mA 1.40V -38.11mA -28.34mA -52.68mA 1.50V -40.12mA -29.78mA -55.54mA 1.60V -42.03mA -31.15mA -58.26mA 1.70V -43.84mA -32.45mA -60.87mA 1.80V -45.56mA -33.66mA -63.35mA 1.90V -47.18mA -34.80mA -65.71mA 2.00V -48.70mA -35.85mA -67.94mA 2.10V -50.13mA -36.84mA -70.05mA 2.20V -51.45mA -37.74mA -72.03mA 2.30V -52.68mA -38.56mA -73.88mA 2.40V -53.81mA -39.30mA -75.61mA 2.50V -54.84mA -39.97mA -77.21mA 2.60V -55.78mA -40.56mA -78.69mA 2.70V -56.61mA -41.07mA -80.04mA 2.80V -57.34mA -41.49mA -81.25mA 2.90V -57.98mA -41.85mA -82.34mA 3.00V -58.52mA -42.12mA -83.30mA 3.10V -58.96mA -42.31mA -84.14mA 3.20V -59.30mA -42.57mA -84.84mA 3.30V -59.54mA -43.01mA -85.42mA 3.40V -59.81mA -43.44mA -85.87mA 3.50V -60.58mA -43.74mA -86.19mA 3.60V -61.11mA -44.00mA -86.68mA 3.70V -61.52mA -44.23mA -87.59mA 3.80V -61.87mA -44.44mA -88.41mA 3.90V -62.19mA -44.65mA -89.00mA 4.00V -62.49mA -44.84mA -89.51mA 4.10V -62.77mA -45.03mA -89.96mA 4.20V -63.03mA -45.21mA -90.39mA 4.30V -63.29mA -45.38mA -90.78mA 4.40V -63.53mA -45.55mA -91.16mA 4.50V -63.77mA -45.71mA -91.52mA 4.60V -64.00mA -45.88mA -91.87mA 4.70V -64.23mA -46.03mA -92.21mA 4.80V -64.45mA -46.19mA -92.54mA 4.90V -64.67mA -46.34mA -92.86mA 5.00V -64.88mA -46.49mA -93.17mA 10.00V -73.72mA -52.89mA -105.74mA | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.00V 5.54A 5.33A 5.74A -4.80V 5.28A 5.08A 5.46A -4.60V 5.01A 4.83A 5.19A -4.40V 4.75A 4.58A 4.91A -4.20V 4.48A 4.33A 4.63A -4.00V 4.22A 4.08A 4.35A -3.80V 3.95A 3.83A 4.07A -3.60V 3.69A 3.58A 3.80A -3.40V 3.42A 3.33A 3.52A -3.20V 3.16A 3.08A 3.24A -3.00V 2.90A 2.83A 2.96A -2.80V 2.63A 2.58A 2.69A -2.60V 2.37A 2.33A 2.41A -2.40V 2.11A 2.08A 2.13A -2.20V 1.85A 1.83A 1.86A -2.00V 1.59A 1.58A 1.58A -1.95V 1.52A 1.52A 1.52A -1.90V 1.46A 1.46A 1.45A -1.85V 1.39A 1.40A 1.38A -1.80V 1.33A 1.34A 1.31A -1.75V 1.26A 1.27A 1.24A -1.70V 1.20A 1.21A 1.17A -1.65V 1.13A 1.15A 1.11A -1.60V 1.07A 1.09A 1.04A -1.55V 1.00A 1.03A 970.41mA -1.50V 939.30mA 969.08mA 902.71mA -1.45V 875.35mA 908.47mA 835.37mA -1.40V 811.40mA 847.86mA 768.03mA -1.35V 747.89mA 787.64mA 701.18mA -1.30V 684.39mA 727.43mA 634.33mA -1.25V 621.49mA 667.75mA 568.19mA -1.20V 558.60mA 608.07mA 502.05mA -1.15V 496.60mA 549.12mA 436.99mA -1.10V 434.59mA 490.18mA 371.93mA -1.05V 373.99mA 432.33mA 308.77mA -1.00V 313.40mA 374.48mA 245.61mA -950.00mV 255.32mA 318.40mA 186.44mA -900.00mV 197.25mA 262.31mA 127.27mA -850.00mV 144.71mA 209.48mA 79.83mA -800.00mV 92.17mA 156.64mA 32.38mA -750.00mV 55.33mA 111.07mA 16.79mA -700.00mV 18.49mA 65.49mA 1.19mA -650.00mV 9.65mA 38.30mA 604.77uA -600.00mV 820.15uA 11.11mA 17.65uA -550.00mV 421.62uA 5.87mA 8.95uA -500.00mV 23.10uA 640.43uA 252.30nA -450.00mV 11.87uA 334.72uA 127.93nA -400.00mV 637.19nA 29.00uA 3.56nA -350.00mV 327.36nA 15.15uA 1.77nA -300.00mV 17.52nA 1.29uA -15.19pA -250.00mV 8.97nA 676.52nA -29.12pA -200.00mV 425.13pA 58.24nA -43.05pA -150.00mV 197.53pA 30.65nA -52.90pA -100.00mV -30.07pA 3.06nA -62.74pA -50.00mV -41.81pA 1.83nA -51.15pA 1.00mV 0.00pA 0.00pA 0.00pA 0.00V 0.00pA 0.00pA 0.00pA | |********************************************************************* | [Ramp] | | typ min max | dV/dt_r 1.59V/405.19ps 1.28V/561.34ps 1.95V/274.04ps dV/dt_f 1.89V/1.01ns 1.59V/1.27ns 2.21V/577.58ps | [END] From bob@icx.com Sat Apr 2 18:47:16 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA23785; Sat, 2 Apr 94 18:47:16 PST Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA10948 for ; Sat, 2 Apr 94 21:43:17 -0500 Date: Sat, 2 Apr 94 18:39:24 PST From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA22068; Sat, 2 Apr 94 18:39:24 PST Message-Id: <9404030239.AA22068@icx.com> To: ibis@vhdl.org Subject: MORE S2IBIS COMMENTS Steve, Thanks for your April 1 response. Here are some responses: (1) There are two types of information that you need to run S2IBIS and to produce completed models within the commented [Pin] mapping portion. The "model_type SPICE_NODE ramp_time input_pin [enable_pin] ..." line contains information for CONTROLING THE SIMULATION of a particular Spice run. Thus vih and vil are the PULSE parameter levels FOR SPICE, and NOT for the [Model]. Extending this for more PULSE parameter rise time and fall time control with "tr" and "tf" is good for generality. In my opinion it is probably worth it to add the complication at this time. However, this is low priority for me since I think your default of 0.1ns seems like a good choice. This actually opens the door for other extensions (RS for source impedance for inputs, some load control (50 ohms, Vcc volts, etc) even though IBIS has some "rigid" guidelines in this area - there may be real world practical considerations or convergence considerations which "force" a departure to still produce an acceptable mode. I would be comfortable defering this matter until later. (2) The second type of information which we are currently unable to enter automatically are some required and optional parameters under [Model]. In this category, would be the some CONTROL information which your are currently putting into the model: Polarity Enable based on the Spice model provided. This is technically correct provided you are using a model which correctly has this information with the correct polarities. This is often the case. For signal integrity analysis, the polarity details may not be important because the LOGIC details are not considered. The threshholds are tested at both limits regardless of the logic Input polarity, and the Output is usually pulsed both direction without being concerned which transition comes first. Consequently some Spice models may be suitable for analysis for several outputs without forcing the unnecessary overhead of putting in the Spice models. For example, the 74F240/241/244 have output polarity and enable polarity variations, with the 241 having both an Active-high and Active-low enable pin. In practice, you may want to use one Spice model for all of the components. My suggestion is NOT to insert Polarity and Enable based on the supplied configuration. Instead, I suggest you create an appropriate convention that allows this information to be entered under user control. This convention will also apply to the Optional and Required IBIS Version 1.1 parameters of Vinl, Vinh, and C_comp as well. For example, suppose we use "**" (and anyone may have better idea than this) as the ADDITIONAL TEXT PARAMETERS, then the format for a 74F240 input may be: *[Pin] signal_name model_name R_pin L_pin C_pin * 1 G_BAR EN_MODEL * Input 101 1 0. 3. **Vinh = 2.0 **Vinl = 0.8 **C_comp 5pF 3pF 7pF * 2 A0 0 IN_MODEL * Input 100 1 0. 3. **Vinh = 2.0 **Vinl = 0.8 **C_comp 5pF 3pF 7pF The ** lines would be printed with the Input [Model] Similarily, ..... * 18 YA0_BAR TRI_MODEL * 3-state 102 2.0e-8 2 1 **Polarity Inverting **C_comp 7pF 5pF 9pF * 19 ..... Here we choose not even to include Enable in the model. Futhermore, the Spice model used may have "forced" the "Non_Inverting" Polarity. (3) Regarding alpha-numeric pins, IBIS already restricts the pin "numbers" to "5 characters" or less, so you are alright for DOS compatiblity. The maximum PGA numbering I think is 4 characters, e.g. A1 ... Z24 (I and O are typically omitted) and then AA1 .. AAnn BB1 .. BBnn and so forth. (4) At some point, your output could adopt a format with comment lines such as the models provided by Intel. I would not object to a different format for differentiation if you want to make improvements. I think it is alright for a fixed format, but an option would be to allow the "comment" lines and text to be included in some manner along with the [Model] ADDITIONAL TEXT PARAMETER of comment (2) above. Happy Easter Bob Ross Interconnectix, Inc. From speters@ichips.intel.com Mon Apr 4 08:27:07 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11325; Mon, 4 Apr 94 08:27:07 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Mon, 4 Apr 94 08:24:56 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Mon, 4 Apr 94 08:24:35 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Mon, 4 Apr 94 08:24:48 PDT Message-Id: <9404041524.AA13622@xtg801.intel.com> To: ibis@vhdl.org Subject: Re: new IBIS model Date: Mon, 04 Apr 1994 08:24:47 -0700 From: Stephen Peters Hello fellow IBISans -- Apparently not everyone on the reflector received the ECL example so, per Kumar's request, I am forwarding it along. Stephen Peters Intel Corp. ----------------------------cut here ------------------------------------------- Folks: Here is a smple ecl model with correct signs (hopefully!!) Here is an ecl pullup and pulldown example [Pullup] Voltage I(typ) I(min) I(max) 0.0 0 0 0 0.7 -0.2m -0.2m -0.2m 0.73 -0.4m -0.4m -0.4m 0.75 -0.8m -0.8m -0.8m 0.76 -1.2m -1.2m -1.2m 0.77 -1.6m -1.6m -1.6m 0.8 -4.4m -4.4m -4.4m 0.82 -7.6m -7.6m -7.6m 0.85 -14.2m -14.2m -14.2m 0.9 -30.0m -30.0m -30.0m 1.0 -58.0m -58.0m -58.0m [Pulldown] Voltage I(typ) I(min) I(max) 0.0 0 0 0 1.6 -0.2m -0.2m -0.2m 1.62 -0.4m -0.4m -0.4m 1.64 -0.6m -0.6m -0.6m 1.65 -0.8m -0.8m -0.8m 1.66 -1.2m -1.2m -1.2m 1.67 -1.6m -1.6m -1.6m 1.68 -2.4m -2.4m -2.4m 1.69 -3.2m -3.2m -3.2m 1.70 -4.4m -4.4m -4.4m 1.72 -7.4m -7.4m -7.4m 1.75 -14.2m -14.2m -14.2m 1.8 -30.5m -30.5m -30.5m 1.9 -65.0m -65.0m -65.0m - Kumar From speters@ichips.intel.com Mon Apr 4 14:49:57 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15101; Mon, 4 Apr 94 14:49:57 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Mon, 4 Apr 94 14:47:48 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Mon, 4 Apr 94 14:47:15 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Mon, 4 Apr 94 14:47:27 PDT Message-Id: <9404042147.AA14961@xtg801.intel.com> To: ibis@vhdl.org Subject: Clarification of 'New IBIS models' Date: Mon, 04 Apr 1994 14:47:26 -0700 From: Stephen Peters Hello Fellow IBISans -- This is a clarification of my previous e-mail in which I posted a new chip set model with non-monotonic data. That model was for CAE vendors use and inspection only. We have decided NOT to post these latest chip set models to vhdl.org until the question of whether the non-monotonic data is correct has been resolved. Regards, Stephen Peters Intel Corp. From bob@icx.com Mon Apr 4 15:40:42 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15372; Mon, 4 Apr 94 15:40:42 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA14851 for ; Mon, 4 Apr 94 17:39:31 -0400 Date: Mon, 4 Apr 94 13:34:06 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA25738; Mon, 4 Apr 94 13:34:06 PDT Message-Id: <9404042034.AA25738@icx.com> To: ibis@vhdl.org Subject: BIRD8 related comment, PSC_A2.IBS To IBIS Committee: Here are some of my thoughts on the recently posted NON-MONOTONIC psc_a2.ibs file related to last Friday's discussions. (1) I am comfortable with the new Intel models as they are provided. While I could fall in the camp that would prefer to see monotonic data for product reasons, efficiency, and so forth, I support Maah Sango's position that the IBIS data should represent the actual data that is produced or measured using the accepted processes as long at that data represents real or simulated performance. I accept Arpad Muranyi's rational of why the artifacts occur, although I confess that some of the details may have gone over my head. It does give me insite in some of the unexpected behavior I have observed. Furthermore, as long as the data is consistent within the framework of the IBIS context model such as the one below, then it is good data. Some simulator companies may have variations to the IBIS context model for internal processing, so it is the simulator companies responsibility to make any appropriate changes to the IBIS data for consistency. In fact, I think MOST company's should produce as part of any direct IBIS interface or translator the appropriate FILTER routines for their products. Only a few products will be architected to accept ALL IBIS data DIRECTLY into tables or tablular functions. |<-----------------OUTPUT and I/O Models---------------------->| | |<-------------INPUT Model------------>| VOLTAGE RANGE o-------------------o | | |----o----| | | | | |--o--| |--o--| |--o--| POWER_CLAMP | | | | | | |-|RAMP |---| VI |--| | VI | PACKAGE Keyword | | | | | | | | Parameters | |-----| |-----| | |--o--| |<------------------->| | dV/dt_r PULLUP | | | | | PIN | |--o-----o----------/\/\/\--UUUUUU---o--o | | | | R_PKG L_PKG | | dV/dt_f PULLDOWN | | | | | |-----| |-----| | | |--o--| GND_CLAMP | | | | | | | | | | | |-|RAMP |---| VI |--| | | VI | | | | | | | | | | |--o--| |--o--| | |--o--| | | | | | | |----o----| --- | --- | --- | --- | C_COMP | | C_PKG | | | | | o-------------o-----o---------------------------o GND (2) Both the [Pullup] and [Pulldown] tables contain similar types of behavior for the I/O devices, so for the purpose of discussion, I will be considering only the [Pulldown] table. I(typ) ^ | ____________----------- | ____------ [Pulldown] | _-- | / | / | / | / | / | / |/ --------------------|--------------------------------------------> Vtable \ * /| \ */ | \/ | * * * * [GND_clamp] * * At about -0.7V and less, the negative side of the [Pulldown] table kicks back toward 0mA. The combination of the [GND_clamp], and [Pulldown] table still retain monotonic behavior. Although the magnitude of the [GND_clamp] may be less than the magnitude of the [Pulldown] current at -0.7V, its rate of change is such that [GND_clamp] becomes by far the dominant current contributor below -0.7V. (3) When the [Model] is operating in the "Output" mode transmitting the ramp, the VI characteristics below 0V are of no concern. Any strong, negative reflected voltage which appears at the PIN will then see the combination of both the [Pulldown] table and [GND_clamp] table curves (non-linear impedances) when the [Model] is in the LOW state. In my opinion, the dominating characteristics for signal integrity analysis are contained in the voltage regions around 0V from say -1V to +2V. I believe that the accuracy of any analysis remains the same if the [Pulldown] curve is FILTERED to the following curve: I(typ) ^ | ____________----------- | ____------ [Pulldown] | _-- | / | / | / | / | / | / |/ --------------------|--------------------------------------------> Vtable /| / | ___________/ | <--------|--------> (b) (a) Furthermore, the FILTERING algorithm should be of the form that it starts at 0V and (a) filters in the positive direction for monotonicity (there may be non-monotonic behavior there as well from some slight fold-back effects because of combinations of internal tolerances), and (b) in the negative direction to remove the "kickback" such as tabulated in the Intel component [Model]s. (4) FILTERING can serve another purpose, that of data reduction. With a good approximation processes, the amount of data in ibis files can be reduced signifantly. Interpolation is assumed to be available to process the data. A number of algorithms can be applied to select of fit points based on an error criteria or on spacing of voltage points, and chances are that the errors introduced in the signal integrity analysis will be negligible and far less compared to errors produced by other possible variations. In case (b) only one data value at -5V might be used and the data between -5V and -0.7V removed. For some systems, reduction of data saves memory and possibly improves performance. Data reduction prior to posting files would also be appropriate. (Of course, companies which are in the business of selling memory chips may not be too concerned about data reduction.) Again I feel that the supplied data is good and is representative of type of data one can expect. For most vendors, it is probably dangerous to expect to use IBIS_CHK compliant data as supplied without further FILTERING or processing to take into account the specific operation of the simulator itself. Thank you Arpad and the Intel team for pointing out the some unexpected data characteristics so that we can respond. Bob Ross, Interconnectix, Inc. From ccm!Arpad_Muranyi@intelhf.intel.com Tue Apr 5 08:41:42 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA27774; Tue, 5 Apr 94 08:41:42 PDT Received: from intelhf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #2) id m0poDDs-000MNjC; Tue, 5 Apr 94 08:39 PDT Received: from ccm by intelhf.intel.com with uucp (Smail3.1.28.1 #1) id m0poDO6-0000A3C; Tue, 5 Apr 94 08:50 PDT Received: by ccm.hf.intel.com (ccmgate) Tue, 5 Apr 94 08:50:02 PST Date: Tue, 5 Apr 94 08:50:02 PST From: Arpad Muranyi Message-Id: <940405085002_1@ccm.hf.intel.com> To: ibis@vhdl.org Subject: Non monotonic curves Bob, Thank you for the beautiful ASCII graphics, and the moral support... I agree with most of what you say, with one little exception. I feel that the VI characteristics below 0V are indeed important, for the very reason you also mention, strong reflections. Your recommendation for fixing the non monotonic curves below -0.7 volt is a good start, but if you consider that the diode curve is monotonic, and the sum of the diode with the transistor is also monotonic, than there is nothing to fix. After all, we do not have to use the transistor curve by itself. Arpad Intel, Folsom To IBIS Committee: Here are some of my thoughts on the recently posted NON-MONOTONIC psc_a2.ibs file related to last Friday's discussions. (1) I am comfortable with the new Intel models as they are provided. While I could fall in the camp that would prefer to see monotonic data for product reasons, efficiency, and so forth, I support Maah Sango's position that the IBIS data should represent the actual data that is produced or measured using the accepted processes as long at that data represents real or simulated performance. I accept Arpad Muranyi's rational of why the artifacts occur, although I confess that some of the details may have gone over my head. It does give me insite in some of the unexpected behavior I have observed. Furthermore, as long as the data is consistent within the framework of the IBIS context model such as the one below, then it is good data. Some simulator companies may have variations to the IBIS context model for internal processing, so it is the simulator companies responsibility to make any appropriate changes to the IBIS data for consistency. In fact, I think MOST company's should produce as part of any direct IBIS interface or translator the appropriate FILTER routines for their products. Only a few products will be architected to accept ALL IBIS data DIRECTLY into tables or tablular functions. |<-----------------OUTPUT and I/O Models---------------------->| | |<-------------INPUT Model------------>| VOLTAGE RANGE o-------------------o | | |----o----| | | | | |--o--| |--o--| |--o--| POWER_CLAMP | | | | | | |-|RAMP |---| VI |--| | VI | PACKAGE Keyword | | | | | | | | Parameters | |-----| |-----| | |--o--| |<------------------->| | dV/dt_r PULLUP | | | | | PIN | |--o-----o----------/\/\/\--UUUUUU---o--o | | | | R_PKG L_PKG | | dV/dt_f PULLDOWN | | | | | |-----| |-----| | | |--o--| GND_CLAMP | | | | | | | | | | | |-|RAMP |---| VI |--| | | VI | | | | | | | | | | |--o--| |--o--| | |--o--| | | | | | | |----o----| --- | --- | --- | --- | C_COMP | | C_PKG | | | | | o-------------o-----o---------------------------o GND (2) Both the [Pullup] and [Pulldown] tables contain similar types of behavior for the I/O devices, so for the purpose of discussion, I will be considering only the [Pulldown] table. I(typ) ^ | ____________----------- | ____------ [Pulldown] | _-- | / | / | / | / | / | / |/ --------------------|--------------------------------------------> Vtable \ * /| \ */ | \/ | * * * * [GND_clamp] * * At about -0.7V and less, the negative side of the [Pulldown] table kicks back toward 0mA. The combination of the [GND_clamp], and [Pulldown] table still retain monotonic behavior. Although the magnitude of the [GND_clamp] may be less than the magnitude of the [Pulldown] current at -0.7V, its rate of change is such that [GND_clamp] becomes by far the dominant current contributor below -0.7V. (3) When the [Model] is operating in the "Output" mode transmitting the ramp, the VI characteristics below 0V are of no concern. Any strong, negative reflected voltage which appears at the PIN will then see the combination of both the [Pulldown] table and [GND_clamp] table curves (non-linear impedances) when the [Model] is in the LOW state. In my opinion, the dominating characteristics for signal integrity analysis are contained in the voltage regions around 0V from say -1V to +2V. I believe that the accuracy of any analysis remains the same if the [Pulldown] curve is FILTERED to the following curve: I(typ) ^ | ____________----------- | ____------ [Pulldown] | _-- | / | / | / | / | / | / |/ --------------------|--------------------------------------------> Vtable /| / | ___________/ | <--------|--------> (b) (a) Furthermore, the FILTERING algorithm should be of the form that it starts at 0V and (a) filters in the positive direction for monotonicity (there may be non-monotonic behavior there as well from some slight fold-back effects because of combinations of internal tolerances), and (b) in the negative direction to remove the "kickback" such as tabulated in the Intel component [Model]s. (4) FILTERING can serve another purpose, that of data reduction. With a good approximation processes, the amount of data in ibis files can be reduced signifantly. Interpolation is assumed to be available to process the data. A number of algorithms can be applied to select of fit points based on an error criteria or on spacing of voltage points, and -chances are that the errors introduced in the signal integrity analysis will be negligible and far less compared to errors produced by other possible variations. In case (b) only one data value at -5V might be used and the data between -5V and -0.7V removed. For some systems, reduction of data saves memory and possibly improves performance. Data reduction prior to posting files would also be appropriate. (Of course, companies which are in the business of selling memory chips may not be too concerned about data reduction.) Again I feel that the supplied data is good and is representative of type of data one can expect. For most vendors, it is probably dangerous to expect to use IBIS_CHK compliant data as supplied without further FILTERING or processing to take into account the specific operation of the simulator itself. Thank you Arpad and the Intel team for pointing out the some unexpected data characteristics so that we can respond. Bob Ross, Interconnectix, Inc. From ccm!Arpad_Muranyi@intelhf.intel.com Tue Apr 5 11:03:43 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29475; Tue, 5 Apr 94 11:03:43 PDT Received: from intelhf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #2) id m0poFRL-000MOCC; Tue, 5 Apr 94 11:01 PDT Received: from ccm by intelhf.intel.com with uucp (Smail3.1.28.1 #1) id m0poFbb-0000KJC; Tue, 5 Apr 94 11:12 PDT Received: by ccm.hf.intel.com (ccmgate) Tue, 5 Apr 94 11:12:07 PST Date: Tue, 5 Apr 94 11:12:07 PST From: Arpad Muranyi Message-Id: <940405111207_4@ccm.hf.intel.com> To: ibis@vhdl.org Subject: Important IBIS question to all Text item: Text_1 Hi IBIS people, In discussing the issue of non-monotonic curves, I realized that there is an unspoken assumption present that needs clarification. I would like to ask everyone to reply if possible to the following question: How do you use the POWER/GND clamp and pullup/down curves in your simulations? a) summing method, or b) exclusive method Explanation: a) By the summing method I mean that the VI curve in the clamp section is added to the VI curve in the pullup/down section for the ON condition. For the OFF (3-stated) condition, only the clamp curves are used. b) By the exclusive method I mean that the clamp curves are strictly used for the 3-state condition, and the pullup/down curves are strictly used for the ON condition without adding in the currents from the clamp sections. I appreciate your responses, Arpad Muranyi Intel Folsom From katz@blazng.enet.dec.com Tue Apr 5 12:50:36 1994 Return-Path: Received: from inet-gw-2.pa.dec.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00577; Tue, 5 Apr 94 12:50:36 PDT Received: from us1rmc.bb.dec.com by inet-gw-2.pa.dec.com (5.65/21Mar94) id AA04083; Tue, 5 Apr 94 12:42:55 -0700 Received: from blazng.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA29135; Tue, 5 Apr 94 15:42:58 -0400 Message-Id: <9404051942.AA29135@us1rmc.bb.dec.com> Received: from blazng.enet; by us1rmc.enet; Tue, 5 Apr 94 15:43:02 EDT Date: Tue, 5 Apr 94 15:43:02 EDT From: Barry Katz To: ibis@vhdl.org Cc: katz@blazng.enet.dec.com Apparently-To: ibis@vhdl.org Subject: Re: Important IBIS question to all Hi Arpad, In one of our internal simulators we currently use the exclusive method for model representation. However, it doesn't matter to us how the IBIS data is represented as long as it is done in a consistent manner. It sounds to me like there are models of both flavors out there. I wonder if some simulation companies are effectively adding in the clamping curves twice. Barry Katz Digital, Hudson MA From jonp@qdt.com Tue Apr 5 16:13:21 1994 Return-Path: Received: from relay2.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02199; Tue, 5 Apr 94 16:13:21 PDT Received: from uucp3.uu.net by relay2.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwkjk02402; Tue, 5 Apr 94 19:11:08 -0400 Received: from qdt.UUCP by uucp3.uu.net with UUCP/RMAIL ; Tue, 5 Apr 1994 19:11:10 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA02055; Tue, 5 Apr 94 15:20:32 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA07584; Tue, 5 Apr 94 15:20:32 PDT Date: Tue, 5 Apr 94 15:20:31 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404052220.AA07584@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA04862; Tue, 5 Apr 94 15:20:33 PDT To: uunet!ccm.hf.intel.com!Arpad_Muranyi@uunet.UU.NET Cc: ibis@vhdl.org In-Reply-To: Arpad Muranyi's message of Tue, 5 Apr 94 11:12:07 PST <940405111207_4@ccm.hf.intel.com> Subject: Important IBIS question to all Quad Design uses the summing method, and though it could be that I was reading the spec through quad colored glasses, I had assumed that the IBIS spec used the summing method also. jonp From bob@icx.com Tue Apr 5 17:34:05 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03109; Tue, 5 Apr 94 17:34:05 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA08887 for ; Tue, 5 Apr 94 20:17:41 -0400 Date: Tue, 5 Apr 94 16:27:16 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA01426; Tue, 5 Apr 94 16:27:16 PDT Message-Id: <9404052327.AA01426@icx.com> To: ibis@vhdl.org Subject: Important IBIS question response Arpad We plan to use a method equivalent to the summing method (a) and we have been assuming that the IBIS files are partitioned consistent with (a). We even assumed that the Output types [Model]s would be partitioned into the clamping and pullup/down portions. In general, I accept your argument last Friday that (within the framework of the IBIS model), such a partitioning is not necessary for the Output Model_type. I would still prefer to see the data partitioned (even if there are some reasonable, arbitrary assumptions about how the data is partitioned) because there may be cases where this may really be necessary. Partitioning should be done in a consistent manner throughout in IBIS models. Then simulator specific issues can be dealt with from a common reference. One case where partitioning assumptions have to be carefully understood is the Open_Drain configuration with an internal pullup resistor (transistor). My approach would be to model the resistor using the POWER_clamp table since I would assume the pullup table does not exist. (Usually these currents are small enough to be ignored, so this is not a big problem in practice.) Another hypothetical case is ECL_Output with a clamp to VEE. Since both the pullup and pulldown tables are connected to VCC, the current path routing differs based on the partitioning assumption with the ECL device in the low state. In the (unlikely) event of a large, negative undershoot, the partitioned model would pull current from VCC and VEE whereas the non- partitioned model would pull all the current from VCC. Thank you for raising a fundamental consideration. Bob Ross, Interconnectix, Inc. From 71436.1314@CompuServe.COM Tue Apr 5 20:59:51 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from dub-img-1.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04988; Tue, 5 Apr 94 20:59:51 PDT Received: from localhost by dub-img-1.compuserve.com (8.6.4/5.930129sam) id XAA28447; Tue, 5 Apr 1994 23:57:41 -0400 Date: 05 Apr 94 23:52:30 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Modeling method and Intel non-monotonic model Message-Id: <940406035230_71436.1314_HHB59-1@CompuServe.COM> From: Kellee Crisafulli, HyperLynx Re: Which modeling method does HyperLynx use, and Does the Intel non-monotonic model work. How do you use the POWER/GND clamp and pullup/down curves in your simulations? a) summing method, or b) exclusive method 1) HyperLynx uses the summing method (per your definition). a) By the summing method I mean that the VI curve in the clamp section is added to the VI curve in the pullup/down section for the ON condition. For the OFF (3-stated) condition, only the clamp curves are used. b) By the exclusive method I mean that the clamp curves are strictly used for the 3-state condition, and the pullup/down curves are strictly used for the ON condition without adding in the currents from the clamp sections. 2) I have tested the Intel model using a falling edge driving a long transmission line resulting in a very large reflection below ground (> -1V). I examined numerous examples using the most current version of the LineSim Pro simulator version 3.2. I found that the model at appeared to work fine. I am still against allowing non-monotonic data in IBIS models, however our simulator was modified several months ago to allow non-monotonic data. In conclusion we see no problem with the Intel model that would prevent it from being released. On that other hand we also support requiring that all V/I tables be monotonic. Have a great week... Kellee From Will_Hobbs@ccm2.jf.intel.com Wed Apr 6 09:24:15 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA13770; Wed, 6 Apr 94 09:24:15 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 6 Apr 94 09:21:58 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 6 Apr 94 09:21:32 -0700 Received: from ccMail by jfsmt2.intel.com id AA765649308 Wed, 06 Apr 94 09:21:48 PST Date: Wed, 06 Apr 94 09:21:48 PST From: "Hobbs, Will" Message-Id: <9403067656.AA765649308@jfsmt2.intel.com> To: ibis@vhdl.org Cc: cpk@cadence.com Subject: DAC IBIS Meeting for V2.0 Ratification Fellow Migratory IBIS Co-conspirators, At the April 1 meeting of the IBIS Open Forum, we chose Thursday, June 9, as the date for our third face-to-face meeting, or Third IBIS Open Forum Summit, as it were. This is the day after closing ceremonies at the DAC conference in San Diego. The purpose of this meeting will be to make any final changes to the proposed IBIS Specification, Version 2.0, and achieve ratification. The proposed roll-up of all changes generated by the BIRD process will be published about two weeks prior to the Summit for everyone to review, hopefully enabling us to reach agreement during the meeting. Kumar of Cadence has offered to supply the Forum with a room at or near the DAC site for this meeting, and needs to know how many attendees there will be so he can arrange for a room of appropriate size. Therefore, I am asking for RSVPs for this meeting. Please reply to me, Will_Hobbs@ccm2.jf.intel.com I will forward the number on to Kumar. You can also copy Kumar on the reply: cpk@cadence.com Thanks, and I look forward to seeing you at DAC. Will Hobbs Intel From huq@rockie.nsc.com Wed Apr 6 09:36:19 1994 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA13870; Wed, 6 Apr 94 09:36:19 PDT Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA06912 for ibis@vhdl.org; Wed, 6 Apr 94 09:34:05 -0700 Received: from lightning.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA28400 for ibis@vhdl.org; Wed, 6 Apr 94 09:34:05 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA00679; Wed, 6 Apr 94 09:34:00 PDT Date: Wed, 6 Apr 94 09:34:00 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9404061634.AA00679@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS article in Computer Design Hi IBIS-Grurs: In the March '94 COMPUTER DESIGN magazine pg 38, IBIS was mentioned in a long one page article titled: "EDA and semiconductor vendors team up for high-speed modeling" Regards, Syed Huq National Semiconductor Corp. Santa Clara,CA From bob@icx.com Wed Apr 6 11:50:16 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15823; Wed, 6 Apr 94 11:50:16 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA12680 for ; Wed, 6 Apr 94 14:43:17 -0400 Date: Wed, 6 Apr 94 11:28:07 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA04108; Wed, 6 Apr 94 11:28:07 PDT Message-Id: <9404061828.AA04108@icx.com> To: ibis@vhdl.org Subject: IBIS in PCB Conference To IBIS Members: "Designing a Pentium Based Board Using High Speed PCB Design Kits" by Greg Seltzer, Mentor Graphics in the Proceedings of the Third Annual PCB Design Conference, March 29-31, 1994 mentions IBIS several times. Bob Ross, Interconnectix, Inc. From Ravender_Goyal@pdxml1.mentorg.com Wed Apr 6 12:40:20 1994 Return-Path: Received: from mgc.mentorg.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16109; Wed, 6 Apr 94 12:40:20 PDT Received: from rainbow.mentorg.com by mgc.mentorg.com with SMTP (16.6/15.5+MGC-TD 2.20) id AA02789; Wed, 6 Apr 94 12:38:10 -0700 Received: from pdxml1.mentorg.com by rainbow.mentorg.com with SMTP (15.11.1.6/15.5+MGC-TD 2.08) id AA24790; Wed, 6 Apr 94 12:38:09 -0700 Message-Id: <9404061938.AA24790@rainbow.mentorg.com> Date: 6 Apr 1994 12:30:33 -0800 From: "Ravender Goyal" Subject: Re: IBIS in PCB Conference To: "Bob Ross" Reply to: RE>IBIS in PCB Conference I would also like to bring to everyone's attention IBIS mentioned in March issue of IEEE Spectrum, article entitled "Managing Signal Integrity". IBIS is becoming of international 'Miss (or Mrs.) Bird' fame. IEEE Spectrum has a worldwide circulation of 300, 000. Ravender -------------------------------------- Date: 4/6/94 11:57 AM To: Ravender Goyal From: Bob Ross Received: by pdxml2.mentorg.com with SMTP;6 Apr 1994 11:57:15 U Received: from mgc.mentorg.com by rainbow.mentorg.com with SMTP (15.11.1.6/15.5+MGC-TD 2.08) id AA24221; Wed, 6 Apr 94 11:54:45 -0700 Received: from vhdl.vhdl.org by mgc.mentorg.com with SMTP (16.6/15.5+MGC-TD 2.20) id AA01762; Wed, 6 Apr 94 11:54:38 -0700 Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15823; Wed, 6 Apr 94 11:50:16 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA12680 for ; Wed, 6 Apr 94 14:43:17 -0400 Date: Wed, 6 Apr 94 11:28:07 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA04108; Wed, 6 Apr 94 11:28:07 PDT Message-Id: <9404061828.AA04108@icx.com> To: ibis@vhdl.org Subject: IBIS in PCB Conference To IBIS Members: "Designing a Pentium Based Board Using High Speed PCB Design Kits" by Greg Seltzer, Mentor Graphics in the Proceedings of the Third Annual PCB Design Conference, March 29-31, 1994 mentions IBIS several times. Bob Ross, Interconnectix, Inc. From cpk@Cadence.COM Wed Apr 6 13:27:17 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16647; Wed, 6 Apr 94 13:27:17 PDT Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id NAA14725 for ; Wed, 6 Apr 1994 13:25:05 -0700 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma014650; Wed Apr 6 13:24:04 1994 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA22900; Wed, 6 Apr 94 13:17:50 -0700 Received: by hot (5.65+/1.5) id AA00622; Wed, 6 Apr 94 16:23:32 -0400 Date: Wed, 6 Apr 94 16:23:32 -0400 From: cpk@cadence.com (C. Kumar) Message-Id: <9404062023.AA00622@hot> To: ibis@vhdl.org Subject: Re: Modeling method and Intel non-monotonic model Hi folks: We use the exclusive method. However the power and ground clamp is always on and are assumed to be unswitched. Our simulator had no problem with Intel's non monotonic data. I tested it in various configurations driving long and short transmission lines. So my position remains the same. The modeller should output whatever data he/she thinks is correct. The problems of simulation should not be of any concern to the modeller. Simulators can be fixed! - kumar From Will_Hobbs@ccm2.jf.intel.com Wed Apr 6 13:33:12 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16758; Wed, 6 Apr 94 13:33:12 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 6 Apr 94 13:30:54 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 6 Apr 94 13:30:12 -0700 Received: from ccMail by jfsmt2.intel.com id AA765664231 Wed, 06 Apr 94 13:30:31 PST Date: Wed, 06 Apr 94 13:30:31 PST From: "Hobbs, Will" Message-Id: <9403067656.AA765664231@jfsmt2.intel.com> To: ibis@vhdl.org Subject: Minutes of 4/1 Meeting Date: April 6, 1994 From: Will Hobbs (503) 696-4369, fax (503) 696-4210 Will_Hobbs@ccm2.jf.intel.com XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum Intel Corporation 5200 NE Elam Young Pkwy, Hillsboro, Oregon 97124 USA and Derrick Duehren (503) 696-4299, fax (503) 696-4904 Intel Program Manager Subject: Minutes from IBIS Open Forum 4/1/94 To: Anacad Steffen Rochel Ansoft Henri Maramis Atmel Corporation Dan Terry Cadence Design Sandeep Khanna, Chris Reed, Pawel Chadzynski, Kumar* Contec Maah Sango*, Clark Cochran Digital Equipment Corp. Barry Katz* High Design Technology Michael Smith HyperLynx Steve Kaufer, Kellee Crisafulli* IBM Jay Diepenbrock IBM-Motorola alliance Lynn Warriner, Hoa Quoc, John Burnett Integrity Engineering Greg Doyle, Wayne Olhoft Intel Corporation Stephen Peters*, Don Telian, Will Hobbs* Arpad Muranyi*, D. Duehren, Lisa Huang* Interconnectix, Inc. Bob Ross* Intergraph Ian Dodd*, David Wiens IntuSoft Charles Hymowitz Logic Modeling Corp. Randy Harr Mentor Graphics Greg Seltzer, Ravender Goyal Meta-Software Mei Wong, Mei-Ling Wei MicroSim Arthur Wong, Jerry Brown, Graham Bell National Semiconductor Syed Huq North Carolina State U. Paul Franzon, Michael Steer, Steve Lipa Performance Signal Integrity Vivek Raghawan, Eric Bracken* Quad Design Jon Powell* Quantic Labs Mike Ventham, Zhen Mu Racal-Redac John Berrie Siemens Nixdorf Werner Rissiek, Olaf Rethmeier Texas Instruments Bob Ward Thomson-CSF/SCTF Jean Lebrun Zeelan Technology Hiro Moriyasu, George Opsahl CC: Intel Corporation Randy Wilhelm, Jerry Budelman, Intel IBIS team In the list above, attendees at the 4/1/94 meeting are indicated by * Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences are listed below: Date Bridge Number Reservation # 4/15/94 (415) 904-8944, 721615 4/29/94 (415) 904-8944, 721618 5/13/94 (415) 904-8944, 721619 5/20/94 Face-to-face, editing committee All meetings are 8:00 AM to 10:00 AM PST (16:00 to 18:00 UTC). We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. PLEASE NOTE: Because of the current large number of open issues, we decided at the 4/1 meeting to hold meetings on a bi-weekly basis until ratification of IBIS 2.0 is achieved. If you know of someone new who wants to join the e-mail reflector (ibis@vhdl.org) send e-mail to ibis-request@vhdl.org. ------------------------------------------------------------------------ 4/1/94 Meeting Agenda ---------------------- Check-in Intros of new IBIS participants Hobbs Review of 3/11/94 minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All Press updates Hobbs/All New Models Available All IBIS 2.0 Ratification Hobbs - DAC Conference 6/6 - 6/10 - Editing Committee IBIS Cookbook Hobbs Spice-to-IBIS Converter Lipa (NCSU) Sign of Current checking Chrisafulli, All BIRD 8, Spec. of V/I data monotonicity Crisafulli BIRD 9, Other model types Ross BIRD 10, Coupling Effects in Package Models Bracken BIRD 2, VIH, VIL Thresholds for Inputs Powell Egg 1, mutual pin coupling (ready to hatch?) Bracken Simulation temperatures (new BIRD?) Warriner Ramp measurement Reid, Ross, et. al. Egg 2, ramp table? Hobbs Canright paper Ward Formal BNF notation (BIRD?) Reed, Harr High freq. and EMI Goyal, et. al. Phased turn-on/off of multiple devices Powell Wrap-up, Next Meeting Plans Hobbs 1. Intros of new IBIS participants New participants: None. In fact, due to the meeting taking place on Good Friday, attendance was 30% lower than normal. 2. Review of 3/11 Minutes There were no corrections made to last month's minutes. 3. Miscellany/Announcements No new announcements. 4. Opens for new issues Jon Powell has questions regarding a new model developed by Intel for the Neptune 3.3v PCMC chip set which exhibits non-monotonic behavior with the pulldown when the voltage goes below ground. Kellee also has a customer that is using it and agrees that this is a probable problem. We agreed to discuss this issue later in the meeting. Kellee would also like to defer discussion of Bird 8 to a future meeting in favor of the new BIRD 11, IBIS_CHK checks for table sign. 5. Press updates There is an article on IBIS about to come out in EDA and ASIC magazine and the March issue of Computer Design, on page 38, devotes a couple of paragraphs to IBIS. 6. New Model Availability New models: Intel's 486DX4 model is about to go on BBS. Expect it in about a week. Arpad also has some new models that are ready for posting. AR, Stephen, Arpad, get models up on the vhdl.org BBS. 7. IBIS 2.0 Ratification: DAC Meeting, Editing Committee Jon Powell proposed the meeting take place on Sunday, from 1-6, with Monday as an overflow day. Jon could provide facilities that day. Various members preferred not to meet on Sunday and Kumar offered for Cadence to provide a room on any day, and needs the number of participants. We tentatively set the meeting for 8-5 on Thursday, 6/9. AR Will, send out notice, ask for RSVPs, for 6/9, 8-5. -- Done Will suggested we convene an IBIS Birds of a Feather session to be held through DAC. Bob Ward said that to do this only requires that 10 people express interest and DAC will supply a time and a room. Bob was volunteered to follow through on this. AR, Bob Ward, get Birds of a Feather session on DAC agenda. Launch note to reflector to get at least 10 replies from those interested in attending. -- Done Regarding the 5/20 editing get-together in Oregon, it was suggested we divide up tasks into controversial/non-controversial topics and quickly close on the non-controversial ones and tackle the remainder separately. Possibly work in sub-groups. 8. IBIS Cookbook Intel has completed its first revision of the internal IBIS Modeling Cookbook, and has made its first pass at a "sanitized" version for use by the forum. Will solicited volunteers to help get this in shape for the forum, and the following individuals stepped forward: Jon Powell, Bob Ross, Kellee Chrisafulli, Maah Saango, Barrie Katz, Arpad Muranyi, Kumar and Eric Bracken. AR Will, organize the review and editing effort for the cookbook. -- WIP 9. Spice to IBIS Bob Ross has used sp2ibis with Pspice and provided some feedback to Steve. Bob found some differences between Pspice results and Berkeley Spice, gave Steve that feedback and another iteration is underway. Bob judges the program usable, but more work is required. Barrie at DEC has it and will be using it soon. Jon Powell: How will it be used? If it is to be used primarily by IC vendors, it does not have to be as clean; if its target is customers, it must be cleaner. Kellee: IC vendors are #1, because they will have the greatest impact. Bob Ross: But it will be public domain, so anyone can use it. Jon is concerned if there is a minor bug that might create major glitch, a model review would be required, so modeling and buffer expertise would be required to be successful, or the evaluation of Sp2ibis will have to be greater. Kellee: maybe we should ask Steve to add something in the program's output to indicate need to correlate resulting model against the original design (a disclaimer or caveat). There was a short discussion about what to do about released IBIS models that had erroneous behavior. Is there a way to resolve such issues? Jon suggested that models should contain the originator's name, or some way to get a message back to originator. AR Jon, organize thoughts, post to reflector. 10. New Issue: Non-Monotonic Pull-Down Behavior Re: pulldown on Neptune, Arpad on line. Jon feels the pulldown transistor becomes linear, and doesn't believe the curve. Arpad had dissected the design and checked the devices and verified the behavior as reflected in the model. AR Arpad, write up a discussion of this for the reflector. Jon: if you are right, all the other IBIS models are wrong. Kellee: The question is whether in the negative region is the diode carrying the current or is the pulldown? Arpad: The models have not always been correlated in that region. Earlier models are still useful, because they are still more accurate in the forward biased diode regions than many other spice models that are out there. Arpad would like to continue this discussion in a forum where we can draw pictures, and would like to add this discussion to the cookbook. Jon: Quad does not model non-monotonic parts. The model that Arpad is generating will not work in Quad tools. Arpad questions whether Jon can use the data together-- the transistor is non-monotonic, but the diode and the diode/transistor combination do not. Maah: we're confusing 2 issues-- what does the data look like, and how do we model it? ARs, Arpad, post description of his findings that led him to the new model data. Specify one particular model for everyone to look at. psc_a2.ibs 11. BIRD 11, IBIS_CHK Changes Kellee Crisafulli proposes three changes in this BIRD, each related to the sign of VI table data, which has proven to be a common pitfall among new modelers. First, the BIRD proposes adding a comment to the IBIS specification discussing the sign of VI table data; second, add checking to ibis_chk for the correct sign, using the algorithm tuned through reflector feedback; and third, add a note to the ibis_chk source saying a BIRD is required to change the source. Proposed changes 1 and 3 appear OK to group, with the additional comment that source licensees are free to modify their own source, but not to post the result. Only the ibis_chk czar (Jon Powell) can post modified versions of ibis_chk, and that requires a ratified BIRD to initiate. Regarding change 2, there is controversy about the sign of the ECL example. Kellee pulled the example out of the IBIS V1.1 spec, which was a CMOS example, and indicated that if this was an ECL example then there would be a sign error because for ECL pulldown, VI is Vcc-V per BIRD 4. Kellee feels that right thing to do is to change the sign and use ECL type data and present a correct ECL table, but doesn't have ECL data. Kumar has ECL data which he offered to supply for inclusion in the BIRD. AR Kumar, post ECL model to reflector, Kellee, use that data in the BIRD. AR Kellee, change the proposed ibis_chk notice to indicate that it is OK to change your own source code, but not the global one without a supporting BIRD. 12. Wrap-up Because we ran out of time, and because a number of people did not attend due to the meeting taking place on Good Friday, we decided to convene on a bi-weekly basis until DAC so we could get 2.0 in shape. Thus, next meeting will be on Bad Friday, 4/15. (For those non-U.S. citizens reading this, April 15 is when Americans must pay their taxes.) AR Will-- make meeting bi-weekly until DAC, post new bridge numbers. -- Done. Dates and numbers appear on the first page of these minutes. From jonp@qdt.com Wed Apr 6 16:19:32 1994 Return-Path: Received: from relay1.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18321; Wed, 6 Apr 94 16:19:32 PDT Received: from uucp4.uu.net by relay1.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwknd19296; Wed, 6 Apr 94 19:17:08 -0400 Received: from qdt.UUCP by uucp4.uu.net with UUCP/RMAIL ; Wed, 6 Apr 1994 19:17:13 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA01017; Wed, 6 Apr 94 15:02:48 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA17819; Wed, 6 Apr 94 15:02:48 PDT Date: Wed, 6 Apr 94 15:02:48 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404062202.AA17819@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA07306; Wed, 6 Apr 94 15:02:49 PDT To: uunet!cadence.com!cpk@uunet.UU.NET Cc: ibis@vhdl.org In-Reply-To: C. Kumar's message of Wed, 6 Apr 94 16:23:32 -0400 <9404062023.AA00622@hot> Subject: Modeling method and Intel non-monotonic model Kumar, Least we be lead astray, The issue being debated here is not "should we model correct data no matter what it is" but "is the data correct?". jonp From bward@sugar.NeoSoft.COM Wed Apr 6 17:56:27 1994 Return-Path: Received: from mail.barrnet.net by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18971; Wed, 6 Apr 94 17:56:27 PDT Received: from sugar.NeoSoft.COM by mail.barrnet.net (5.67/1.37) id AA29814; Wed, 6 Apr 94 17:32:59 -0700 Received: by sugar.NeoSoft.COM id AA05941 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Wed, 6 Apr 1994 19:32:00 -0500 Message-Id: <199404070032.AA05941@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: BOF at DAC Date: Wed, 6 Apr 94 19:31:56 CDT To all on the ibis forum = We will be organizing a Birds of a Feather session at DAC this year! All the BOF sessions are to be held at the Marriott after the show floor closes on Wednesday afternoon ( so about 5 PM-ish ) and are to be finished just before the big party starts, also at the Marriott, ( so about 7:30 PM-ish ). If we have at 10 people sign up, the DAC office will assign us a meeting room, furnish seating, an overhead projector, and supplies. We are also asked by the DAC office to advertise the session for public attendance on the bulletin board by the information desk. I am suggesting that we have a supply of blamk overhead sheets and a supply of appropriate marker pens to use it as a blackboard, and that we have some slides ready to show an overview of ibis as a conversation starter. Possibly some pages from the overview document. The actual presentation should not be more than 5 to 10 minutes, and the rest of the time be taken in totally informal conversation about ibis. The only restriction is that we must not become commercial in tone and start selling a product. The discussion must remain general and philosophical. I am arranging with the graphic artist here at TI to make up a poster for me for the advertising of the session. I will be arriving the weekend before DAC, so I can get it posted and so on. In order for us to be sure of a room assignment, would those of you on the reflector who feel confident they can be there please let me know at my email address, bward@neosoft.com, and I will send the count to the DAC office. I would like to send a count by the end of next week, if at all possible, so by then or when I have at least 10, whichever comes first ... Thanks, Bob bward@neosoft.com  From cpk@Cadence.COM Thu Apr 7 06:53:16 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA27361; Thu, 7 Apr 94 06:53:16 PDT Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id GAA25011 for ; Thu, 7 Apr 1994 06:51:06 -0700 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma024988; Thu Apr 7 06:50:38 1994 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA03326; Thu, 7 Apr 94 06:44:18 -0700 Received: by hot (5.65+/1.5) id AA00813; Thu, 7 Apr 94 09:50:09 -0400 Date: Thu, 7 Apr 94 09:50:09 -0400 From: cpk@cadence.com (C. Kumar) Message-Id: <9404071350.AA00813@hot> To: ibis@vhdl.org Subject: Re: Modeling method and Intel non-monotonic model Reflecting more on this issue.. Even though the data from Intel contained non monotonicity, the model itself worked out nicely because of the "addition" effect of the clamps. But there may arise cases where we may have non monotonocity in the operating region which may real or may be an artifact of the modelling method and software. Worse still , if the simulations do not converge, it is almost impossible to tell whether it is an artifact of the simulator or the real device itself is unstable. In such cases , which Jon and Kellee may be alluding to , we may consider issuing general warning about the presence of non monotonic data. - Kumar From bob@icx.com Thu Apr 7 11:07:28 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29863; Thu, 7 Apr 94 11:07:28 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA08362 for ; Thu, 7 Apr 94 13:56:43 -0400 Date: Thu, 7 Apr 94 10:29:08 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA07634; Thu, 7 Apr 94 10:29:08 PDT Message-Id: <9404071729.AA07634@icx.com> To: ibis@vhdl.org Subject: Meeting Times To IBIS Committee: Because of the shift to Daylight Savings Time, the Friday 8:00 AM to 10:00 AM PDT meeting times should now be 15:00 to 17:00 UTC. Bob Ross, Interconnectix, Inc. From Will_Hobbs@ccm2.jf.intel.com Thu Apr 7 12:25:46 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00615; Thu, 7 Apr 94 12:25:46 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Thu, 7 Apr 94 12:23:23 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Thu, 7 Apr 94 12:22:56 -0700 Received: from ccMail by jfsmt2.intel.com id AA765746594 Thu, 07 Apr 94 12:23:14 PST Date: Thu, 07 Apr 94 12:23:14 PST From: "Hobbs, Will" Message-Id: <9403077657.AA765746594@jfsmt2.intel.com> To: ibis@vhdl.org, bob@icx.com ( Bob Ross) Subject: Re: Meeting Times Bob, and others, Thanks for pointing that out. I will correct that in future minutes. Will To IBIS Committee: Because of the shift to Daylight Savings Time, the Friday 8:00 AM to 10:00 AM PDT meeting times should now be 15:00 to 17:00 UTC. Bob Ross, Interconnectix, Inc. From speters@ichips.intel.com Thu Apr 7 17:39:31 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02954; Thu, 7 Apr 94 17:39:31 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Thu, 7 Apr 94 17:37:20 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Thu, 7 Apr 94 17:36:57 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Thu, 7 Apr 94 17:37:09 PDT Message-Id: <9404080037.AA26224@xtg801.intel.com> To: ibis@vhdl.org Subject: EGG #2 -- controlled rise-time devices Date: Thu, 07 Apr 1994 17:37:08 -0700 From: Stephen Peters Hello Fellow IBISIANS -- In this egg I am proposing a method that allows IBIS to handle controlled rise-time devices by describing the output waveform with a a 'percent voltage' vs 'percent time' curve. First, some background: The past month or so I have been trying to model a set of buffers that have edge rate control via phased turn on of multiple output transistors. As shown in FIG 1, a set of transistors are ganged together and turned on at slightly different times, thus shaping the output waveform as shown in FIG 2. _ | ___________|___________O pin | | | _| _| _| g1 -| g2 -| g3 -| |_ |_ |_ | | | _|_______|_______|__ gnd FIG 1. -- example pulldown stage with phased turn on. | *************** | * * | * * | ** * volts | * * | * * | * * | ** * | * * | * * | * * |_______________________________________________________ time FIG 2. -- example shaped output waveform As shown in FIG 2, the output waveform is not a smooth curve. Using the standard Dv/Dt and IV curve methodology an IBIS model was not able to successfully predict either the time it takes to reach logic thresholds or the maximum Dv/Dt of the waveform (critical for determining the maximum allowable stub length in a layout topology.) The only way I have found to build an accurate model of the buffer is to scale the I-V curve of the buffer with a second curve that describes the 'percent output voltage' (%V) vs. the "percent rise time (%T). Theory: The problem is that the standard I-V curve, taken under what are effectively DC conditions, do not describe the I-V characteristics of the device while the output is in transition. As transistors are turning on or off, the I-V characteristics change. The idea behind the %V - %T methodology is that, while the output transistors are turning on (i.e. the output is in transition), the I/V characteristics of the output can be described as a *scaled* version of the final DC I-V characteristics. For example, suppose the output took 3ns to reach its final DC I-V value, each transistor was identical (1/3 the total drive strength) and each transistor turned on 1ns apart. After 1ns the output has obtained 33% of its final DC strength, after 2ns it has obtained 66% of its final DC strength and after 3ns it is at 100% of its final DC strength. The output I/V characteristics have been effectively scaled by a specific percentage, based on the 100% rise time of the output waveform. A (really) simplified behavioral model of this type looks like the following: _ --|----------------------------|---|_| output pin | ____________ ___ _|_ |__| V-I curve |---| M | | | | generator | | U |---| | | ___| | | L | | V | (current source) | |___________| |_T_| |___| | ___________ | | time ramp-----| %V - %T |______| | generator | | curve | | | |__________| | | | __|____________________________|____ The I-V curves are obtained as always, the %V - %T curve is obtained by picking points off a graph (or table) of the output waveform. Both the I-V and %V - %T data is used to determine the final output current. Results: I've modeled a real live example of a buffer of this type using Quad Design's version of the %V - %T methodology. With the Quad software I am able to match the output waveform almost exactly -- for a given resistive load (i.e. get a %V - %T curve from a transistor level simulation, enter the data into the Quad model, then do a Quad simulation into the same load and compare results). As one changes the load the waveforms (Quad vs. transistor level) began to diverge, but in any case it is still far more accurate that the standard IBIS model. I also have preliminary results using an HSPICE model provided by Arpad Muranyi here at Intel. They look good but more testing is needed. Issues: This methodology has worked for a specific set of load topologies under a rather narrow range of Zo. I have not had a chance to try capacitive loads, nor try extreme ranges of Zo. My guess is that this method also works for edge rate control devices where the gate waveform is shaped, but I don't have a design to try it out on. I also don't have any data on how this method works if the transistors are not scaled linearly (HINT HINT -- anybody got any of these designs and would be willing to share simulation results with the group?) What I am looking for is feedback that addresses the usability, accuracy and robustness of this methodology. With your feedback I'd like to get an official bird together and posted in the next week or so, with an eye towards getting this into rev 2.0. Best Regards, Stephen Peters Intel Corp. From bward@sugar.NeoSoft.COM Thu Apr 7 20:18:32 1994 Return-Path: Received: from sugar.NeoSoft.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04458; Thu, 7 Apr 94 20:18:32 PDT Received: by sugar.NeoSoft.COM id AA19747 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Thu, 7 Apr 1994 22:15:17 -0500 Message-Id: <199404080315.AA19747@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: Update on BOF at DAC Date: Thu, 7 Apr 94 22:15:05 CDT Hi, Ibis folk! I already have eight folks who have expressed intention to be at the BOF. I need ten, so this is an excellent excellent start! I have also noticed quite a lot of mail bouncing to me as undeliverable when the reflector fans it out. So on the premise that I might be missing someone, I post this list. I presently have : myself Derrick Duehren Will Hobbs Paul Franzon Kumar Jon Powell Bob Ross Randy Harr If there is anyone else who has replied and I have missed it, please post it again. We are so close, just 2 to go. Sounds like public radio this time of year ... Bob bward@neosoft.com or bward@dadhb1.ti.com From 71436.1314@CompuServe.COM Thu Apr 7 21:46:41 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from dub-img-1.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04959; Thu, 7 Apr 94 21:46:41 PDT Received: from localhost by dub-img-1.compuserve.com (8.6.4/5.930129sam) id AAA02882; Fri, 8 Apr 1994 00:44:31 -0400 Date: 08 Apr 94 00:39:41 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Bird 11.1 updated version Message-Id: <940408043941_71436.1314_HHB40-1@CompuServe.COM> From: Kellee Crisafulli To: Will and Derrick Re: Bird 11.1 with changes per the last meeting Date: April 6, 1994 I have made the changes per the last meeting. Please resubmit to the forum. (I wasn't sure if I need to submit a modified BIRD to you or just send it to the reflector) Thanks, Kellee ******************************************************************************* ******************************************************************************* Buffer Issue Resolution Document (BIRD) BIRD ID#: {don't fill in, will be filled in by Will Hobbs for tracking} ISSUE TITLE: Improving common error detection in IBIS_CHK program. REQUESTOR: Kellee Crisafulli, HyperLynx Inc. DATE SUBMITTED: 03-28-94 DATE REVISED: 03-28-94 DATE ACCEPTED BY IBIS OPEN FORUM: TBD ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: Several common problems with IBIS models are not detected with the present version of IBIS_CHK. Two main problems include: 1) Incorrect 'I'(current) signs in the V/I tables. 2) Pullup and POWER_clamp V/I tables are not VCC relative. This BIRD is directed at problem 1 only. A 2nd separate BIRD will be generated to address problem 2. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: The following changes apply to version 1.1 and forward versions of the IBIS_CHK program and including testing of some parameters for BIRD 7.2 for ECL model types *************************************************************************** Change 1- Add verbage on current direction. *************************************************************************** Keywords: [Pullup], [Pulldown], [GND_clamp], [POWER_clamp] Required: Yes, if they exist in the device Description: The data points under these keywords define the V/I curves of the pulldown and pullup structures of an output buffer and the V/I curves of the clamping diodes connected to the GND and the POWER pins, respectively. Currents are considered positive when their direction is into the component. *************************************************************************** Change 2- Add detection to IBIS_CHK program for V/I table 'I' sign errors. *************************************************************************** For each of the following V/I tables: Pullup, Pulldown, POWER_clamp, GND_clamp 1) Find the minimum and maximum voltage points (Vmin, Vmax) in the table. 2) IF:The current in the TYPICAL column corresponding to Vmax is less than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have decreasing current. ELSE: The table is assumed to have increasing current. Note: This works for all cases of discontinuities unless the magnitude of discontinuity is such that this model is in all probability competely unrealistic. Examples: *** example with non-monotonic data at the end point V: I: 0.00 0.0 4.90 50.0ma 4.91 49.9ma 4.93 56.7ma 5.00 3.0ma -> V/I table has increasing current (3.0 > 0) Vmax = 5.0, I =3.0mA Vmin = 0.0, I =0.0 *** example with negative to positve voltages with negative first V: I: -5.00 -0.1ma 0.00 0.0 5.00 100.0ma -> V/I table has increasing current (100 > -0.1) Vmax = 5.0, I=100mA Vmin = -5.0, I=-0.1mA *** example with table data entered postive voltages first V: I: 5.00 10.1ma 0.00 0.0 -5.00 -10.1ma -> V/I table has increasing current (10.1 > -10.1) Vmax = 5.0, I=10.1mA Vmin = -5.0, I=-10.1mA *** example with only two entrys V: I: 0.00 0.0 -5.00 10.1ma -> V/I table has decreasing current (0 < 10.1) Vmax = 0.0, I=0 Vmin = -5.0, I=10.1mA *** ECL example [Pullup] Voltage I(typ) I(min) I(max) 0.0 0 0 0 0.7 -0.2m -0.2m -0.2m 0.73 -0.4m -0.4m -0.4m 0.75 -0.8m -0.8m -0.8m 0.76 -1.2m -1.2m -1.2m 0.77 -1.6m -1.6m -1.6m 0.8 -4.4m -4.4m -4.4m 0.82 -7.6m -7.6m -7.6m 0.85 -14.2m -14.2m -14.2m 0.9 -30.0m -30.0m -30.0m 1.0 -58.0m -50.0m -68.0m -> V/I table has decreasing current ( -58 < 0) Vmax = 1.0, Ityp=-58mA Vmin = 0, Ityp=0 [Pulldown] Voltage I(typ) I(min) I(max) 0.0 0 0 0 1.6 -0.2m -0.2m -0.2m 1.62 -0.4m -0.4m -0.4m 1.64 -0.6m -0.6m -0.6m 1.65 -0.8m -0.8m -0.8m 1.66 -1.2m -1.2m -1.2m 1.67 -1.6m -1.6m -1.6m 1.68 -2.4m -2.4m -2.4m 1.69 -3.2m -3.2m -3.2m 1.70 -4.4m -4.4m -4.4m 1.72 -7.4m -7.4m -7.4m 1.75 -14.2m -14.2m -14.2m 1.8 -30.5m -30.5m -30.5m 1.9 -65.0m -60.0m -75.0m -> V/I table has decreasing current ( -65 < 0) Vmax = 1.9, Ityp=-65mA Vmin = 0.0, Ityp= 0 *** An abreviated INTEL model for a CMOS output |**************************************************************************** [Pulldown] | Voltage I(typ) I(min) I(max) -5.00V -38.70mA -29.47mA -51.22mA -1.00V -24.88mA -19.18mA -32.90mA -0.50V -14.35mA -11.06mA -19.05mA 0.00V -11.84pA -554.66pA -11.03pA 100.00mV 3.20mA 2.47mA 4.27mA 200.00mV 6.24mA 4.80mA 8.30mA 4.90V 38.68mA 29.45mA 51.18mA 5.00V 38.70mA 29.47mA 51.22mA 10.00V 39.96mA 30.37mA 53.06mA -> V/I table increasing [GND_clamp] | Voltage I(typ) I(min) I(max) -5.00V -680.00mA NA NA -1.10V -75.50mA NA NA -600.00mV -950.00uA NA NA -500.00mV -78.00uA NA NA -200.00mV 0.00pA NA NA -100.00mV 0.00pA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA -> V/I table increasing (0 > -680) [Pullup] | Voltage I(typ) I(min) I(max) -5.00V 38.14mA 27.33mA 54.76mA -4.50V 37.49mA 26.87mA 53.79mA -1.00V 17.13mA 12.81mA 23.55mA -0.50V 9.26mA 6.96mA 12.66mA 0.00V 13.57pA 613.51pA 11.04pA 100.00mV -1.96mA -1.48mA -2.67mA 200.00mV -3.87mA -2.92mA -5.27mA 500.00mV -9.26mA -6.96mA -12.66mA 1.80V -26.79mA -19.79mA -37.25mA 1.90V -27.74mA -20.46mA -38.64mA 4.60V -37.62mA -26.97mA -54.00mA 4.70V -37.76mA -27.06mA -54.20mA 5.00V -38.14mA -27.33mA -54.76mA 10.00V -44.52mA -33.72mA -61.15mA -> V/I table decreasing [POWER_clamp] | Voltage I(typ) I(min) I(max) -5.00V 1.05A NA NA -1.10V 79.00mA NA NA -1.00V 54.00mA NA NA -900.00mV 29.00mA NA NA -800.00mV 10.40mA NA NA -200.00mV 0.00uA NA NA -100.00mV 0.00uA NA NA 0.00V 0.00pA NA NA -> V/I table decreasing 3) IF the model is any of the following types:(Input_ECL, Output_ECL, I/O_ECL) { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has decreasing current - GND_clamp V/I table has increasing current } ELSE { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has increasing current - GND_clamp V/I table has increasing current } 4) If any table moves in the wrong direction report the following error message: 'Error found in xxx V/I table at line number nnn!'. Where xxx is one of the following Pullup, Pulldown, POWER_clamp, GND_clamp. Where nnn is the line number. Note: It is acceptable to stop the parser after the first line found with this error. *************************************************************************** Change 3- Add a header comment statement at the TOP of the IBIS_CHK program to insure that new changes to the IBIS_CHK program donot break tests that worked in old MAJOR versions. This approach makes the program larger however it insures the parser always works the same on older versions of IBIS. This apporach uses more memory, but has the reward of low maintaining costs. The IBIS_CHK program is very small and would not be effected by this until many revisions have occured. *************************************************************************** NOTICE TO ANY PERSON MODIFING THIS PROGRAM! ------------------------------------------- This program SHALL NOT BE MODIFIED unless there is an associated IBIS BIRD. Said BIRD shall be agreed upon by IBIS committee vote. Only the currently elected IBIS_CHK 'czar and programmer' is allowed to modify the source code. The present CZAR is Jon Powell (April 1994). The IBIS committee may also hire programmers from time to time to make major changes to the source code. Note: Source licensees are free to modify their own copies of this source code in any way they choose. Source licensees shall not redistribute the source code modified or otherwise. Source licensing is available from the IBIS open forum. The IBIS open forum is non-profit. The code for each MAJOR version of the IBIS_CHK program SHALL NOT BE MODIFIED when adding code for the next version of the IBIS specification. Instead completely new code for all functions and features shall be created. This may require duplication of numerous functions. Each function shall be preceded by VXX_ where XX is the MAJOR version of the IBIS specification which is being parsed and tested. A MAJOR version would for example be 1.x going to 2.x. A MINOR version would for example be 1.1 to 1.2. Functions using the above syntax would look as follows: V01_GetValue MINOR revisions DO NOT required new code. Startup code shall be provided at the top of the program which reads the version number from the IBIS file and runs the portion of the program corresponding to that MAJOR version. Code which is used only by the program startup function is not duplicated. ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Change 1) Suggested from inputs of several people in Email and at the at previous IBIS meetings. Change 2) Defective IBIS models are slipping through the IBIS_CHK program. A method for determining sign errors in V/I table was determined based on inputs from several people including: Kellee Crisafulli, HyperLynx Jon Powell, Quad Design Arpad, Intel Bob Ward, TI Bob Ross, Interconnectix Maah Sango, Contec I reviewed all the comments that have been submitted and I believe this method will work with all conditions mentioned so far. Change 3) I am proposing a method of insuring that future IBIS_CHK modifications donot effect the parsing of older IBIS files. This only applies to MAJOR revisions in the specification, like 2.0 comming up. This would not apply to this update, it would however be added to the program header information now and would apply to all future MAJOR updates to the IBIS specification. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: Comments about EMAIL leading up to this BIRD -------------------------------------------- From: Jon Powel, qdt Cases that will not work for proposed algorithm V: I: 0.0 0.0 3.5 50.0 3.51 49.9 3.52 49.8 3.53 49.7 5.0 100.0 any OC any OD If current is not negative at GND for the pullup then it cannot pullup? (except for ECL OC etc?). Action: problems fixed in BIRD 11.0 ****************** From: Arpad, Intel What happens if there are equal number of increases and decreases in a curve? Most of the curves I am generating lately do that and I do not think I am doing it wrong. Action: problems fixed in BIRD 11.0 ******************** Bob Ward, TI I think the proposed method of current sign determination might run into trouble in at least two cases. One is when there are exactly the same number of rising and falling segments. The other is the same problem one runs into testing for monotonicity of the independent variable. That problem is that very small oscillations occur on the "flat" part of a numerically generated curve, not so much because they are real, but because of the nature of small numbers, finite precision, and floating point round off. Action: Problems fixed in BIRD 11.0 ****************************** Bob Ross, Interconnectix, Inc. If this proposal is adopted, it would apply to just IBIS Version1.1. The polarity rules do not comply with proposed IBIS extensions BIRDS 3 and 4 for ECL type devices. For ECL type devices, the polarities of both the Pullup and Pulldown tables will go in the same (decreasing) direction because BOTH tables are tabulated referenced to Vcc using Vtable = Vcc - Vout. I am sure this will become another area of confusion, justifying a test. Action: Problem fixed BIRD 11.0 ************************** Maah Sango, Contec Microelectronics USA Inc 2. I agree with Bob Ross that the proposed scheme for enforcing data integrity will not work for ECL, nor for a few other device types. (See item 3 of the proposal). Either the "pullup" or the "pulldown" data for the ECL and other device types will violate these requirements. Action: Problem fixed Bird 11.0 3. The proposed scheme, item 3, will not always work even for CMOS unless we use only the magnitudes of the currents. Existing data for ageing (old) devices is sometimes presented with positive currents and sometimes with negative currents for CMOS pullup devices. Action: Problem fixed Bird 11.0 4. I am not sure that checking only the two end points will always guarantee the conclusions we are assuming here. Current(I) data in between these two points may increase or decrease and still be perfectly valid, particularly if we think of device types other than CMOS. Action: Numerous examples cited, none found that present a problem ******************************* Arpad, Intel If we JUST want a polarity checker for the MOST COMMON error, I have another most common error to check for: VCC-relative! That needed more explaining than the polarity of the current in my experience, and I have seen more people being confused about that. Should that also be checked for then? Action: Another Bird needs to be generated separate from Bird 11 ******************************************************************************* Changes from the April-1-94 IBIS meeting BIRD 11, IBIS_CHK Changes Kellee Crisafulli proposes three changes in this BIRD, each related to the sign of VI table data, which has proven to be a common pitfall among new modelers. First, the BIRD proposes adding a comment to the IBIS specification discussing the sign of VI table data; second, add checking to ibis_chk for the correct sign, using the algorithm tuned through reflector feedback; and third, add a note to the ibis_chk source saying a BIRD is required to change the source. Proposed changes 1 and 3 appear OK to group, with the additional comment that source licensees are free to modify their own source, but not to post the result. Only the ibis_chk czar (Jon Powell) can post modified versions of ibis_chk, and that requires a ratified BIRD to initiate. AR:Kellee, change the proposed ibis_chk notice to indicate that it is OK to change your own source code, but not the global one without a supporting BIRD. Action: Done Regarding change 2, there is controversy about the sign of the ECL example. Kellee pulled the example out of the IBIS V1.1 spec, which was a CMOS example, and indicated that if this was an ECL example then there would be a sign error because for ECL pulldown, VI is Vcc-V per BIRD 4. Kellee feels that right thing to do is to change the sign and use ECL type data and present a correct ECL table, but doesn't have ECL data. Kumar has ECL data which he offered to supply for inclusion in the BIRD. AR:Kumar, post ECL model to reflector, Kellee, use that data in the BIRD. Action: I have incorporated the model. AR Kellee, Two people noted that the directions of the current tests for the ECL were wrong. Kellee thought they were correct during the phone conversation. Action: I was wrong, and have changed them to correct the problem. From Derrick_Duehren@ccm2.jf.intel.com Thu Apr 7 22:14:21 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05117; Thu, 7 Apr 94 22:14:21 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pp8rR-000MNNC; Thu, 7 Apr 94 22:12 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Thu, 7 Apr 94 22:12:08 PST Date: Thu, 7 Apr 94 22:12:08 PST From: Derrick Duehren Message-Id: <940407221208_1@ccm.hf.intel.com> To: IBIS@vhdl.org Subject: IBIS BIRD 11.1 (update) Text item: Text_1 ****************************************************************************** ****************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 11.1 ISSUE TITLE: Improving common error detection in IBIS_CHK program REQUESTOR: Kellee Crisafulli, HyperLynx Inc. DATE SUBMITTED: March 28, 1994 DATE REVISED: March 28, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Several common problems with IBIS models are not detected with the present version of IBIS_CHK. Two main problems include: 1) Incorrect 'I'(current) signs in the V/I tables. 2) Pullup and POWER_clamp V/I tables are not VCC relative. This BIRD is directed at problem 1 only. A 2nd separate BIRD will be generated to address problem 2. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The following changes apply to version 1.1 and forward versions of the IBIS_CHK program and including testing of some parameters for BIRD 7.2 for ECL model types ****************************************************************************** Change 1- Add verbage on current direction. ****************************************************************************** Keywords: [Pullup], [Pulldown], [GND_clamp], [POWER_clamp] Required: Yes, if they exist in the device Description: The data points under these keywords define the V/I curves of the pulldown and pullup structures of an output buffer and the V/I curves of the clamping diodes connected to the GND and the POWER pins, respectively. Currents are considered positive when their direction is into the component. ****************************************************************************** Change 2- Add detection to IBIS_CHK program for V/I table 'I' sign errors. ****************************************************************************** For each of the following V/I tables: Pullup, Pulldown, POWER_clamp, GND_clamp 1) Find the minimum and maximum voltage points (Vmin, Vmax) in the table. 2) IF:The current in the TYPICAL column corresponding to Vmax is less than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have decreasing current. ELSE: The table is assumed to have increasing current. Note: This works for all cases of discontinuities unless the magnitude of discontinuity is such that this model is in all probability competely unrealistic. Examples: *** example with non-monotonic data at the end point V: I: 0.00 0.0 4.90 50.0ma 4.91 49.9ma 4.93 56.7ma 5.00 3.0ma -> V/I table has increasing current (3.0 > 0) Vmax = 5.0, I =3.0mA Vmin = 0.0, I =0.0 *** example with negative to positve voltages with negative first V: I: -5.00 -0.1ma 0.00 0.0 5.00 100.0ma -> V/I table has increasing current (100 > -0.1) Vmax = 5.0, I=100mA Vmin = -5.0, I=-0.1mA *** example with table data entered postive voltages first V: I: 5.00 10.1ma 0.00 0.0 -5.00 -10.1ma -> V/I table has increasing current (10.1 > -10.1) Vmax = 5.0, I=10.1mA Vmin = -5.0, I=-10.1mA *** example with only two entrys V: I: 0.00 0.0 -5.00 10.1ma -> V/I table has decreasing current (0 < 10.1) Vmax = 0.0, I=0 Vmin = -5.0, I=10.1mA *** ECL example [Pullup] Voltage I(typ) I(min) I(max) 0.0 0 0 0 0.7 -0.2m -0.2m -0.2m 0.73 -0.4m -0.4m -0.4m 0.75 -0.8m -0.8m -0.8m 0.76 -1.2m -1.2m -1.2m 0.77 -1.6m -1.6m -1.6m 0.8 -4.4m -4.4m -4.4m 0.82 -7.6m -7.6m -7.6m 0.85 -14.2m -14.2m -14.2m 0.9 -30.0m -30.0m -30.0m 1.0 -58.0m -50.0m -68.0m -> V/I table has decreasing current ( -58 < 0) Vmax = 1.0, Ityp=-58mA Vmin = 0, Ityp=0 [Pulldown] Voltage I(typ) I(min) I(max) 0.0 0 0 0 1.6 -0.2m -0.2m -0.2m 1.62 -0.4m -0.4m -0.4m 1.64 -0.6m -0.6m -0.6m 1.65 -0.8m -0.8m -0.8m 1.66 -1.2m -1.2m -1.2m 1.67 -1.6m -1.6m -1.6m 1.68 -2.4m -2.4m -2.4m 1.69 -3.2m -3.2m -3.2m 1.70 -4.4m -4.4m -4.4m 1.72 -7.4m -7.4m -7.4m 1.75 -14.2m -14.2m -14.2m 1.8 -30.5m -30.5m -30.5m 1.9 -65.0m -60.0m -75.0m -> V/I table has decreasing current ( -65 < 0) Vmax = 1.9, Ityp=-65mA Vmin = 0.0, Ityp= 0 *** An abreviated INTEL model for a CMOS output | [Pulldown] | Voltage I(typ) I(min) I(max) -5.00V -38.70mA -29.47mA -51.22mA -1.00V -24.88mA -19.18mA -32.90mA -0.50V -14.35mA -11.06mA -19.05mA 0.00V -11.84pA -554.66pA -11.03pA 100.00mV 3.20mA 2.47mA 4.27mA 200.00mV 6.24mA 4.80mA 8.30mA 4.90V 38.68mA 29.45mA 51.18mA 5.00V 38.70mA 29.47mA 51.22mA 10.00V 39.96mA 30.37mA 53.06mA -> V/I table increasing [GND_clamp] | Voltage I(typ) I(min) I(max) -5.00V -680.00mA NA NA -1.10V -75.50mA NA NA -600.00mV -950.00uA NA NA -500.00mV -78.00uA NA NA -200.00mV 0.00pA NA NA -100.00mV 0.00pA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA -> V/I table increasing (0 >-680) [Pullup] | Voltage I(typ) I(min) I(max) -5.00V 38.14mA 27.33mA 54.76mA -4.50V 37.49mA 26.87mA 53.79mA -1.00V 17.13mA 12.81mA 23.55mA -0.50V 9.26mA 6.96mA 12.66mA 0.00V 13.57pA 613.51pA 11.04pA 100.00mV -1.96mA -1.48mA -2.67mA 200.00mV -3.87mA -2.92mA -5.27mA 500.00mV -9.26mA -6.96mA -12.66mA 1.80V -26.79mA -19.79mA -37.25mA 1.90V -27.74mA -20.46mA -38.64mA 4.60V -37.62mA -26.97mA -54.00mA 4.70V -37.76mA -27.06mA -54.20mA 5.00V -38.14mA -27.33mA -54.76mA 10.00V -44.52mA -33.72mA -61.15mA -> V/I table decreasing [POWER_clamp] | Voltage I(typ) I(min) I(max) -5.00V 1.05A NA NA -1.10V 79.00mA NA NA -1.00V 54.00mA NA NA -900.00mV 29.00mA NA NA -800.00mV 10.40mA NA NA -200.00mV 0.00uA NA NA -100.00mV 0.00uA NA NA 0.00V 0.00pA NA NA -> V/I table decreasing 3) If the model is any of the following types:(Input_ECL, Output_ECL, I/O_ECL) { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has decreasing current - GND_clamp V/I table has increasing current } ELSE { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has increasing current - GND_clamp V/I table has increasing current } 4) If any table moves in the wrong direction report the following error message: 'Error found in xxx V/I table at line number nnn!'. Where xxx is one of the following: Pullup, Pulldown, POWER_clamp, GND_clamp. Where nnn is the line number. Note: It is acceptable to stop the parser after the first line found with this error. ****************************************************************************** Change 3- Add a header comment statement at the TOP of the IBIS_CHK program to insure that new changes to the IBIS_CHK program donot break tests that worked in old MAJOR versions. This approach makes the program larger however it insures the parser always works the same on older versions of IBIS. This apporach uses more memory, but has the reward of low maintaining costs. The IBIS_CHK program is very small and would not be effected by this until many revisions have occured. ****************************************************************************** NOTICE TO ANY PERSON MODIFING THIS PROGRAM! ------------------------------------------- This program SHALL NOT BE MODIFIED unless there is an associated IBIS BIRD. Said BIRD shall be agreed upon by IBIS committee vote. Only the currently elected IBIS_CHK 'czar and programmer' is allowed to modify the source code. The present CZAR is Jon Powell (April 1994). The IBIS committee may also hire programmers from time to time to make major changes to the source code. Note: Source licensees are free to modify their own copies of this source code in any way they choose. Source licensees shall not redistribute the source code modified or otherwise. Source licensing is available from the IBIS open forum. The IBIS open forum is non-profit. The code for each MAJOR version of the IBIS_CHK program SHALL NOT BE MODIFIED when adding code for the next version of the IBIS specification. Instead completely new code for all functions and features shall be created. This may require duplication of numerous functions. Each function shall be preceded by VXX_ where XX is the MAJOR version of the IBIS specification which is being parsed and tested. A MAJOR version would for example be 1.x going to 2.x. A MINOR version would for example be 1.1 to 1.2. Functions using the above syntax would look as follows: V01_GetValue MINOR revisions DO NOT required new code. Startup code shall be provided at the top of the program which reads the version number from the IBIS file and runs the portion of the program corresponding to that MAJOR version. Code which is used only by the program startup function is not duplicated. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Change 1) Suggested from inputs of several people in Email and at previous IBIS meetings. Change 2) Defective IBIS models are slipping through the IBIS_CHK program. A method for determining sign errors in V/I table was determined based on inputs from several people including: Kellee Crisafulli, HyperLynx Jon Powell, Quad Design Arpad, Intel Bob Ward, TI Bob Ross, Interconnectix Maah Sango, Contec I reviewed all the comments that have been submitted and I believe this method will work with all conditions mentioned so far. Change 3) I am proposing a method of insuring that future IBIS_CHK modifications donot effect the parsing of older IBIS files. This only applies to MAJOR revisions in the specification, like 2.0 comming up. This would not apply to this update, it would however be added to the program header information now and would apply to all future MAJOR updates to the IBIS specification. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: Comments about EMAIL leading up to this BIRD -------------------------------------------- From: Jon Powel, qdt Cases that will not work for proposed algorithm V: I: 0.0 0.0 3.5 50.0 3.51 49.9 3.52 49.8 3.53 49.7 5.0 100.0 any OC any OD If current is not negative at GND for the pullup then it cannot pullup? (except for ECL OC etc?). Action: problems fixed in BIRD 11.0 ****************** From: Arpad, Intel What happens if there are equal number of increases and decreases in a curve? Most of the curves I am generating lately do that and I do not think I am doing it wrong. Action: problems fixed in BIRD 11.0 ******************** Bob Ward, TI I think the proposed method of current sign determination might run into trouble in at least two cases: One is when there are exactly the same number of rising and falling segments. The other is the same problem one runs into testing for monotonicity of the independent variable. That problem is that very small oscillations occur on the "flat" part of a numerically generated curve, not so much because they are real, but because of the nature of small numbers, finite precision, and floating point round off. Action: Problems fixed in BIRD 11.0 ****************************** Bob Ross, Interconnectix, Inc. If this proposal is adopted, it would apply to just IBIS Version1.1. The polarity rules do not comply with proposed IBIS extensions BIRDS 3 and 4 for ECL type devices. For ECL type devices, the polarities of both the Pullup and Pulldown tables will go in the same (decreasing) direction because BOTH are tabulated referenced to Vcc using Vtable = Vcc - Vout. I am sure this will become another area of confusion, justifying a test. Action: Problem fixed BIRD 11.0 ************************** Maah Sango, Contec Microelectronics USA Inc 2. I agree with Bob Ross that the proposed scheme for enforcing data integrity will not work for ECL, nor for a few other device types. (See item 3 of the proposal). Either the "pullup" or the "pulldown" data for the ECL and other device types will violate these requirements. Action: Problem fixed Bird 11.0 3. The proposed scheme, item 3, will not always work even for CMOS unless we use only the magnitudes of the currents. Existing data for ageing (old) devices is sometimes presented with positive currents and sometimes with negative currents for CMOS pullup devices. Action: Problem fixed Bird 11.0 4. I am not sure that checking only the two end points will always guarantee the conclusions we are assuming here. Current(I) data in between these two points may increase or decrease and still be perfectly valid, particularly if we think of device types other than CMOS. Action: Numerous examples cited, none found that present a problem ******************************* Arpad, Intel If we JUST want a polarity checker for the MOST COMMON error, I have another most common error to check for: VCC-relative! That needed more explaining than the polarity of the current in my experience, and I have seen more people being confused about that. Should that also be checked for then? Action: Another Bird needs to be generated separate from Bird 11 ****************************************************************************** Changes from the April-1-94 IBIS meeting BIRD 11, IBIS_CHK Changes Kellee Crisafulli proposes three changes in this BIRD, each related to the sign of VI table data, which has proven to be a common pitfall among new modelers. First, the BIRD proposes adding a comment to the IBIS specification discussing the sign of VI table data; second, add checking to ibis_chk for the correct sign, using the algorithm tuned through reflector feedback; and third, add a note to the ibis_chk source saying a BIRD is required to change the source. Proposed changes 1 and 3 appear OK to group, with the additional comment that source licensees are free to modify their own source, but not to post the result. Only the ibis_chk czar (Jon Powell) can post modified versions of ibis_chk, and that requires a ratified BIRD to initiate. AR:Kellee, change the proposed ibis_chk notice to indicate that it is OK to change your own source code, but not the global one without a supporting BIRD. Action: Done Regarding change 2, there is controversy about the sign of the ECL example. Kellee pulled the example out of the IBIS V1.1 spec, which was a CMOS example, and indicated that if this was an ECL example then there would be a sign error because for ECL pulldown, VI is Vcc-V per BIRD 4. Kellee feels that right thing to do is to change the sign and use ECL type data and present a correct ECL table, but doesn't have ECL data. Kumar has ECL data which he offered to supply for inclusion in the BIRD. AR:Kumar, post ECL model to reflector, Kellee, use that data in the BIRD. Action: I have incorporated the model. AR Kellee, Two people noted that the directions of the current tests for the ECL were wrong. Kellee thought they were correct during the phone conversation. Action: I was wrong, and have changed them to correct the problem. From cpk@Cadence.COM Fri Apr 8 08:54:16 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12266; Fri, 8 Apr 94 08:54:16 PDT Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id IAA29915 for ; Fri, 8 Apr 1994 08:52:05 -0700 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma029880; Fri Apr 8 08:51:11 1994 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA09536; Fri, 8 Apr 94 08:44:41 -0700 Received: by hot (5.65+/1.5) id AA02737; Fri, 8 Apr 94 11:50:41 -0400 Date: Fri, 8 Apr 94 11:50:41 -0400 From: cpk@cadence.com (C. Kumar) Message-Id: <9404081550.AA02737@hot> To: ibis@vhdl.org Subject: Re: EGG #2 -- controlled rise-time devices The important issue for the user is how many v-t curves to generate and for how many loads. In principal the number of v-t curves should be unrestricted. The v-t data format should specify whether the data is for rising, falling and what load it was generated for. I feel uncomfortable with the modelling strategy which says that the behavior has to be scaled from dc which it may not have any relation to. In a ideal case I would have preferred i-v data at each time point. -kumar From Arpad_Muranyi@ccm.fm.intel.com Fri Apr 8 15:21:53 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15055; Fri, 8 Apr 94 15:21:53 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0ppOti-000MNUC; Fri, 8 Apr 94 15:19 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Fri, 8 Apr 94 15:19:34 PST Date: Fri, 8 Apr 94 15:19:34 PST From: Arpad Muranyi Message-Id: <940408151934_2@ccm.hf.intel.com> To: cpk@Cadence.COM, ibis@vhdl.org Subject: Re[2]: EGG #2 -- controlled rise-time devices Kumar, I agree with what you are saying, but that actually means that we want to describe a surface point by point. This is the best way, but would require a huge data table for each structure. For example, if you allow 100 data points for each independent axis (V, t) you end up with 100^2 data points, which you have to multiply by three, since we have three numbers describing each point. I don't think we can handle that yet. The proposed method would at least give us a good start. Arpad The important issue for the user is how many v-t curves to generate and for how many loads. In principal the number of v-t curves should be unrestricted. The v-t data format should specify whether the data is for rising, falling and what load it was generated for. I feel uncomfortable with the modelling strategy which says that the behavior has to be scaled from dc which it may not have any relation to. In a ideal case I would have preferred i-v data at each time point. -kumar From Arpad_Muranyi@ccm.fm.intel.com Fri Apr 8 17:20:59 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15916; Fri, 8 Apr 94 17:20:59 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0ppQl7-000MNWC; Fri, 8 Apr 94 17:18 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Fri, 8 Apr 94 17:18:48 PST Date: Fri, 8 Apr 94 17:18:48 PST From: Arpad Muranyi Message-Id: <940408171848_2@ccm.hf.intel.com> To: ibis@vhdl.org Subject: Re[2]: EGG #2 -- controlled rise-time devices ---------------------------- Forwarded with Changes --------------------------- From: Arpad Muranyi at JFCCM3 Date: 4/8/94 3:40PM *To: ibis@vhdl.org at Internet_Gateway *To: cpk@Cadence.COM at Internet_Gateway Subject: Re[2]: EGG #2 -- controlled rise-time devices ------------------------------------------------------------------------------- I am not sure if you got this, so I am trying again. (It came back to me) Kumar, I agree with what you are saying, but that actually means that we want to describe a surface point by point. This is the best way, but would require a huge data table for each structure. For example, if you allow 100 data points for each independent axis (V, t) you end up with 100^2 data points, which you have to multiply by three, since we have three numbers describing each point. I don't think we can handle that yet. The proposed method would at least give us a good start. Arpad The important issue for the user is how many v-t curves to generate and for how many loads. In principal the number of v-t curves should be unrestricted. The v-t data format should specify whether the data is for rising, falling and what load it was generated for. I feel uncomfortable with the modelling strategy which says that the behavior has to be scaled from dc which it may not have any relation to. In a ideal case I would have preferred i-v data at each time point. -kumar From bob@icx.com Fri Apr 8 19:09:12 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16568; Fri, 8 Apr 94 19:09:12 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA19700 for ; Fri, 8 Apr 94 22:02:42 -0400 Date: Fri, 8 Apr 94 18:59:14 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA12402; Fri, 8 Apr 94 18:59:14 PDT Message-Id: <9404090159.AA12402@icx.com> To: ibis@vhdl.org Subject: BIRD11.1 COMMENTS Kellee and IBIS Committee: I am in basic agreement with BIRD11.1 and plan to support it. There are some "nitpick" technical points that could be a problem and cause ambiguity. They relate to the fundamental question: Will tables composed of only 0 mA entries or of only constant current entries be flagged as an error in Version 2.0? They are acceptable in Version 1.1, and could be useful to get around some Model_type omissions and do some (beyond IBIS) constant current source modeling or biasing of tables modeling. I prefer to retain the capability of having table with only 0 mA or of constant current. However, because Version 2.0 will contain all of the Model_types I need, I can accept an explicit restriction that no table may consist of only 0 mA or constant current entries. What is the intention of BIRD11.1 is in this regard? Here are some "editorial" changes which relate exactly to this question. I. In BIRD11.1, Change 2 states, "For each of the following V/I tables: Pullup, Pulldown, POWER_clamp, GND_clamp 1) Find the minimum and maximum voltage points (Vmin, Vmax) in the table. 2) IF:The current in the TYPICAL column corresponding to Vmax is less than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have decreasing current. ELSE: The table is assumed to have increasing current." >From this wording, "increasing" includes both EQUAL and INCREASING. I believe you really mean: "2) IF:The current in the TYPICAL column corresponding to Vmax is less than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have decreasing current. ELSE IF:The current in the TYPICAL column corresponding to Vmax is greater than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have increasing current. ELSE: The table is assumed to have equal current." The last "ELSE" condition may be omitted if it is not used based on how case II is handled. II. Here is the change I really want, but do not need as long as we are all in agreement with our expectations. The test in Change 2 states: "3) If the model is any of the following types:(Input_ECL, Output_ECL, I/O_ECL) { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has decreasing current - GND_clamp V/I table has increasing current } ELSE { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has decreasing current - Pulldown V/I table has increasing current - GND_clamp V/I table has increasing current }" I would prefer the valid cases be enlarged: 3) If the model is any of the following types:(Input_ECL, Output_ECL, I/O_ECL) { Verify that: - Pullup V/I table has decreasing current - POWER_clamp V/I table has equal or decreasing current - Pulldown V/I table has decreasing current - GND_clamp V/I table has equal or increasing current } ELSE { Verify that: - Pullup V/I table has equal or decreasing current - POWER_clamp V/I table has equal or decreasing current - Pulldown V/I table has equal or increasing current - GND_clamp V/I table has equal or increasing current } III. Finally Change 2, section 4) states: "4) If any table moves in the wrong direction report the following error message: 'Error found in xxx V/I table at line number nnn!'. Where xxx is one of the following: Pullup, Pulldown, POWER_clamp, GND_clamp. Where nnn is the line number. Note: It is acceptable to stop the parser after the first line found with this error." I could technically be very happy with the wording as is, and yet we may have entirely different expectations. To me "If any table MOVES in the wrong direction ..." means an error is NOT reported if there is NO table movement - e.g., NO error is reported if the tests reveal EQUAL currents. I believe you really intended "If any table verification fails ...". I would prefer that the IBIS_CHK parser not stop, but continue to check the file for all errors (including other occurances of this error). So I would delete the "Note" entirely. Bob Ross, Interconnectix, Inc. From bob@icx.com Sat Apr 9 18:27:19 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26923; Sat, 9 Apr 94 18:27:19 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA01923 for ; Sat, 9 Apr 94 21:17:34 -0400 Date: Sat, 9 Apr 94 18:13:03 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA14937; Sat, 9 Apr 94 18:13:03 PDT Message-Id: <9404100113.AA14937@icx.com> To: ibis@vhdl.org Subject: EGG2 COMMENTS To Stephen Peters and IBIS Committee: Stephen, I am pleased to see a start in describing in more detail the time domain characteristics of the buffer. Since the status of EGG2 is in the prehatch stage, my comments relate to preferences as to what should be included. My overall position is that the response data should be presented from well defined test conditions without any further processing. As a reasonable approximation, that could define the response shape of the generator - as a tabular or piecewise representation. The simulator vendors may choose to do further processing and reformatting of the data such as into %voltage vs %time tables in a manner consistent with their data structures and internal algorithms. This transformation would cover the edge rate control buffer response which uses phased turn on of multiple transistors that you described. Furthermore, the simulator vendors may choose to convert this data through "optimization" or other processes such that a MODIFIED table reproduces the original, specified data when All elements of the simulator specific internal model and high-to-low and low-to-high transition algorithms are considered. This could provide more accurate models for other types of devices as well. Alternatively, the simulator company may choose to use this data as the basis for deriving the dV/dt_r and dV/dt_f ramp rates that best produce and match the specified response, rather than just base them on 20-80% points. Thus a tabular representation of the time response is valuable to those vendors which do not have full support of V-T tables. Fixed ramps may be fully adequate for the types of analysis done by that simulator. So, the emphasis if this comment is that if V-T tables are given, they come directly from extractions and be formatted in Voltage vs Time Tables. Bob Ross, Interconnectix, Inc. From bward@sugar.NeoSoft.COM Sun Apr 10 19:59:56 1994 Return-Path: Received: from sugar.NeoSoft.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA08853; Sun, 10 Apr 94 19:59:56 PDT Received: by sugar.NeoSoft.COM id AA02138 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Sun, 10 Apr 1994 21:57:05 -0500 Message-Id: <199404110257.AA02138@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: BOF at DAC update Date: Sun, 10 Apr 94 21:56:43 CDT Hi, Ibis-folk- Well we did it! We have the required ten people to get a room assigned to us for an official BOF session at DAC. I will pass the list of ten to the powers that be within DAC ( and any more that come in to me as well ) so that you do not have to make a special effort to register at the information booth for the BOF session, as I understand it. We will still have a poster advertising it, and ask that anyone who is interested sign up there. Thanks for putting all the names on the list so we could have a real live session. Hope to see all of you there! Bob bward@neosoft.com or bward@dadhb1.ti.com From jonp@qdt.com Mon Apr 11 09:49:21 1994 Return-Path: Received: from relay2.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17374; Mon, 11 Apr 94 09:49:21 PDT Received: from uucp2.uu.net by relay2.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwlep10115; Mon, 11 Apr 94 12:47:03 -0400 Received: from qdt.UUCP by uucp2.uu.net with UUCP/RMAIL ; Mon, 11 Apr 1994 12:47:05 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00544; Mon, 11 Apr 94 09:40:16 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA00690; Mon, 11 Apr 94 09:40:14 PDT Date: Mon, 11 Apr 94 09:40:14 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404111640.AA00690@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA10590; Mon, 11 Apr 94 09:40:17 PDT To: ibis@vhdl.org Subject: EGG2 COMMENTS I really like Bob Ross' idea of being able to determine our own rise time etc. from a picture of the AC waveforms in specified test conditions. jonp From bward@sugar.NeoSoft.COM Mon Apr 11 11:18:42 1994 Return-Path: Received: from sugar.NeoSoft.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18213; Mon, 11 Apr 94 11:18:42 PDT Received: by sugar.NeoSoft.COM id AA03716 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Mon, 11 Apr 1994 13:16:06 -0500 Message-Id: <199404111816.AA03716@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: EGG2 comments cnt'd Date: Mon, 11 Apr 94 13:16:01 CDT Hi, ibis-folk Actually the more I think about it the more I think the proposed method will solve most of the feedback slew rate controlled devices we wrestled with at the last summit. I want to review the Egg in more detail, but so far I am all for it! Bob Ward bward@neosoft.com or bward@dadhb1.ti.com From Derrick_Duehren@ccm2.jf.intel.com Tue Apr 12 15:23:39 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01532; Tue, 12 Apr 94 15:23:39 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pqqpi-000MNeC; Tue, 12 Apr 94 15:21 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Tue, 12 Apr 94 15:21:25 PST Date: Tue, 12 Apr 94 15:21:25 PST From: Derrick Duehren Message-Id: <940412152125_2@ccm.hf.intel.com> To: IBIS@vhdl.org Subject: IBIS 4/15/94 Meeting Agenda Text item: Text_1 IBIS Open Forum Meeting Agenda for 4/15/94 Bridge: Res: (415) 904-8944 721615 All meetings are 8:00 AM to 10:00 AM PST (15:00 to 17:00 UTC). When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. 8:00 Check-in Intros of new IBIS participants Hobbs Review of previous meeting's minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All New models available All IBIS 2.0 Ratification/DAC Hobbs, Ward - Rev 2.0 Ratification Summit (6/9) - Birds of a Feather session (6/8) IBIS Cookbook Hobbs 8:20 BIRD 8, Spec. of V/I data monotonicity Crisafulli BIRD 9, Other model types Ross BIRD 10, Coupling effects in package models Bracken 9:00 BIRD 11, Sign of current checking Hobbs, All Egg 2, Variable ramp Peters BIRD 2, VIH, VIL Thresholds for Inputs Powell Simulation temperatures (new BIRD?) Warriner Ramp measurement Reid, Ross, et. al. 9:55 Wrap-up, Next Meeting Plans Hobbs NOTE: From this point on, we propose tabling until after 2.0: Formal BNF notation (BIRD?) Reed, Harr High freq. and EMI Goyal, et. al. Phased turn-on/off of multiple devices Powell From Derrick_Duehren@ccm2.jf.intel.com Wed Apr 13 10:24:02 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA10777; Wed, 13 Apr 94 10:24:02 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pr8dC-000MNjC; Wed, 13 Apr 94 10:21 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Wed, 13 Apr 94 10:21:42 PST Date: Wed, 13 Apr 94 10:21:42 PST From: Derrick Duehren Message-Id: <940413102142_1@ccm.hf.intel.com> To: IBIS@vhdl.org Subject: IBIS 4/15/94 Agenda Text item: Text_1 This is a repeat. I'm not sure that my original posting of this agenda made it out. - Derrick IBIS Open Forum Meeting Agenda for 4/15/94 Bridge: Res: (415) 904-8944 721615 All meetings are 8:00 AM to 10:00 AM PST (15:00 to 17:00 UTC). When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. 8:00 Check-in Intros of new IBIS participants Hobbs Review of previous meeting's minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All New models available All IBIS 2.0 Ratification/DAC Hobbs, Ward - Rev 2.0 Ratification Summit (6/9) - Birds of a Feather session (6/8) IBIS Cookbook Hobbs 8:20 BIRD 8, Spec. of V/I data monotonicity Crisafulli BIRD 9, Other model types Ross BIRD 10, Coupling effects in package models Bracken 9:00 BIRD 11, Sign of current checking Hobbs, All Egg 2, Variable ramp Peters BIRD 2, VIH, VIL Thresholds for Inputs Powell Simulation temperatures (new BIRD?) Warriner Ramp measurement Reid, Ross, et. al. 9:55 Wrap-up, Next Meeting Plans Hobbs NOTE: From this point on, we propose tabling until after 2.0: Formal BNF notation (BIRD?) Reed, Harr High freq. and EMI Goyal, et. al. Phased turn-on/off of multiple devices Powell From Will_Hobbs@ccm2.jf.intel.com Wed Apr 13 20:31:06 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA14551; Wed, 13 Apr 94 20:31:06 PDT Received: from ccm.jf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0prI6h-000MNeC; Wed, 13 Apr 94 20:28 PDT Received: by ccm.jf.intel.com (ccmgate 3.0) Wed, 13 Apr 94 20:28:47 PST Date: Wed, 13 Apr 94 20:28:47 PST From: Will Hobbs Message-Id: <940413202847_2@ccm.jf.intel.com> To: Derrick_Duehren@ccm2.jf.intel.com, ibis@vhdl.org Subject: IBIS Agenda Returned mail Text item: Text Item Folks, I hope this is getting to you. If it is triplicated, we apologize, but as you see from the dialog below, we're not sure if this is getting out. I hope to see (hear) you on Friday. Will Will, I've sent out the IBIS agenda twice and have not received a reflection of it. Have you received it? If not, please try posting it yourself. Thanks. - Derrick This is a repeat. I'm not sure that my original posting of this agenda made it out. - Derrick IBIS Open Forum Meeting Agenda for 4/15/94 Bridge: Res: (415) 904-8944 721615 All meetings are 8:00 AM to 10:00 AM PST (15:00 to 17:00 UTC). When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. 8:00 Check-in Intros of new IBIS participants Hobbs Review of previous meeting's minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All New models available All IBIS 2.0 Ratification/DAC Hobbs, Ward - Rev 2.0 Ratification Summit (6/9) - Birds of a Feather session (6/8) IBIS Cookbook Hobbs 8:20 BIRD 8, Spec. of V/I data monotonicity Crisafulli BIRD 9, Other model types Ross BIRD 10, Coupling effects in package models Bracken 9:00 BIRD 11, Sign of current checking Hobbs, All Egg 2, Variable ramp Peters BIRD 2, VIH, VIL Thresholds for Inputs Powell Simulation temperatures (new BIRD?) Warriner Ramp measurement Reid, Ross, et. al. 9:55 Wrap-up, Next Meeting Plans Hobbs NOTE: From this point on, we propose tabling until after 2.0: Formal BNF notation (BIRD?) Reed, Harr High freq. and EMI Goyal, et. al. Phased turn-on/off of multiple devices Powell From jonp@qdt.com Fri Apr 15 14:51:38 1994 Return-Path: Received: from relay2.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06148; Fri, 15 Apr 94 14:51:38 PDT Received: from uucp2.uu.net by relay2.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwlud13994; Fri, 15 Apr 94 17:48:48 -0400 Received: from qdt.UUCP by uucp2.uu.net with UUCP/RMAIL ; Fri, 15 Apr 1994 17:48:50 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00790; Fri, 15 Apr 94 14:04:11 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA16649; Fri, 15 Apr 94 14:03:28 PDT Date: Fri, 15 Apr 94 14:03:28 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404152103.AA16649@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA13944; Fri, 15 Apr 94 14:03:32 PDT To: IBIS@vhdl.org Subject: Non-monotonic Pulldown curves Hey guys, Here is my report on non-montonic effects in CMOS pulldown curves. I include the postscript file as it has to many curves for Asciization (a least by me). Please feel free to let me know your feelings, especially if you have counter examples/data. If you need me to fax you a hard copy, please let me know. jonp@qdt.com %!PS-Adobe-3.0 %%BoundingBox: (atend) %%Pages: (atend) %%PageOrder: (atend) %%DocumentFonts: (atend) %%Creator: Frame 4.0 %%DocumentData: Clean7Bit %%EndComments %%BeginProlog % % Frame ps_prolog 4.0, for use with Frame 4.0 products % This ps_prolog file is Copyright (c) 1986-1993 Frame Technology % Corporation. All rights reserved. This ps_prolog file may be % freely copied and distributed in conjunction with documents created % using FrameMaker, FrameBuilder and FrameViewer as long as this % copyright notice is preserved. % % Frame products normally print colors as their true color on a color printer % or as shades of gray, based on luminance, on a black-and white printer. The % following flag, if set to True, forces all non-white colors to print as pure % black. This has no effect on bitmap images. /FMPrintAllColorsAsBlack false def % % Frame products can either set their own line screens or use a printer's % default settings. Three flags below control this separately for no % separations, spot separations and process separations. If a flag % is true, then the default printer settings will not be changed. If it is % false, Frame products will use their own settings from a table based on % the printer's resolution. /FMUseDefaultNoSeparationScreen true def /FMUseDefaultSpotSeparationScreen true def /FMUseDefaultProcessSeparationScreen false def % % For any given PostScript printer resolution, Frame products have two sets of % screen angles and frequencies for printing process separations, which are % recomended by Adobe. The following variable chooses the higher frequencies % when set to true or the lower frequencies when set to false. This is only % effective if the appropriate FMUseDefault...SeparationScreen flag is false. /FMUseHighFrequencyScreens true def % % PostScript Level 2 printers contain an "Accurate Screens" feature which can % improve process separation rendering at the expense of compute time. This % flag is ignored by PostScript Level 1 printers. /FMUseAcccurateScreens true def % % The following PostScript procedure defines the spot function that Frame % products will use for process separations. You may un-comment-out one of % the alternative functions below, or use your own. % % Dot function /FMSpotFunction {abs exch abs 2 copy add 1 gt {1 sub dup mul exch 1 sub dup mul add 1 sub } {dup mul exch dup mul add 1 exch sub }ifelse } def % % Line function % /FMSpotFunction { pop } def % % Elipse function % /FMSpotFunction { dup 5 mul 8 div mul exch dup mul exch add % sqrt 1 exch sub } def % % /FMversion (4.0) def /FMLevel1 /languagelevel where {pop languagelevel} {1} ifelse 2 lt def /FMPColor FMLevel1 { false /colorimage where {pop pop true} if } { true } ifelse def /FrameDict 400 dict def systemdict /errordict known not {/errordict 10 dict def errordict /rangecheck {stop} put} if % The readline in PS 23.0 doesn't recognize cr's as nl's on AppleTalk FrameDict /tmprangecheck errordict /rangecheck get put errordict /rangecheck {FrameDict /bug true put} put FrameDict /bug false put mark % Some PS machines read past the CR, so keep the following 3 lines together! currentfile 5 string readline 00 0000000000 cleartomark errordict /rangecheck FrameDict /tmprangecheck get put FrameDict /bug get { /readline { /gstring exch def /gfile exch def /gindex 0 def { gfile read pop dup 10 eq {exit} if dup 13 eq {exit} if gstring exch gindex exch put /gindex gindex 1 add def } loop pop gstring 0 gindex getinterval true } bind def } if /FMshowpage /showpage load def /FMquit /quit load def /FMFAILURE { dup = flush FMshowpage /Helvetica findfont 12 scalefont setfont 72 200 moveto show FMshowpage FMquit } def /FMVERSION { FMversion ne { (Frame product version does not match ps_prolog!) FMFAILURE } if } def /FMBADEPSF { (PostScript Lang. Ref. Man., 2nd Ed., H.2.4 says EPS must not call X ) dup dup (X) search pop exch pop exch pop length 4 -1 roll putinterval FMFAILURE } def /FMLOCAL { FrameDict begin 0 def end } def /concatprocs { /proc2 exch cvlit def/proc1 exch cvlit def/newproc proc1 length proc2 length add array def newproc 0 proc1 putinterval newproc proc1 length proc2 putinterval newproc cvx }def FrameDict begin /FMnone 0 def /FMcyan 1 def /FMmagenta 2 def /FMyellow 3 def /FMblack 4 def /FMcustom 5 def /FrameNegative false def /FrameSepIs FMnone def /FrameSepBlack 0 def /FrameSepYellow 0 def /FrameSepMagenta 0 def /FrameSepCyan 0 def /FrameSepRed 1 def /FrameSepGreen 1 def /FrameSepBlue 1 def /FrameCurGray 1 def /FrameCurPat null def /FrameCurColors [ 0 0 0 1 0 0 0 ] def /FrameColorEpsilon .001 def /eqepsilon { sub dup 0 lt {neg} if FrameColorEpsilon le } bind def /FrameCmpColorsCMYK { 2 copy 0 get exch 0 get eqepsilon { 2 copy 1 get exch 1 get eqepsilon { 2 copy 2 get exch 2 get eqepsilon { 3 get exch 3 get eqepsilon } {pop pop false} ifelse }{pop pop false} ifelse } {pop pop false} ifelse } bind def /FrameCmpColorsRGB { 2 copy 4 get exch 0 get eqepsilon { 2 copy 5 get exch 1 get eqepsilon { 6 get exch 2 get eqepsilon }{pop pop false} ifelse } {pop pop false} ifelse } bind def /RGBtoCMYK { 1 exch sub 3 1 roll 1 exch sub 3 1 roll 1 exch sub 3 1 roll 3 copy 2 copy le { pop } { exch pop } ifelse 2 copy le { pop } { exch pop } ifelse dup dup dup 6 1 roll 4 1 roll 7 1 roll sub 6 1 roll sub 5 1 roll sub 4 1 roll } bind def /CMYKtoRGB { dup dup 4 -1 roll add 5 1 roll 3 -1 roll add 4 1 roll add 1 exch sub dup 0 lt {pop 0} if 3 1 roll 1 exch sub dup 0 lt {pop 0} if exch 1 exch sub dup 0 lt {pop 0} if exch } bind def /FrameSepInit { 1.0 RealSetgray } bind def /FrameSetSepColor { /FrameSepBlue exch def /FrameSepGreen exch def /FrameSepRed exch def /FrameSepBlack exch def /FrameSepYellow exch def /FrameSepMagenta exch def /FrameSepCyan exch def /FrameSepIs FMcustom def setCurrentScreen } bind def /FrameSetCyan { /FrameSepBlue 1.0 def /FrameSepGreen 1.0 def /FrameSepRed 0.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 1.0 def /FrameSepIs FMcyan def setCurrentScreen } bind def /FrameSetMagenta { /FrameSepBlue 1.0 def /FrameSepGreen 0.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 1.0 def /FrameSepCyan 0.0 def /FrameSepIs FMmagenta def setCurrentScreen } bind def /FrameSetYellow { /FrameSepBlue 0.0 def /FrameSepGreen 1.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 1.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMyellow def setCurrentScreen } bind def /FrameSetBlack { /FrameSepBlue 0.0 def /FrameSepGreen 0.0 def /FrameSepRed 0.0 def /FrameSepBlack 1.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMblack def setCurrentScreen } bind def /FrameNoSep { /FrameSepIs FMnone def setCurrentScreen } bind def /FrameSetSepColors { FrameDict begin [ exch 1 add 1 roll ] /FrameSepColors exch def end } bind def /FrameColorInSepListCMYK { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsCMYK { pop true exit } if } forall dup true ne {pop false} if } bind def /FrameColorInSepListRGB { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsRGB { pop true exit } if } forall dup true ne {pop false} if } bind def /RealSetgray /setgray load def /RealSetrgbcolor /setrgbcolor load def /RealSethsbcolor /sethsbcolor load def end /setgray { FrameDict begin FrameSepIs FMnone eq { RealSetgray } { FrameSepIs FMblack eq { RealSetgray } { FrameSepIs FMcustom eq FrameSepRed 0 eq and FrameSepGreen 0 eq and FrameSepBlue 0 eq and { RealSetgray } { 1 RealSetgray pop } ifelse } ifelse } ifelse end } bind def /setrgbcolor { FrameDict begin FrameSepIs FMnone eq { RealSetrgbcolor } { 3 copy [ 4 1 roll ] FrameColorInSepListRGB { FrameSepBlue eq exch FrameSepGreen eq and exch FrameSepRed eq and { 0 } { 1 } ifelse } { FMPColor { RealSetrgbcolor currentcmykcolor } { RGBtoCMYK } ifelse FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind def /sethsbcolor { FrameDict begin FrameSepIs FMnone eq { RealSethsbcolor } { RealSethsbcolor currentrgbcolor setrgbcolor } ifelse end } bind def FrameDict begin /setcmykcolor where { pop /RealSetcmykcolor /setcmykcolor load def } { /RealSetcmykcolor { 4 1 roll 3 { 3 index add 0 max 1 min 1 exch sub 3 1 roll} repeat setrgbcolor pop } bind def } ifelse userdict /setcmykcolor { FrameDict begin FrameSepIs FMnone eq { RealSetcmykcolor } { 4 copy [ 5 1 roll ] FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and { 0 } { 1 } ifelse } { FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind put FMLevel1 not { /patProcDict 5 dict dup begin <0f1e3c78f0e1c387> { 3 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def <8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -1 -1 moveto 9 9 lineto stroke } bind def <03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def end def /patDict 15 dict dup begin /PatternType 1 def /PaintType 2 def /TilingType 3 def /BBox [ 0 0 8 8 ] def /XStep 8 def /YStep 8 def /PaintProc { begin patProcDict bstring known { patProcDict bstring get exec } { 8 8 true [1 0 0 -1 0 8] bstring imagemask } ifelse end } bind def end def } if /combineColor { FrameSepIs FMnone eq { graymode FMLevel1 or not { [/Pattern [/DeviceCMYK]] setcolorspace FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor } { FrameCurColors 3 get 1.0 ge { FrameCurGray RealSetgray } { FMPColor graymode and { 0 1 3 { FrameCurColors exch get 1 FrameCurGray sub mul } for RealSetcmykcolor } { 4 1 6 { FrameCurColors exch get graymode { 1 exch sub 1 FrameCurGray sub mul 1 exch sub } { 1.0 lt {FrameCurGray} {1} ifelse } ifelse } for RealSetrgbcolor } ifelse } ifelse } ifelse } { FrameCurColors 0 4 getinterval aload FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and FrameSepIs FMcustom eq and { FrameCurGray } { 1 } ifelse } { FrameSepIs FMblack eq {FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse graymode FMLevel1 or not { [/Pattern [/DeviceGray]] setcolorspace FrameCurPat setcolor } { graymode not FMLevel1 and { dup 1 lt {pop FrameCurGray} if } if RealSetgray } ifelse } ifelse } bind def /savematrix { orgmatrix currentmatrix pop } bind def /restorematrix { orgmatrix setmatrix } bind def /dmatrix matrix def /dpi 72 0 dmatrix defaultmatrix dtransform dup mul exch dup mul add sqrt def /freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def /sangle 1 0 dmatrix defaultmatrix dtransform exch atan def /dpiranges [ 2540 2400 1693 1270 1200 635 600 0 ] def /CMLowFreqs [ 100.402 94.8683 89.2289 100.402 94.8683 66.9349 63.2456 47.4342 ] def /YLowFreqs [ 95.25 90.0 84.65 95.25 90.0 70.5556 66.6667 50.0 ] def /KLowFreqs [ 89.8026 84.8528 79.8088 89.8026 84.8528 74.8355 70.7107 53.033 ] def /CLowAngles [ 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 ] def /MLowAngles [ 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 ] def /YLowTDot [ true true false true true false false false ] def /CMHighFreqs [ 133.87 126.491 133.843 108.503 102.523 100.402 94.8683 63.2456 ] def /YHighFreqs [ 127.0 120.0 126.975 115.455 109.091 95.25 90.0 60.0 ] def /KHighFreqs [ 119.737 113.137 119.713 128.289 121.218 89.8026 84.8528 63.6395 ] def /CHighAngles [ 71.5651 71.5651 71.5651 70.0169 70.0169 71.5651 71.5651 71.5651 ] def /MHighAngles [ 18.4349 18.4349 18.4349 19.9831 19.9831 18.4349 18.4349 18.4349 ] def /YHighTDot [ false false true false false true true false ] def /PatFreq [ 10.5833 10.0 9.4055 10.5833 10.0 10.5833 10.0 9.375 ] def /screenIndex { 0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for } bind def /getCyanScreen { FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getMagentaScreen { FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getYellowScreen { FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse screenIndex dup 3 1 roll get 3 1 roll get { 3 div {2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat FMSpotFunction } } {/FMSpotFunction load } ifelse 0.0 exch } bind def /getBlackScreen { FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse screenIndex get 45.0 /FMSpotFunction load } bind def /getSpotScreen { getBlackScreen } bind def /getCompositeScreen { getBlackScreen } bind def /FMSetScreen FMLevel1 { /setscreen load }{ { 8 dict begin /HalftoneType 1 def /SpotFunction exch def /Angle exch def /Frequency exch def /AccurateScreens FMUseAcccurateScreens def currentdict end sethalftone } bind } ifelse def /setDefaultScreen { FMPColor { orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer } { orgxfer cvx settransfer } ifelse orgfreq organgle orgproc cvx setscreen } bind def /setCurrentScreen { FrameSepIs FMnone eq { FMUseDefaultNoSeparationScreen { setDefaultScreen } { getCompositeScreen FMSetScreen } ifelse } { FrameSepIs FMcustom eq { FMUseDefaultSpotSeparationScreen { setDefaultScreen } { getSpotScreen FMSetScreen } ifelse } { FMUseDefaultProcessSeparationScreen { setDefaultScreen } { FrameSepIs FMcyan eq { getCyanScreen FMSetScreen } { FrameSepIs FMmagenta eq { getMagentaScreen FMSetScreen } { FrameSepIs FMyellow eq { getYellowScreen FMSetScreen } { getBlackScreen FMSetScreen } ifelse } ifelse } ifelse } ifelse } ifelse } ifelse } bind def end /gstring FMLOCAL /gfile FMLOCAL /gindex FMLOCAL /orgrxfer FMLOCAL /orggxfer FMLOCAL /orgbxfer FMLOCAL /orgxfer FMLOCAL /orgproc FMLOCAL /orgrproc FMLOCAL /orggproc FMLOCAL /orgbproc FMLOCAL /organgle FMLOCAL /orgrangle FMLOCAL /orggangle FMLOCAL /orgbangle FMLOCAL /orgfreq FMLOCAL /orgrfreq FMLOCAL /orggfreq FMLOCAL /orgbfreq FMLOCAL /yscale FMLOCAL /xscale FMLOCAL /edown FMLOCAL /manualfeed FMLOCAL /paperheight FMLOCAL /paperwidth FMLOCAL /FMDOCUMENT { array /FMfonts exch def /#copies exch def FrameDict begin 0 ne /manualfeed exch def /paperheight exch def /paperwidth exch def 0 ne /FrameNegative exch def 0 ne /edown exch def /yscale exch def /xscale exch def FMLevel1 { manualfeed {setmanualfeed} if /FMdicttop countdictstack 1 add def /FMoptop count def setpapername manualfeed {true} {papersize} ifelse {manualpapersize} {false} ifelse {desperatepapersize} {false} ifelse { (Can't select requested paper size for Frame print job!) FMFAILURE } if count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for } {{1 dict dup /PageSize [paperwidth paperheight]put setpagedevice}stopped { (Can't select requested paper size for Frame print job!) FMFAILURE } if {1 dict dup /ManualFeed manualfeed put setpagedevice } stopped pop } ifelse FMPColor { currentcolorscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def cvlit /orgbproc exch def /orgbangle exch def /orgbfreq exch def cvlit /orggproc exch def /orggangle exch def /orggfreq exch def cvlit /orgrproc exch def /orgrangle exch def /orgrfreq exch def currentcolortransfer FrameNegative { 1 1 4 { pop { 1 exch sub } concatprocs 4 1 roll } for 4 copy setcolortransfer } if cvlit /orgxfer exch def cvlit /orgbxfer exch def cvlit /orggxfer exch def cvlit /orgrxfer exch def } { currentscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def currenttransfer FrameNegative { { 1 exch sub } concatprocs dup settransfer } if cvlit /orgxfer exch def } ifelse end } def /pagesave FMLOCAL /orgmatrix FMLOCAL /landscape FMLOCAL /pwid FMLOCAL /FMBEGINPAGE { FrameDict begin /pagesave save def 3.86 setmiterlimit /landscape exch 0 ne def landscape { 90 rotate 0 exch dup /pwid exch def neg translate pop }{ pop /pwid exch def } ifelse edown { [-1 0 0 1 pwid 0] concat } if 0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto 0 paperheight lineto 0 0 lineto 1 setgray fill xscale yscale scale /orgmatrix matrix def gsave } def /FMENDPAGE { grestore pagesave restore end showpage } def /FMFONTDEFINE { FrameDict begin findfont ReEncode 1 index exch definefont FMfonts 3 1 roll put end } def /FMFILLS { FrameDict begin dup array /fillvals exch def dict /patCache exch def end } def /FMFILL { FrameDict begin fillvals 3 1 roll put end } def /FMNORMALIZEGRAPHICS { newpath 0.0 0.0 moveto 1 setlinewidth 0 setlinecap 0 0 0 sethsbcolor 0 setgray } bind def /fx FMLOCAL /fy FMLOCAL /fh FMLOCAL /fw FMLOCAL /llx FMLOCAL /lly FMLOCAL /urx FMLOCAL /ury FMLOCAL /FMBEGINEPSF { end /FMEPSF save def /showpage {} def % See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714. % "...the following operators MUST NOT be used in an EPS file:" (emphasis ours) /banddevice {(banddevice) FMBADEPSF} def /clear {(clear) FMBADEPSF} def /cleardictstack {(cleardictstack) FMBADEPSF} def /copypage {(copypage) FMBADEPSF} def /erasepage {(erasepage) FMBADEPSF} def /exitserver {(exitserver) FMBADEPSF} def /framedevice {(framedevice) FMBADEPSF} def /grestoreall {(grestoreall) FMBADEPSF} def /initclip {(initclip) FMBADEPSF} def /initgraphics {(initgraphics) FMBADEPSF} def /initmatrix {(initmatrix) FMBADEPSF} def /quit {(quit) FMBADEPSF} def /renderbands {(renderbands) FMBADEPSF} def /setglobal {(setglobal) FMBADEPSF} def /setpagedevice {(setpagedevice) FMBADEPSF} def /setshared {(setshared) FMBADEPSF} def /startjob {(startjob) FMBADEPSF} def /lettertray {(lettertray) FMBADEPSF} def /letter {(letter) FMBADEPSF} def /lettersmall {(lettersmall) FMBADEPSF} def /11x17tray {(11x17tray) FMBADEPSF} def /11x17 {(11x17) FMBADEPSF} def /ledgertray {(ledgertray) FMBADEPSF} def /ledger {(ledger) FMBADEPSF} def /legaltray {(legaltray) FMBADEPSF} def /legal {(legal) FMBADEPSF} def /statementtray {(statementtray) FMBADEPSF} def /statement {(statement) FMBADEPSF} def /executivetray {(executivetray) FMBADEPSF} def /executive {(executive) FMBADEPSF} def /a3tray {(a3tray) FMBADEPSF} def /a3 {(a3) FMBADEPSF} def /a4tray {(a4tray) FMBADEPSF} def /a4 {(a4) FMBADEPSF} def /a4small {(a4small) FMBADEPSF} def /b4tray {(b4tray) FMBADEPSF} def /b4 {(b4) FMBADEPSF} def /b5tray {(b5tray) FMBADEPSF} def /b5 {(b5) FMBADEPSF} def FMNORMALIZEGRAPHICS [/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall fx fw 2 div add fy fh 2 div add translate rotate fw 2 div neg fh 2 div neg translate fw urx llx sub div fh ury lly sub div scale llx neg lly neg translate /FMdicttop countdictstack 1 add def /FMoptop count def } bind def /FMENDEPSF { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMEPSF restore FrameDict begin } bind def FrameDict begin /setmanualfeed { %%BeginFeature *ManualFeed True statusdict /manualfeed true put %%EndFeature } bind def /max {2 copy lt {exch} if pop} bind def /min {2 copy gt {exch} if pop} bind def /inch {72 mul} def /pagedimen { paperheight sub abs 16 lt exch paperwidth sub abs 16 lt and {/papername exch def} {pop} ifelse } bind def /papersizedict FMLOCAL /setpapername { /papersizedict 14 dict def papersizedict begin /papername /unknown def /Letter 8.5 inch 11.0 inch pagedimen /LetterSmall 7.68 inch 10.16 inch pagedimen /Tabloid 11.0 inch 17.0 inch pagedimen /Ledger 17.0 inch 11.0 inch pagedimen /Legal 8.5 inch 14.0 inch pagedimen /Statement 5.5 inch 8.5 inch pagedimen /Executive 7.5 inch 10.0 inch pagedimen /A3 11.69 inch 16.5 inch pagedimen /A4 8.26 inch 11.69 inch pagedimen /A4Small 7.47 inch 10.85 inch pagedimen /B4 10.125 inch 14.33 inch pagedimen /B5 7.16 inch 10.125 inch pagedimen end } bind def /papersize { papersizedict begin /Letter {lettertray letter} def /LetterSmall {lettertray lettersmall} def /Tabloid {11x17tray 11x17} def /Ledger {ledgertray ledger} def /Legal {legaltray legal} def /Statement {statementtray statement} def /Executive {executivetray executive} def /A3 {a3tray a3} def /A4 {a4tray a4} def /A4Small {a4tray a4small} def /B4 {b4tray b4} def /B5 {b5tray b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end statusdict begin stopped end } bind def /manualpapersize { papersizedict begin /Letter {letter} def /LetterSmall {lettersmall} def /Tabloid {11x17} def /Ledger {ledger} def /Legal {legal} def /Statement {statement} def /Executive {executive} def /A3 {a3} def /A4 {a4} def /A4Small {a4small} def /B4 {b4} def /B5 {b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end stopped } bind def /desperatepapersize { statusdict /setpageparams known { paperwidth paperheight 0 1 statusdict begin {setpageparams} stopped end } {true} ifelse } bind def /DiacriticEncoding [ /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /space /exclam /quotedbl /numbersign /dollar /percent /ampersand /quotesingle /parenleft /parenright /asterisk /plus /comma /hyphen /period /slash /zero /one /two /three /four /five /six /seven /eight /nine /colon /semicolon /less /equal /greater /question /at /A /B /C /D /E /F /G /H /I /J /K /L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z /bracketleft /backslash /bracketright /asciicircum /underscore /grave /a /b /c /d /e /f /g /h /i /j /k /l /m /n /o /p /q /r /s /t /u /v /w /x /y /z /braceleft /bar /braceright /asciitilde /.notdef /Adieresis /Aring /Ccedilla /Eacute /Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis /atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis /iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve /ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex /udieresis /dagger /.notdef /cent /sterling /section /bullet /paragraph /germandbls /registered /copyright /trademark /acute /dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef /yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /ordfeminine /ordmasculine /.notdef /ae /oslash /questiondown /exclamdown /logicalnot /.notdef /florin /.notdef /.notdef /guillemotleft /guillemotright /ellipsis /.notdef /Agrave /Atilde /Otilde /OE /oe /endash /emdash /quotedblleft /quotedblright /quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis /fraction /currency /guilsinglleft /guilsinglright /fi /fl /daggerdbl /periodcentered /quotesinglbase /quotedblbase /perthousand /Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute /Icircumflex /Idieresis /Igrave /Oacute /Ocircumflex /.notdef /Ograve /Uacute /Ucircumflex /Ugrave /dotlessi /circumflex /tilde /macron /breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron ] def /ReEncode { dup length dict begin { 1 index /FID ne {def} {pop pop} ifelse } forall 0 eq {/Encoding DiacriticEncoding def} if currentdict end } bind def FMPColor { /BEGINBITMAPCOLOR { BITMAPCOLOR} def /BEGINBITMAPCOLORc { BITMAPCOLORc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUECOLOR } def /BEGINBITMAPTRUECOLORc { BITMAPTRUECOLORc } def } { /BEGINBITMAPCOLOR { BITMAPGRAY} def /BEGINBITMAPCOLORc { BITMAPGRAYc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUEGRAY } def /BEGINBITMAPTRUECOLORc { BITMAPTRUEGRAYc } def } ifelse /K { FMPrintAllColorsAsBlack { dup 1 eq 2 index 1 eq and 3 index 1 eq and not {7 {pop} repeat 0 0 0 1 0 0 0} if } if FrameCurColors astore pop combineColor } bind def /graymode true def /bwidth FMLOCAL /bpside FMLOCAL /bstring FMLOCAL /onbits FMLOCAL /offbits FMLOCAL /xindex FMLOCAL /yindex FMLOCAL /x FMLOCAL /y FMLOCAL /setPatternMode { FMLevel1 { /bwidth exch def /bpside exch def /bstring exch def /onbits 0 def /offbits 0 def freq sangle landscape {90 add} if {/y exch def /x exch def /xindex x 1 add 2 div bpside mul cvi def /yindex y 1 add 2 div bpside mul cvi def bstring yindex bwidth mul xindex 8 idiv add get 1 7 xindex 8 mod sub bitshift and 0 ne FrameNegative {not} if {/onbits onbits 1 add def 1} {/offbits offbits 1 add def 0} ifelse } setscreen offbits offbits onbits add div FrameNegative {1.0 exch sub} if /FrameCurGray exch def } { pop pop dup patCache exch known { patCache exch get } { dup patDict /bstring 3 -1 roll put patDict 9 PatFreq screenIndex get div dup matrix scale makepattern dup patCache 4 -1 roll 3 -1 roll put } ifelse /FrameCurGray 0 def /FrameCurPat exch def } ifelse /graymode false def combineColor } bind def /setGrayScaleMode { graymode not { /graymode true def FMLevel1 { setCurrentScreen } if } if /FrameCurGray exch def combineColor } bind def /normalize { transform round exch round exch itransform } bind def /dnormalize { dtransform round exch round exch idtransform } bind def /lnormalize { 0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop } bind def /H { lnormalize setlinewidth } bind def /Z { setlinecap } bind def /PFill { graymode FMLevel1 or not { gsave 1 setgray eofill grestore } if } bind def /PStroke { graymode FMLevel1 or not { gsave 1 setgray stroke grestore } if stroke } bind def /fillvals FMLOCAL /X { fillvals exch get dup type /stringtype eq {8 1 setPatternMode} {setGrayScaleMode} ifelse } bind def /V { PFill gsave eofill grestore } bind def /Vclip { clip } bind def /Vstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /N { PStroke } bind def /Nclip { strokepath clip newpath } bind def /Nstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /M {newpath moveto} bind def /E {lineto} bind def /D {curveto} bind def /O {closepath} bind def /n FMLOCAL /L { /n exch def newpath normalize moveto 2 1 n {pop normalize lineto} for } bind def /Y { L closepath } bind def /x1 FMLOCAL /x2 FMLOCAL /y1 FMLOCAL /y2 FMLOCAL /R { /y2 exch def /x2 exch def /y1 exch def /x1 exch def x1 y1 x2 y1 x2 y2 x1 y2 4 Y } bind def /rad FMLOCAL /rarc {rad arcto } bind def /RR { /rad exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def mark newpath { x1 y1 rad add moveto x1 y2 x2 y2 rarc x2 y2 x2 y1 rarc x2 y1 x1 y1 rarc x1 y1 x1 y2 rarc closepath } stopped {x1 y1 x2 y2 R} if cleartomark } bind def /RRR { /rad exch def normalize /y4 exch def /x4 exch def normalize /y3 exch def /x3 exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def newpath normalize moveto mark { x2 y2 x3 y3 rarc x3 y3 x4 y4 rarc x4 y4 x1 y1 rarc x1 y1 x2 y2 rarc closepath } stopped {x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if cleartomark } bind def /C { grestore gsave R clip setCurrentScreen } bind def /CP { grestore gsave Y clip setCurrentScreen } bind def /FMpointsize FMLOCAL /F { FMfonts exch get FMpointsize scalefont setfont } bind def /Q { /FMpointsize exch def F } bind def /T { moveto show } bind def /RF { rotate 0 ne {-1 1 scale} if } bind def /TF { gsave moveto RF show grestore } bind def /P { moveto 0 32 3 2 roll widthshow } bind def /PF { gsave moveto RF 0 32 3 2 roll widthshow grestore } bind def /S { moveto 0 exch ashow } bind def /SF { gsave moveto RF 0 exch ashow grestore } bind def /B { moveto 0 32 4 2 roll 0 exch awidthshow } bind def /BF { gsave moveto RF 0 32 4 2 roll 0 exch awidthshow grestore } bind def /G { gsave newpath normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /Gstrk { savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /Gclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GG { gsave newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /GGclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GGstrk { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /A { gsave savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /Aclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /Astrk { Gstrk } bind def /AA { gsave savematrix newpath 3 index 2 div add exch 4 index 2 div sub exch normalize 3 index 2 div sub exch 4 index 2 div add exch translate rotate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /AAclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /AAstrk { GGstrk } bind def /x FMLOCAL /y FMLOCAL /w FMLOCAL /h FMLOCAL /xx FMLOCAL /yy FMLOCAL /ww FMLOCAL /hh FMLOCAL /FMsaveobject FMLOCAL /FMoptop FMLOCAL /FMdicttop FMLOCAL /BEGINPRINTCODE { /FMdicttop countdictstack 1 add def /FMoptop count 7 sub def /FMsaveobject save def userdict begin /showpage {} def FMNORMALIZEGRAPHICS 3 index neg 3 index neg translate } bind def /ENDPRINTCODE { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMsaveobject restore } bind def /gn { 0 { 46 mul cf read pop 32 sub dup 46 lt {exit} if 46 sub add } loop add } bind def /str FMLOCAL /cfs { /str sl string def 0 1 sl 1 sub {str exch val put} for str def } bind def /ic [ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 {0 hx} {1 hx} {2 hx} {3 hx} {4 hx} {5 hx} {6 hx} {7 hx} {8 hx} {9 hx} {10 hx} {11 hx} {12 hx} {13 hx} {14 hx} {15 hx} {16 hx} {17 hx} {18 hx} {19 hx} {gn hx} {0} {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {gn} {0 wh} {1 wh} {2 wh} {3 wh} {4 wh} {5 wh} {6 wh} {7 wh} {8 wh} {9 wh} {10 wh} {11 wh} {12 wh} {13 wh} {14 wh} {gn wh} {0 bl} {1 bl} {2 bl} {3 bl} {4 bl} {5 bl} {6 bl} {7 bl} {8 bl} {9 bl} {10 bl} {11 bl} {12 bl} {13 bl} {14 bl} {gn bl} {0 fl} {1 fl} {2 fl} {3 fl} {4 fl} {5 fl} {6 fl} {7 fl} {8 fl} {9 fl} {10 fl} {11 fl} {12 fl} {13 fl} {14 fl} {gn fl} ] def /sl FMLOCAL /val FMLOCAL /ws FMLOCAL /im FMLOCAL /bs FMLOCAL /cs FMLOCAL /len FMLOCAL /pos FMLOCAL /ms { /sl exch def /val 255 def /ws cfs /im cfs /val 0 def /bs cfs /cs cfs } bind def 400 ms /ip { is 0 cf cs readline pop { ic exch get exec add } forall pop } bind def /rip { bis ris copy pop is 0 cf cs readline pop { ic exch get exec add } forall pop pop ris gis copy pop dup is exch cf cs readline pop { ic exch get exec add } forall pop pop gis bis copy pop dup add is exch cf cs readline pop { ic exch get exec add } forall pop } bind def /wh { /len exch def /pos exch def ws 0 len getinterval im pos len getinterval copy pop pos len } bind def /bl { /len exch def /pos exch def bs 0 len getinterval im pos len getinterval copy pop pos len } bind def /s1 1 string def /fl { /len exch def /pos exch def /val cf s1 readhexstring pop 0 get def pos 1 pos len add 1 sub {im exch val put} for pos len } bind def /hx { 3 copy getinterval cf exch readhexstring pop pop } bind def /h FMLOCAL /w FMLOCAL /d FMLOCAL /lb FMLOCAL /bitmapsave FMLOCAL /is FMLOCAL /cf FMLOCAL /wbytes { dup dup 24 eq { pop pop 3 mul } { 8 eq {pop} {1 eq {7 add 8 idiv} {3 add 4 idiv} ifelse} ifelse } ifelse } bind def /BEGINBITMAPBWc { 1 {} COMMONBITMAPc } bind def /BEGINBITMAPGRAYc { 8 {} COMMONBITMAPc } bind def /BEGINBITMAP2BITc { 2 {} COMMONBITMAPc } bind def /COMMONBITMAPc { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def r /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h d [w 0 0 h neg 0 h] {ip} image bitmapsave restore grestore } bind def /BEGINBITMAPBW { 1 {} COMMONBITMAP } bind def /BEGINBITMAPGRAY { 8 {} COMMONBITMAP } bind def /BEGINBITMAP2BIT { 2 {} COMMONBITMAP } bind def /COMMONBITMAP { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def r /is w d wbytes string def /cf currentfile def w h d [w 0 0 h neg 0 h] {cf is readhexstring pop} image bitmapsave restore grestore } bind def /ngrayt 256 array def /nredt 256 array def /nbluet 256 array def /ngreent 256 array def /gryt FMLOCAL /blut FMLOCAL /grnt FMLOCAL /redt FMLOCAL /indx FMLOCAL /cynu FMLOCAL /magu FMLOCAL /yelu FMLOCAL /k FMLOCAL /u FMLOCAL FMLevel1 { /colorsetup { currentcolortransfer /gryt exch def /blut exch def /grnt exch def /redt exch def 0 1 255 { /indx exch def /cynu 1 red indx get 255 div sub def /magu 1 green indx get 255 div sub def /yelu 1 blue indx get 255 div sub def /k cynu magu min yelu min def /u k currentundercolorremoval exec def % /u 0 def nredt indx 1 0 cynu u sub max sub redt exec put ngreent indx 1 0 magu u sub max sub grnt exec put nbluet indx 1 0 yelu u sub max sub blut exec put ngrayt indx 1 k currentblackgeneration exec sub gryt exec put } for {255 mul cvi nredt exch get} {255 mul cvi ngreent exch get} {255 mul cvi nbluet exch get} {255 mul cvi ngrayt exch get} setcolortransfer {pop 0} setundercolorremoval {} setblackgeneration } bind def } { /colorSetup2 { [ /Indexed /DeviceRGB 255 {dup red exch get 255 div exch dup green exch get 255 div exch blue exch get 255 div} ] setcolorspace } bind def } ifelse /tran FMLOCAL /fakecolorsetup { /tran 256 string def 0 1 255 {/indx exch def tran indx red indx get 77 mul green indx get 151 mul blue indx get 28 mul add add 256 idiv put} for currenttransfer {255 mul cvi tran exch get 255.0 div} exch concatprocs settransfer } bind def /BITMAPCOLOR { /d 8 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def FMLevel1 { colorsetup /is w d wbytes string def /cf currentfile def w h d [w 0 0 h neg 0 h] {cf is readhexstring pop} {is} {is} true 3 colorimage } { colorSetup2 /is w d wbytes string def /cf currentfile def 7 dict dup begin /ImageType 1 def /Width w def /Height h def /ImageMatrix [w 0 0 h neg 0 h] def /DataSource {cf is readhexstring pop} bind def /BitsPerComponent d def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def /BITMAPCOLORc { /d 8 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def FMLevel1 { colorsetup /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h d [w 0 0 h neg 0 h] {ip} {is} {is} true 3 colorimage } { colorSetup2 /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def 7 dict dup begin /ImageType 1 def /Width w def /Height h def /ImageMatrix [w 0 0 h neg 0 h] def /DataSource {ip} bind def /BitsPerComponent d def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def /BITMAPTRUECOLORc { /d 24 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def /is im 0 lb getinterval def /ris im 0 w getinterval def /gis im w w getinterval def /bis im w 2 mul w getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {w rip pop ris} {gis} {bis} true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUECOLOR { gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def /is w string def /gis w string def /bis w string def /cf currentfile def w h 8 [w 0 0 h neg 0 h] { cf is readhexstring pop } { cf gis readhexstring pop } { cf bis readhexstring pop } true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUEGRAYc { /d 24 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def /is im 0 lb getinterval def /ris im 0 w getinterval def /gis im w w getinterval def /bis im w 2 mul w getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {w rip pop ris gis bis w gray} image bitmapsave restore grestore } bind def /ww FMLOCAL /r FMLOCAL /g FMLOCAL /b FMLOCAL /i FMLOCAL /gray { /ww exch def /b exch def /g exch def /r exch def 0 1 ww 1 sub { /i exch def r i get .299 mul g i get .587 mul b i get .114 mul add add r i 3 -1 roll floor cvi put } for r } bind def /BITMAPTRUEGRAY { gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def /is w string def /gis w string def /bis w string def /cf currentfile def w h 8 [w 0 0 h neg 0 h] { cf is readhexstring pop cf gis readhexstring pop cf bis readhexstring pop w gray} image bitmapsave restore grestore } bind def /BITMAPGRAY { 8 {fakecolorsetup} COMMONBITMAP } bind def /BITMAPGRAYc { 8 {fakecolorsetup} COMMONBITMAPc } bind def /ENDBITMAP { } bind def end /ALDsave FMLOCAL /ALDmatrix matrix def ALDmatrix currentmatrix pop /StartALD { /ALDsave save def savematrix ALDmatrix setmatrix } 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0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 329.94 360 T 3 9 Q (d) 334.39 355.8 T 2 6 Q (1) 339.23 353.25 T 0 0 612 792 C 348.23 349.75 363.52 370 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 349.23 360 T 3 9 Q (d) 353.68 355.8 T 2 6 Q (2) 358.52 353.25 T 0 0 612 792 C 374.51 348.75 389.8 369 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 375.51 359 T 3 9 Q (b) 379.96 354.8 T 2 6 Q (1) 384.8 352.25 T 0 0 612 792 C 393.8 349.75 409.1 370 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 394.8 360 T 3 9 Q (b) 399.25 355.8 T 2 6 Q (2) 404.09 353.25 T 0 0 612 792 C 482.75 349.75 498.04 370 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 484.25 360 T 3 9 Q (s) 488.7 355.8 T 2 6 Q (1) 492.54 353.25 T 0 0 612 792 C 208.6 303.75 223.89 324 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 210.1 314 T 3 9 Q (s) 214.55 309.8 T 2 6 Q (1) 218.39 307.25 T 0 0 612 792 C 429.62 249.75 444.92 270 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 430.62 260 T 3 9 Q (b) 435.08 255.8 T 2 6 Q (1) 439.92 253.25 T 0 0 612 792 C 457.68 249.75 472.98 270 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 3 12 Q 0 X 0 0 0 1 0 0 0 K (I) 458.69 260 T 3 9 Q (b) 463.14 255.8 T 2 6 Q (2) 467.98 253.25 T 0 0 612 792 C FMENDPAGE %%EndPage: "4" 4 %%Page: "5" 5 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] [ 0 0 0 0 1 1 1] [ 0 0 0 1 0 0 0] 9 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 72 748.77 540 768.57 R 7 X 0 0 0 1 0 0 0 K V 0 11.2 Q 0 X (METHOD 2) 72 755.2 T 72 18 540 54 R 7 X V 0 10 Q 0 X (Measuring Pulldown Currents in CMOS devices) 72 35.33 T (April 15, 1994 2:01 pm) 72 23.33 T 1 12 Q (5) 533.33 23.33 T 72.33 46 540 46 2 L 1 H 2 Z N 72 765.96 539.67 765.96 2 L N 72 751.89 540 751.89 2 L N 72 72 540 720 R 7 X V 0 0 0 1 0 0 0 K 2 F 0 X (One of the theoretical drawbacks with spice models is that they assume that the bulk) 108 712 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (resistance is 0. This can lead to the simulation of extremely large and unreasonable bulk) 108 698 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.35 (and drain currents. The mathematical precision of floating point arithmetic will then cause) 108 684 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (errors when trying to subtract two large numbers \050we are trying to detect a 5 milliamp) 108 670 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.54 (difference in two 1.0E+20 milliamp numbers\051.If you place a small \050but realistic\051 resistance) 108 656 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (in the bulk, you eliminate these huge currents and this allows the desired I) 108 642 T 2 9.6 Q (s) 463.96 639 T 2 12 Q ( current to be) 467.69 642 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.26 (seen Figure 7 on page 5 shows Test Fixture 1 with a 1 ohm bulk resistance \050NOTE: 1 ohm) 108 628 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.25 (is very small. 100 ohms would be more realistic and show this effect even greater\051. Figure) 108 614 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (8 on page 6 shows Test Fixture 2 under the same conditions.) 108 600 T 0 0 0 1 0 0 0 K 0 F (Figure 7:) 158.95 287 T (IV curve of T) 212.3 287 T (est Fixture 1 with bulk resistance) 278.99 287 T 72 303 540 576 C 72 303 540 576 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 90 0 0 612 792 270 401.13 164.57 240.44 FMBEGINEPSF %%BeginDocument: %!PS-Adobe-2.0 EPSF-2.0 %%BoundingBox: 0 0 612 792 %%DocumentFonts: %%EndComments %%BeginProcSet: /D /setdash load def /L /lineto load def /M /moveto load def /N /newpath load def /S /stroke load def %%EndProcSet %%EndProlog %%Page: 0 1 save 0.50000E+00 setlinewidth 1 setlinecap 1 setlinejoin 612 0 translate -90 rotate 0 -576 translate -720 0 translate N [] 0 D 60 490 M 56 490 L 56 497 L 60 497 L S N 56 493 M 58 493 L S N 64 490 M 64 497 L 68 490 L 68 497 L S N 72 490 M 72 497 L 72 493 L 76 493 L 76 490 L 76 497 L S N 80 490 M 80 493 L 81 497 L 83 497 L 84 493 L 84 490 L S N 80 492 M 84 492 L S N 88 490 M 88 497 L 92 490 L 92 497 L S N 100 491 M 99 490 L 97 490 L 96 491 L 96 496 L 97 497 L 99 497 L 100 496 L S N 108 490 M 104 490 L 104 497 L 108 497 L S N 104 493 M 106 493 L S N 112 490 M 112 497 L 115 497 L 116 496 L 116 491 L 115 490 L 112 490 L S N 128 497 M 128 490 L 132 490 L S N 137 490 M 136 491 L 136 496 L 137 497 L 139 497 L 140 496 L 140 491 L 139 490 L 137 490 L S N 144 497 M 145 490 L 146 497 L 147 490 L 148 497 L S N 153 493 M 155 493 L S N 164 496 M 163 497 L 161 497 L 160 496 L 160 494 L 161 493 L 163 493 L 164 492 L 164 491 L 163 490 L 161 490 L 160 491 L S N 170 490 M 170 497 L 168 497 L 172 497 L S N 176 490 M 176 493 L 177 497 L 179 497 L 180 493 L 180 490 L S N 176 492 M 180 492 L S N 186 490 M 186 497 L 184 497 L 188 497 L S N 196 490 M 192 490 L 192 497 L 196 497 L S N 192 493 M 194 493 L S N 208 497 M 210 490 L 212 497 L S N 216 490 M 220 497 L S N 225 490 M 227 490 L 226 490 L 226 497 L 225 497 L 227 497 L S N 240 490 M 240 497 L 243 497 L 244 496 L 244 494 L 243 493 L 240 493 L S N 248 497 M 248 490 L 252 490 L S N 257 490 M 256 491 L 256 496 L 257 497 L 259 497 L 260 496 L 260 491 L 259 490 L 257 490 L S N 266 490 M 266 497 L 264 497 L 268 497 L S N 274 490 M 273 489 L S N 289 490 M 291 490 L 290 490 L 290 497 L 289 497 L 291 497 L S N 296 490 M 296 497 L 300 490 L 300 497 L S N 308 491 M 307 490 L 305 490 L 304 491 L 304 496 L 305 497 L 307 497 L 308 496 L S N 312 497 M 312 490 L 316 490 L S N 320 497 M 320 491 L 321 490 L 323 490 L 324 491 L 324 497 L S N 328 490 M 328 497 L 331 497 L 332 496 L 332 491 L 331 490 L 328 490 L S N 337 490 M 339 490 L 338 490 L 338 497 L 337 497 L 339 497 L S N 344 490 M 344 497 L 348 490 L 348 497 L S N 356 496 M 355 497 L 353 497 L 352 496 L 352 491 L 353 490 L 355 490 L 356 491 L 356 493 L 354 493 L 354 492 L S N 369 496 M 370 497 L 370 490 L 369 490 L 371 490 L S N 378 490 M 379 490 L S N 386 490 M 385 491 L 385 496 L 386 497 L 387 497 L 388 496 L 388 491 L 387 490 L 386 490 L S N 401 490 M 400 491 L 400 496 L 401 497 L 403 497 L 404 496 L 404 491 L 403 490 L 401 490 L S N 408 490 M 408 497 L 408 493 L 412 493 L 412 490 L 412 497 L S N 416 490 M 416 497 L 418 493 L 420 497 L 420 490 L S N 428 496 M 427 497 L 425 497 L 424 496 L 424 494 L 425 493 L 427 493 L 428 492 L 428 491 L 427 490 L 425 490 L 424 491 L S N 444 496 M 443 497 L 441 497 L 440 496 L 440 494 L 441 493 L 443 493 L 444 492 L 444 491 L 443 490 L 441 490 L 440 491 L S N 448 497 M 448 491 L 449 490 L 451 490 L 452 491 L 452 497 L S N 456 490 M 456 497 L 459 497 L 460 496 L 460 494 L 459 493 L 456 493 L 459 493 L 460 492 L 460 491 L 459 490 L 456 490 L S N 468 496 M 467 497 L 465 497 L 464 496 L 464 494 L 465 493 L 467 493 L 468 492 L 468 491 L 467 490 L 465 490 L 464 491 L S N 474 490 M 474 497 L 472 497 L 476 497 L S N 480 490 M 480 497 L 483 497 L 484 496 L 484 494 L 483 493 L 480 493 L 482 493 L 484 490 L S N 488 490 M 488 493 L 489 497 L 491 497 L 492 493 L 492 490 L S N 488 492 M 492 492 L S N 498 490 M 498 497 L 496 497 L 500 497 L S N 508 490 M 504 490 L 504 497 L 508 497 L S N 504 493 M 506 493 L S N 520 490 M 520 497 L 523 497 L 524 496 L 524 494 L 523 493 L 520 493 L 522 493 L 524 490 L S N 532 490 M 528 490 L 528 497 L 532 497 L S N 528 493 M 530 493 L S N 540 496 M 539 497 L 537 497 L 536 496 L 536 494 L 537 493 L 539 493 L 540 492 L 540 491 L 539 490 L 537 490 L 536 491 L S N 545 490 M 547 490 L 546 490 L 546 497 L 545 497 L 547 497 L S N 556 496 M 555 497 L 553 497 L 552 496 L 552 494 L 553 493 L 555 493 L 556 492 L 556 491 L 555 490 L 553 490 L 552 491 L S N 562 490 M 562 497 L 560 497 L 564 497 L S N 568 490 M 568 493 L 569 497 L 571 497 L 572 493 L 572 490 L S N 568 492 M 572 492 L S N 576 490 M 576 497 L 580 490 L 580 497 L S N 588 491 M 587 490 L 585 490 L 584 491 L 584 496 L 585 497 L 587 497 L 588 496 L S N 596 490 M 592 490 L 592 497 L 596 497 L S N 592 493 M 594 493 L S N 273 487 M 272 483 L 276 483 L S N 275 487 M 275 480 L S N 281 483 M 283 483 L S N 288 480 M 288 483 L 289 487 L 291 487 L 292 483 L 292 480 L S N 288 482 M 292 482 L S N 296 480 M 296 487 L 299 487 L 300 486 L 300 484 L 299 483 L 296 483 L S N 304 480 M 304 487 L 307 487 L 308 486 L 308 484 L 307 483 L 304 483 L 306 483 L 308 480 L S N 312 481 M 313 480 L 315 480 L 316 481 L 316 486 L 315 487 L 313 487 L 312 486 L 312 484 L 313 483 L 315 483 L 316 484 L S N 321 487 M 320 483 L 324 483 L S N 323 487 M 323 480 L S N 337 486 M 338 487 L 338 480 L 337 480 L 339 480 L S N 344 481 M 345 480 L 347 480 L 348 481 L 348 486 L 347 487 L 345 487 L 344 486 L 344 484 L 345 483 L 347 483 L 348 484 L S N 354 481 M 354 482 L S N 354 484 M 354 486 L S N 361 487 M 360 483 L 364 483 L S N 363 487 M 363 480 L S N 369 483 M 368 484 L 368 486 L 369 487 L 371 487 L 372 486 L 372 484 L 371 483 L 369 483 L 368 482 L 368 481 L 369 480 L 371 480 L 372 481 L 372 482 L 371 483 L S N 378 481 M 378 482 L S N 378 484 M 378 486 L S N 388 487 M 384 487 L 384 483 L 385 484 L 387 484 L 388 483 L 388 481 L 387 480 L 385 480 L 384 481 L S N 392 481 M 393 480 L 395 480 L 396 481 L 396 486 L 395 487 L 393 487 L 392 486 L 392 484 L 393 483 L 395 483 L 396 484 L S N [] 0 D 98 40 M 97 41 L 97 46 L 98 47 L 99 47 L 100 46 L 100 41 L 99 40 L 98 40 L S N 106 40 M 107 40 L S N 536 46 M 537 47 L 537 40 L 536 40 L 538 40 L S N 545 40 M 544 41 L 544 46 L 545 47 L 546 47 L 547 46 L 547 41 L 546 40 L 545 40 L S N 553 40 M 552 41 L 552 46 L 553 47 L 554 47 L 555 46 L 555 41 L 554 40 L 553 40 L S N 561 40 M 562 40 L S N 569 40 M 568 41 L 568 46 L 569 47 L 570 47 L 571 46 L 571 41 L 570 40 L 569 40 L S N 575 40 M 575 47 L 577 43 L 579 47 L 579 40 L S N 290 40 M 290 47 L 288 47 L 292 47 L S N 297 40 M 299 40 L 298 40 L 298 47 L 297 47 L 299 47 L S N 304 40 M 304 47 L 306 43 L 308 47 L 308 40 L S N 316 40 M 312 40 L 312 47 L 316 47 L S N 312 43 M 314 43 L S N 331 47 M 330 47 L 329 46 L 329 41 L 330 40 L 331 40 L S N 336 47 M 336 40 L 340 40 L S N 345 40 M 347 40 L 346 40 L 346 47 L 345 47 L 347 47 L S N 352 40 M 352 47 L 356 40 L 356 47 L S N 361 47 M 362 47 L 363 46 L 363 41 L 362 40 L 361 40 L S N [] 0 D 127 60 M 127 64 L S N 150 60 M 150 64 L S N 173 60 M 173 64 L S N 196 60 M 196 64 L S N [] 0 D 188 56 M 189 57 L 191 57 L 192 56 L 192 54 L 191 53 L 189 53 L 188 52 L 188 50 L 192 50 L S N 198 50 M 197 51 L 197 56 L 198 57 L 199 57 L 200 56 L 200 51 L 199 50 L 198 50 L S N 206 50 M 207 50 L S N 214 50 M 213 51 L 213 56 L 214 57 L 215 57 L 216 56 L 216 51 L 215 50 L 214 50 L S N 220 50 M 220 57 L 222 53 L 224 57 L 224 50 L S N [.5 4] 0 D 196 469 M 196 60 L S N [] 0 D 196 60 M 196 68 L S N 219 60 M 219 64 L S N 242 60 M 242 64 L S N 266 60 M 266 64 L S N 289 60 M 289 64 L S N [] 0 D 282 57 M 281 53 L 285 53 L S N 284 57 M 284 50 L S N 291 50 M 290 51 L 290 56 L 291 57 L 292 57 L 293 56 L 293 51 L 292 50 L 291 50 L S N 299 50 M 300 50 L S N 307 50 M 306 51 L 306 56 L 307 57 L 308 57 L 309 56 L 309 51 L 308 50 L 307 50 L S N 313 50 M 313 57 L 315 53 L 317 57 L 317 50 L S N [.5 4] 0 D 289 469 M 289 60 L S N [] 0 D 289 60 M 289 68 L S N 312 60 M 312 64 L S N 335 60 M 335 64 L S N 358 60 M 358 64 L S N 381 60 M 381 64 L S N [] 0 D 377 56 M 376 57 L 374 57 L 373 56 L 373 51 L 374 50 L 376 50 L 377 51 L 377 52 L 376 53 L 374 53 L 373 52 L S N 383 50 M 382 51 L 382 56 L 383 57 L 384 57 L 385 56 L 385 51 L 384 50 L 383 50 L S N 391 50 M 392 50 L S N 399 50 M 398 51 L 398 56 L 399 57 L 400 57 L 401 56 L 401 51 L 400 50 L 399 50 L S N 405 50 M 405 57 L 407 53 L 409 57 L 409 50 L S N [.5 4] 0 D 381 469 M 381 60 L S N [] 0 D 381 60 M 381 68 L S N 404 60 M 404 64 L S N 428 60 M 428 64 L S N 451 60 M 451 64 L S N 474 60 M 474 64 L S N [] 0 D 467 53 M 466 54 L 466 56 L 467 57 L 469 57 L 470 56 L 470 54 L 469 53 L 467 53 L 466 52 L 466 51 L 467 50 L 469 50 L 470 51 L 470 52 L 469 53 L S N 476 50 M 475 51 L 475 56 L 476 57 L 477 57 L 478 56 L 478 51 L 477 50 L 476 50 L S N 484 50 M 485 50 L S N 492 50 M 491 51 L 491 56 L 492 57 L 493 57 L 494 56 L 494 51 L 493 50 L 492 50 L S N 498 50 M 498 57 L 500 53 L 502 57 L 502 50 L S N [.5 4] 0 D 474 469 M 474 60 L S N [] 0 D 474 60 M 474 68 L S N 497 60 M 497 64 L S N 520 60 M 520 64 L S N 543 60 M 543 64 L S N 567 60 M 567 64 L S N [] 0 D 560 56 M 561 57 L 561 50 L 560 50 L 562 50 L S N 569 50 M 568 51 L 568 56 L 569 57 L 570 57 L 571 56 L 571 51 L 570 50 L 569 50 L S N 577 50 M 576 51 L 576 56 L 577 57 L 578 57 L 579 56 L 579 51 L 578 50 L 577 50 L S N 585 50 M 586 50 L S N 593 50 M 592 51 L 592 56 L 593 57 L 594 57 L 595 56 L 595 51 L 594 50 L 593 50 L S N 599 50 M 599 57 L 601 53 L 603 57 L 603 50 L S N [.5 4] 0 D 567 469 M 567 60 L S N [] 0 D 567 60 M 567 68 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 16 310 M 16 313 L 17 317 L 19 317 L 20 313 L 20 310 L S N 16 312 M 20 312 L S N 16 300 M 16 307 L 18 303 L 20 307 L 20 300 L S N 16 290 M 16 297 L 19 297 L 20 296 L 20 294 L 19 293 L 16 293 L S N 16 277 M 16 270 L 20 270 L S N 17 260 M 19 260 L 18 260 L 18 267 L 17 267 L 19 267 L S N 16 250 M 16 257 L 20 250 L 20 257 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N [] 0 D 69 57 M 71 57 L S N 76 60 M 77 61 L 79 61 L 80 60 L 80 58 L 79 57 L 77 57 L 76 56 L 76 54 L 80 54 L S N 86 54 M 87 54 L S N 94 54 M 93 55 L 93 60 L 94 61 L 95 61 L 96 60 L 96 55 L 95 54 L 94 54 L S N [.5 4] 0 D 567 60 M 104 60 L S N [] 0 D 104 60 M 112 60 L S N 104 68 M 108 68 L S N 104 76 M 108 76 L S N 104 84 M 108 84 L S N 104 92 M 108 92 L S N [] 0 D 61 89 M 63 89 L S N 69 92 M 70 93 L 70 86 L 69 86 L 71 86 L S N 78 86 M 79 86 L S N 85 89 M 84 90 L 84 92 L 85 93 L 87 93 L 88 92 L 88 90 L 87 89 L 85 89 L 84 88 L 84 87 L 85 86 L 87 86 L 88 87 L 88 88 L 87 89 L S N 94 86 M 93 87 L 93 92 L 94 93 L 95 93 L 96 92 L 96 87 L 95 86 L 94 86 L S N [.5 4] 0 D 567 92 M 104 92 L S N [] 0 D 104 92 M 112 92 L S N 104 100 M 108 100 L S N 104 109 M 108 109 L S N 104 117 M 108 117 L S N 104 125 M 108 125 L S N [] 0 D 61 122 M 63 122 L S N 69 125 M 70 126 L 70 119 L 69 119 L 71 119 L S N 78 119 M 79 119 L S N 88 125 M 87 126 L 85 126 L 84 125 L 84 120 L 85 119 L 87 119 L 88 120 L 88 121 L 87 122 L 85 122 L 84 121 L S N 94 119 M 93 120 L 93 125 L 94 126 L 95 126 L 96 125 L 96 120 L 95 119 L 94 119 L S N [.5 4] 0 D 567 125 M 104 125 L S N [] 0 D 104 125 M 112 125 L S N 104 133 M 108 133 L S N 104 141 M 108 141 L S N 104 149 M 108 149 L S N 104 158 M 108 158 L S N [] 0 D 61 155 M 63 155 L S N 69 158 M 70 159 L 70 152 L 69 152 L 71 152 L S N 78 152 M 79 152 L S N 85 159 M 84 155 L 88 155 L S N 87 159 M 87 152 L S N 94 152 M 93 153 L 93 158 L 94 159 L 95 159 L 96 158 L 96 153 L 95 152 L 94 152 L S N [.5 4] 0 D 567 158 M 104 158 L S N [] 0 D 104 158 M 112 158 L S N 104 166 M 108 166 L S N 104 174 M 108 174 L S N 104 182 M 108 182 L S N 104 190 M 108 190 L S N [] 0 D 61 187 M 63 187 L S N 69 190 M 70 191 L 70 184 L 69 184 L 71 184 L S N 78 184 M 79 184 L S N 84 190 M 85 191 L 87 191 L 88 190 L 88 188 L 87 187 L 85 187 L 84 186 L 84 184 L 88 184 L S N 94 184 M 93 185 L 93 190 L 94 191 L 95 191 L 96 190 L 96 185 L 95 184 L 94 184 L S N [.5 4] 0 D 567 190 M 104 190 L S N [] 0 D 104 190 M 112 190 L S N 104 199 M 108 199 L S N 104 207 M 108 207 L S N 104 215 M 108 215 L S N 104 223 M 108 223 L S N [] 0 D 69 220 M 71 220 L S N 77 223 M 78 224 L 78 217 L 77 217 L 79 217 L S N 86 217 M 87 217 L S N 94 217 M 93 218 L 93 223 L 94 224 L 95 224 L 96 223 L 96 218 L 95 217 L 94 217 L S N [.5 4] 0 D 567 223 M 104 223 L S N [] 0 D 104 223 M 112 223 L S N 104 231 M 108 231 L S N 104 239 M 108 239 L S N 104 248 M 108 248 L S N 104 256 M 108 256 L S N [] 0 D 45 253 M 47 253 L S N 53 253 M 52 254 L 52 256 L 53 257 L 55 257 L 56 256 L 56 254 L 55 253 L 53 253 L 52 252 L 52 251 L 53 250 L 55 250 L 56 251 L 56 252 L 55 253 L S N 62 250 M 61 251 L 61 256 L 62 257 L 63 257 L 64 256 L 64 251 L 63 250 L 62 250 L S N 70 250 M 69 251 L 69 256 L 70 257 L 71 257 L 72 256 L 72 251 L 71 250 L 70 250 L S N 78 250 M 79 250 L S N 86 250 M 85 251 L 85 256 L 86 257 L 87 257 L 88 256 L 88 251 L 87 250 L 86 250 L S N 92 250 M 92 257 L 94 253 L 96 257 L 96 250 L S N [.5 4] 0 D 567 256 M 104 256 L S N [] 0 D 104 256 M 112 256 L S N 104 264 M 108 264 L S N 104 272 M 108 272 L S N 104 280 M 108 280 L S N 104 289 M 108 289 L S N [] 0 D 45 286 M 47 286 L S N 56 289 M 55 290 L 53 290 L 52 289 L 52 284 L 53 283 L 55 283 L 56 284 L 56 285 L 55 286 L 53 286 L 52 285 L S N 62 283 M 61 284 L 61 289 L 62 290 L 63 290 L 64 289 L 64 284 L 63 283 L 62 283 L S N 70 283 M 69 284 L 69 289 L 70 290 L 71 290 L 72 289 L 72 284 L 71 283 L 70 283 L S N 78 283 M 79 283 L S N 86 283 M 85 284 L 85 289 L 86 290 L 87 290 L 88 289 L 88 284 L 87 283 L 86 283 L S N 92 283 M 92 290 L 94 286 L 96 290 L 96 283 L S N [.5 4] 0 D 567 289 M 104 289 L S N [] 0 D 104 289 M 112 289 L S N 104 297 M 108 297 L S N 104 305 M 108 305 L S N 104 313 M 108 313 L S N 104 321 M 108 321 L S N [] 0 D 45 318 M 47 318 L S N 53 322 M 52 318 L 56 318 L S N 55 322 M 55 315 L S N 62 315 M 61 316 L 61 321 L 62 322 L 63 322 L 64 321 L 64 316 L 63 315 L 62 315 L S N 70 315 M 69 316 L 69 321 L 70 322 L 71 322 L 72 321 L 72 316 L 71 315 L 70 315 L S N 78 315 M 79 315 L S N 86 315 M 85 316 L 85 321 L 86 322 L 87 322 L 88 321 L 88 316 L 87 315 L 86 315 L S N 92 315 M 92 322 L 94 318 L 96 322 L 96 315 L S N [.5 4] 0 D 567 321 M 104 321 L S N [] 0 D 104 321 M 112 321 L S N 104 329 M 108 329 L S N 104 338 M 108 338 L S N 104 346 M 108 346 L S N 104 354 M 108 354 L S N [] 0 D 45 351 M 47 351 L S N 52 354 M 53 355 L 55 355 L 56 354 L 56 352 L 55 351 L 53 351 L 52 350 L 52 348 L 56 348 L S N 62 348 M 61 349 L 61 354 L 62 355 L 63 355 L 64 354 L 64 349 L 63 348 L 62 348 L S N 70 348 M 69 349 L 69 354 L 70 355 L 71 355 L 72 354 L 72 349 L 71 348 L 70 348 L S N 78 348 M 79 348 L S N 86 348 M 85 349 L 85 354 L 86 355 L 87 355 L 88 354 L 88 349 L 87 348 L 86 348 L S N 92 348 M 92 355 L 94 351 L 96 355 L 96 348 L S N [.5 4] 0 D 567 354 M 104 354 L S N [] 0 D 104 354 M 112 354 L S N 104 362 M 108 362 L S N 104 370 M 108 370 L S N 104 379 M 108 379 L S N 104 387 M 108 387 L S N [] 0 D 86 381 M 85 382 L 85 387 L 86 388 L 87 388 L 88 387 L 88 382 L 87 381 L 86 381 L S N 94 381 M 95 381 L S N [.5 4] 0 D 567 387 M 104 387 L S N [] 0 D 104 387 M 112 387 L S N 104 395 M 108 395 L S N 104 403 M 108 403 L S N 104 411 M 108 411 L S N 104 419 M 108 419 L S N [] 0 D 52 419 M 53 420 L 55 420 L 56 419 L 56 417 L 55 416 L 53 416 L 52 415 L 52 413 L 56 413 L S N 62 413 M 61 414 L 61 419 L 62 420 L 63 420 L 64 419 L 64 414 L 63 413 L 62 413 L S N 70 413 M 69 414 L 69 419 L 70 420 L 71 420 L 72 419 L 72 414 L 71 413 L 70 413 L S N 78 413 M 79 413 L S N 86 413 M 85 414 L 85 419 L 86 420 L 87 420 L 88 419 L 88 414 L 87 413 L 86 413 L S N 92 413 M 92 420 L 94 416 L 96 420 L 96 413 L S N [.5 4] 0 D 567 419 M 104 419 L S N [] 0 D 104 419 M 112 419 L S N 104 428 M 108 428 L S N 104 436 M 108 436 L S N 104 444 M 108 444 L S N 104 452 M 108 452 L S N [] 0 D 53 453 M 52 449 L 56 449 L S N 55 453 M 55 446 L S N 62 446 M 61 447 L 61 452 L 62 453 L 63 453 L 64 452 L 64 447 L 63 446 L 62 446 L S N 70 446 M 69 447 L 69 452 L 70 453 L 71 453 L 72 452 L 72 447 L 71 446 L 70 446 L S N 78 446 M 79 446 L S N 86 446 M 85 447 L 85 452 L 86 453 L 87 453 L 88 452 L 88 447 L 87 446 L 86 446 L S N 92 446 M 92 453 L 94 449 L 96 453 L 96 446 L S N [.5 4] 0 D 567 452 M 104 452 L S N [] 0 D 104 452 M 112 452 L S N 104 460 M 108 460 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 559 60 L S N 567 68 M 563 68 L S N 567 76 M 563 76 L S N 567 84 M 563 84 L S N 567 92 M 563 92 L S N 567 92 M 559 92 L S N 567 100 M 563 100 L S N 567 109 M 563 109 L S N 567 117 M 563 117 L S N 567 125 M 563 125 L S N 567 125 M 559 125 L S N 567 133 M 563 133 L S N 567 141 M 563 141 L S N 567 149 M 563 149 L S N 567 158 M 563 158 L S N 567 158 M 559 158 L S N 567 166 M 563 166 L S N 567 174 M 563 174 L S N 567 182 M 563 182 L S N 567 190 M 563 190 L S N 567 190 M 559 190 L S N 567 199 M 563 199 L S N 567 207 M 563 207 L S N 567 215 M 563 215 L S N 567 223 M 563 223 L S N 567 223 M 559 223 L S N 567 231 M 563 231 L S N 567 239 M 563 239 L S N 567 248 M 563 248 L S N 567 256 M 563 256 L S N 567 256 M 559 256 L S N 567 264 M 563 264 L S N 567 272 M 563 272 L S N 567 280 M 563 280 L S N 567 289 M 563 289 L S N 567 289 M 559 289 L S N 567 297 M 563 297 L S N 567 305 M 563 305 L S N 567 313 M 563 313 L S N 567 321 M 563 321 L S N 567 321 M 559 321 L S N 567 329 M 563 329 L S N 567 338 M 563 338 L S N 567 346 M 563 346 L S N 567 354 M 563 354 L S N 567 354 M 559 354 L S N 567 362 M 563 362 L S N 567 370 M 563 370 L S N 567 379 M 563 379 L S N 567 387 M 563 387 L S N 567 387 M 559 387 L S N 567 395 M 563 395 L S N 567 403 M 563 403 L S N 567 411 M 563 411 L S N 567 419 M 563 419 L S N 567 419 M 559 419 L S N 567 428 M 563 428 L S N 567 436 M 563 436 L S N 567 444 M 563 444 L S N 567 452 M 563 452 L S N 567 452 M 559 452 L S N 567 460 M 563 460 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 584 467 M 588 460 L S N 584 460 M 588 467 L S N 592 467 M 596 460 L S N 592 460 M 596 467 L S N 600 467 M 604 460 L S N 600 460 M 604 467 L S N 608 467 M 612 460 L S N 608 460 M 612 467 L S N 618 460 M 619 460 L S N 626 460 M 626 467 L 624 467 L 628 467 L S N 632 460 M 632 467 L 635 467 L 636 466 L 636 464 L 635 463 L 632 463 L 634 463 L 636 460 L S N 642 460 M 641 461 L 641 466 L 642 467 L 643 467 L 644 466 L 644 461 L 643 460 L 642 460 L S N 585 450 M 587 450 L 586 450 L 586 457 L 585 457 L 587 457 L S N 595 457 M 594 457 L 593 456 L 593 451 L 594 450 L 595 450 L S N 600 457 M 602 450 L 604 457 L S N 608 450 M 608 457 L 611 457 L 612 456 L 612 451 L 611 450 L 608 450 L S N 617 456 M 618 457 L 618 450 L 617 450 L 619 450 L S N 576 441 M 580 448 L 583 441 L 576 441 L S N 580 445 M 663 445 L S N 184 60 M 184 62 L 185 64 L 185 67 L 185 70 L 186 73 L 186 76 L 187 78 L 187 81 L 188 84 L 188 87 L 189 89 L 189 92 L 190 95 L 190 98 L 191 101 L 191 103 L 191 106 L 192 109 L 192 112 L 193 114 L 193 117 L 194 120 L 194 123 L 195 126 L 195 128 L 196 131 L 196 134 L 197 137 L 197 139 L 197 142 L 198 145 L 198 148 L 199 151 L 199 153 L 200 156 L 200 159 L 201 162 L 201 164 L 202 167 L 202 170 L 203 173 L 203 176 L 204 178 L 204 181 L 204 184 L 205 187 L 205 190 L 206 192 L 206 195 L 207 198 L 207 201 L 208 203 L 208 206 L 209 209 L 209 212 L 210 215 L 210 217 L 210 220 L 211 223 L 211 226 L 212 228 L 212 231 L 213 234 L 213 237 L 214 240 L 214 242 L 215 245 L 215 248 L 216 251 L 216 253 L 216 256 L 217 259 L 217 262 L 218 264 L 218 267 L 219 270 L 219 273 L 220 275 L 220 278 L 221 281 L 221 284 L 222 286 L 222 289 L 222 292 L 223 295 L 223 297 L 224 300 L 224 303 L 225 305 L 225 308 L 226 311 L 226 313 L 227 316 L 227 319 L 228 321 L 228 324 L 229 327 L 229 329 L 229 332 L 230 334 L 230 337 L 231 339 L 231 342 L 232 344 L 232 346 L 233 349 L 233 351 L 234 353 L 234 355 L 235 356 L 235 358 L 235 359 L 236 360 L 236 361 L 237 362 L 237 363 L 238 363 L 238 364 L 239 365 L 240 366 L 241 367 L 241 368 L 242 368 L 242 369 L 243 369 L 243 370 L 244 370 L 244 371 L 245 371 L 245 372 L 246 372 L 246 373 L 247 373 L 247 374 L 248 375 L 249 376 L 250 377 L 250 378 L 251 378 L 251 379 L 252 379 L 252 380 L 253 380 L 253 381 L 254 381 L 254 382 L 254 383 L 255 383 L 255 384 L 256 384 L 256 385 L 257 385 L 257 386 L 258 387 L 259 388 L 260 389 L 260 390 L 261 390 L 261 391 L 262 392 L 263 393 L 264 394 L 265 395 L 266 396 L 266 397 L 267 397 L 267 398 L 268 398 L 268 399 L 269 399 L 269 400 L 270 400 L 270 401 L 271 401 L 271 402 L 272 402 L 272 403 L 273 403 L 273 404 L 274 404 L 274 405 L 275 405 L 275 406 L 276 406 L 276 407 L 277 407 L 278 408 L 279 409 L 279 410 L 280 410 L 281 411 L 282 412 L 283 412 L 283 413 L 284 413 L 285 414 L 285 415 L 286 415 L 287 416 L 288 416 L S N 288 416 M 288 417 L 289 417 L 290 418 L 291 418 L 291 419 L 292 419 L 292 420 L 293 420 L 294 421 L 295 421 L 295 422 L 296 422 L 297 423 L 298 423 L 298 424 L 299 424 L 300 425 L 301 425 L 302 426 L 303 426 L 304 427 L 305 427 L 305 428 L 306 428 L 307 428 L 307 429 L 308 429 L 309 429 L 309 430 L 310 430 L 311 430 L 311 431 L 312 431 L 313 431 L 314 432 L 315 432 L 316 432 L 316 433 L 317 433 L 318 433 L 318 434 L 319 434 L 320 434 L 321 434 L 321 435 L 322 435 L 323 435 L 324 435 L 324 436 L 325 436 L 326 436 L 327 436 L 328 437 L 329 437 L 330 437 L 331 437 L 331 438 L 332 438 L 333 438 L 334 438 L 335 438 L 335 439 L 336 439 L 337 439 L 338 439 L 339 439 L 340 439 L 341 440 L 342 440 L 343 440 L 344 440 L 345 440 L 346 440 L 347 440 L 348 440 L 349 441 L 350 441 L 351 441 L 352 441 L 353 441 L 354 441 L 355 441 L 356 441 L 357 441 L 358 441 L 359 441 L 360 441 L 361 441 L 362 441 L 363 441 L 364 441 L 365 442 L 366 442 L 367 442 L 368 442 L 369 442 L 370 442 L 371 442 L 372 442 L 373 442 L 374 442 L 375 442 L 376 442 L 377 442 L 378 442 L 379 442 L 380 442 L 381 442 L 381 443 L 382 443 L 383 443 L 384 443 L 385 443 L 386 443 L 387 443 L 388 443 L 389 443 L 390 443 L 391 443 L 392 443 L 393 443 L 394 443 L 395 443 L 396 443 L 397 443 L 398 444 L 399 444 L 400 444 L 401 444 L 402 444 L 403 444 L 404 444 L 405 444 L 406 444 L 407 444 L 408 444 L 409 444 L 410 444 L 411 444 L 412 444 L 413 444 L 414 444 L 414 445 L 415 445 L 416 445 L 417 445 L 418 445 L 419 445 L 420 445 L 421 445 L 422 445 L 423 445 L 424 445 L 425 445 L 426 445 L 427 445 L 428 445 L 429 445 L 430 445 L 430 446 L 431 446 L 432 446 L 433 446 L 434 446 L 435 446 L 436 446 L 437 446 L 438 446 L 439 446 L 440 446 L 441 446 L 442 446 L 443 446 L 444 446 L 445 446 L 446 446 L 447 447 L 448 447 L 449 447 L 450 447 L 451 447 L 452 447 L 453 447 L 454 447 L 455 447 L 456 447 L 457 447 L 458 447 L 459 447 L 460 447 L 461 447 L 462 447 L 462 448 L 463 448 L 464 448 L 465 448 L 466 448 L 467 448 L 468 448 L 469 448 L S N 469 448 M 470 448 L 471 448 L 472 448 L 473 448 L 474 448 L 475 448 L 476 448 L 477 448 L 478 448 L 478 449 L 479 449 L 480 449 L 481 449 L 482 449 L 483 449 L 484 449 L 485 449 L 486 449 L 487 449 L 488 449 L 489 449 L 490 449 L 491 449 L 492 449 L 493 449 L 494 450 L 495 450 L 496 450 L 497 450 L 498 450 L 499 450 L 500 450 L 501 450 L 502 450 L 503 450 L 504 450 L 505 450 L 506 450 L 507 450 L 508 450 L 509 450 L 510 451 L 511 451 L 512 451 L 513 451 L 514 451 L 515 451 L 516 451 L 517 451 L 518 451 L 519 451 L 520 451 L 521 451 L 522 451 L 523 451 L 524 451 L 525 452 L 526 452 L 527 452 L 528 452 L 529 452 L 530 452 L 531 452 L 532 452 L 533 452 L 534 452 L 535 452 L 536 452 L 537 452 L 538 452 L 539 452 L 540 452 L 540 453 L 541 453 L 542 453 L 543 453 L 544 453 L 545 453 L 546 453 L 547 453 L 548 453 L 549 453 L 550 453 L 551 453 L 552 453 L 553 453 L 554 453 L 555 454 L 556 454 L 557 454 L 558 454 L 559 454 L 560 454 L 561 454 L 562 454 L 563 454 L 564 454 L 565 454 L S N 565 454 M 566 454 L 567 454 L S N 563 450 M 567 457 L 570 450 L 563 450 L S N 585 430 M 587 430 L 586 430 L 586 437 L 585 437 L 587 437 L S N 595 437 M 594 437 L 593 436 L 593 431 L 594 430 L 595 430 L S N 600 437 M 602 430 L 604 437 L S N 612 436 M 611 437 L 609 437 L 608 436 L 608 434 L 609 433 L 611 433 L 612 432 L 612 431 L 611 430 L 609 430 L 608 431 L S N 617 436 M 618 437 L 618 430 L 617 430 L 619 430 L S N 576 421 M 576 428 L 583 428 L 583 421 L 576 421 L S N [15 3] 0 D 580 425 M 663 425 L S N 104 260 M 104 261 L 105 261 L 106 262 L 107 262 L 108 263 L 109 263 L 109 264 L 110 264 L 111 265 L 112 265 L 112 266 L 113 266 L 114 266 L 114 267 L 115 267 L 116 268 L 117 268 L 117 269 L 118 269 L 119 270 L 120 270 L 120 271 L 121 271 L 122 271 L 122 272 L 123 272 L 123 273 L 124 273 L 125 274 L 126 274 L 127 275 L 128 275 L 128 276 L 129 276 L 129 277 L 130 277 L 131 277 L 131 278 L 132 278 L 133 279 L 134 279 L 134 280 L 135 280 L 135 281 L 136 281 L 137 281 L 137 282 L 138 282 L 139 283 L 140 283 L 140 284 L 141 284 L 141 285 L 142 285 L 143 285 L 143 286 L 144 286 L 145 287 L 146 287 L 146 288 L 147 288 L 147 289 L 148 289 L 149 290 L 150 290 L 150 291 L 151 291 L 152 292 L 153 292 L 154 293 L 155 294 L 156 294 L 156 295 L 157 295 L 158 296 L 159 296 L 159 297 L 160 297 L 160 298 L 161 298 L 162 299 L 163 299 L 163 300 L 164 300 L 165 301 L 166 301 L 166 302 L 167 302 L 167 303 L 168 303 L 169 304 L 170 304 L 170 305 L 171 305 L 172 306 L 173 307 L 174 308 L 175 308 L 175 309 L 176 309 L 177 310 L 178 310 L 178 311 L 179 311 L 179 312 L 180 312 L 181 313 L 182 314 L 183 314 L 183 315 L 184 315 L 185 316 L 186 317 L 187 317 L 187 318 L 188 318 L 188 319 L 189 319 L 190 320 L 191 320 L 191 321 L 192 322 L 193 322 L 193 323 L 194 323 L 195 324 L 196 325 L 197 325 L 197 326 L 198 326 L 198 327 L 199 327 L 199 328 L 200 328 L 201 329 L 202 330 L 203 330 L 203 331 L 204 331 L 204 332 L 205 332 L 205 333 L 206 333 L 206 334 L 207 334 L 208 335 L 209 336 L 210 336 L 210 337 L 211 338 L 212 338 L 212 339 L 213 339 L 213 340 L 214 340 L 215 341 L 216 342 L 216 343 L 217 343 L 218 344 L 219 345 L 220 346 L 221 346 L 221 347 L 222 347 L 222 348 L 223 349 L 224 350 L 225 350 L 225 351 L 226 351 L 226 352 L 227 352 L 227 353 L 228 353 L 228 354 L 229 354 L 229 355 L 230 355 L 230 356 L 231 356 L 231 357 L 232 357 L 232 358 L 233 358 L 233 359 L 234 359 L 234 360 L 235 360 L 235 361 L 236 362 L 237 363 L 238 364 L 239 365 L 240 366 L 241 367 L 241 368 L 242 368 L 242 369 L 243 369 L S N 243 369 M 243 370 L 244 370 L 244 371 L 245 371 L 245 372 L 246 372 L 246 373 L 247 373 L 247 374 L 248 375 L 249 376 L 250 377 L 250 378 L 251 378 L 251 379 L 252 379 L 252 380 L 253 380 L 253 381 L 254 381 L 254 382 L 254 383 L 255 383 L 255 384 L 256 384 L 256 385 L 257 385 L 257 386 L 258 387 L 259 388 L 260 389 L 260 390 L 261 390 L 261 391 L 262 392 L 263 393 L 264 394 L 265 395 L 266 396 L 266 397 L 267 397 L 267 398 L 268 398 L 268 399 L 269 399 L 269 400 L 270 400 L 270 401 L 271 401 L 271 402 L 272 402 L 272 403 L 273 403 L 273 404 L 274 404 L 274 405 L 275 405 L 275 406 L 276 406 L 276 407 L 277 407 L 278 408 L 279 409 L 279 410 L 280 410 L 281 411 L 282 412 L 283 412 L 283 413 L 284 413 L 285 414 L 285 415 L 286 415 L 287 416 L 288 416 L 288 417 L 289 417 L 290 418 L 291 418 L 291 419 L 292 419 L 292 420 L 293 420 L 294 421 L 295 421 L 295 422 L 296 422 L 297 423 L 298 423 L 298 424 L 299 424 L 300 425 L 301 425 L 302 426 L 303 426 L 304 427 L 305 427 L 305 428 L 306 428 L 307 428 L 307 429 L 308 429 L 309 429 L 309 430 L 310 430 L 311 430 L 311 431 L 312 431 L 313 431 L 314 432 L 315 432 L 316 432 L 316 433 L 317 433 L 318 433 L 318 434 L 319 434 L 320 434 L 321 434 L 321 435 L 322 435 L 323 435 L 324 435 L 324 436 L 325 436 L 326 436 L 327 436 L 328 437 L 329 437 L 330 437 L 331 437 L 331 438 L 332 438 L 333 438 L 334 438 L 335 438 L 335 439 L 336 439 L 337 439 L 338 439 L 339 439 L 340 439 L 341 440 L 342 440 L 343 440 L 344 440 L 345 440 L 346 440 L 347 440 L 348 440 L 349 441 L 350 441 L 351 441 L 352 441 L 353 441 L 354 441 L 355 441 L 356 441 L 357 441 L 358 441 L 359 441 L 360 441 L 361 441 L 362 441 L 363 441 L 364 441 L 365 442 L 366 442 L 367 442 L 368 442 L 369 442 L 370 442 L 371 442 L 372 442 L 373 442 L 374 442 L 375 442 L 376 442 L 377 442 L 378 442 L 379 442 L 380 442 L 381 442 L 381 443 L 382 443 L 383 443 L 384 443 L 385 443 L 386 443 L 387 443 L 388 443 L 389 443 L 390 443 L 391 443 L 392 443 L 393 443 L 394 443 L 395 443 L 396 443 L 397 443 L S N 397 443 M 398 444 L 399 444 L 400 444 L 401 444 L 402 444 L 403 444 L 404 444 L 405 444 L 406 444 L 407 444 L 408 444 L 409 444 L 410 444 L 411 444 L 412 444 L 413 444 L 414 444 L 414 445 L 415 445 L 416 445 L 417 445 L 418 445 L 419 445 L 420 445 L 421 445 L 422 445 L 423 445 L 424 445 L 425 445 L 426 445 L 427 445 L 428 445 L 429 445 L 430 445 L 430 446 L 431 446 L 432 446 L 433 446 L 434 446 L 435 446 L 436 446 L 437 446 L 438 446 L 439 446 L 440 446 L 441 446 L 442 446 L 443 446 L 444 446 L 445 446 L 446 446 L 447 447 L 448 447 L 449 447 L 450 447 L 451 447 L 452 447 L 453 447 L 454 447 L 455 447 L 456 447 L 457 447 L 458 447 L 459 447 L 460 447 L 461 447 L 462 447 L 462 448 L 463 448 L 464 448 L 465 448 L 466 448 L 467 448 L 468 448 L 469 448 L 470 448 L 471 448 L 472 448 L 473 448 L 474 448 L 475 448 L 476 448 L 477 448 L 478 448 L 478 449 L 479 449 L 480 449 L 481 449 L 482 449 L 483 449 L 484 449 L 485 449 L 486 449 L 487 449 L 488 449 L 489 449 L 490 449 L 491 449 L 492 449 L 493 449 L 494 450 L 495 450 L 496 450 L 497 450 L 498 450 L 499 450 L 500 450 L 501 450 L 502 450 L 503 450 L 504 450 L 505 450 L 506 450 L 507 450 L 508 450 L 509 450 L 510 451 L 511 451 L 512 451 L 513 451 L 514 451 L 515 451 L 516 451 L 517 451 L 518 451 L 519 451 L 520 451 L 521 451 L 522 451 L 523 451 L 524 451 L 525 452 L 526 452 L 527 452 L 528 452 L 529 452 L 530 452 L 531 452 L 532 452 L 533 452 L 534 452 L 535 452 L 536 452 L 537 452 L 538 452 L 539 452 L 540 452 L 540 453 L 541 453 L 542 453 L 543 453 L 544 453 L 545 453 L 546 453 L 547 453 L 548 453 L 549 453 L 550 453 L 551 453 L 552 453 L 553 453 L 554 453 L 555 454 L 556 454 L 557 454 L 558 454 L 559 454 L 560 454 L 561 454 L 562 454 L 563 454 L 564 454 L 565 454 L S N 565 454 M 566 454 L 567 454 L S N [] 0 D 563 450 M 563 457 L 570 457 L 570 450 L 563 450 L S N 585 410 M 587 410 L 586 410 L 586 417 L 585 417 L 587 417 L S N 595 417 M 594 417 L 593 416 L 593 411 L 594 410 L 595 410 L S N 600 417 M 602 410 L 604 417 L S N 608 410 M 608 417 L 611 417 L 612 416 L 612 414 L 611 413 L 608 413 L 611 413 L 612 412 L 612 411 L 611 410 L 608 410 L S N 617 416 M 618 417 L 618 410 L 617 410 L 619 410 L S N 576 405 M 578 408 L 581 408 L 583 405 L 581 401 L 578 401 L 576 405 L S N [10 3 1 3] 0 D 580 405 M 663 405 L S N 170 60 M 171 63 L 171 65 L 172 68 L 172 70 L 172 73 L 173 75 L 173 77 L 174 80 L 174 82 L 175 85 L 175 87 L 176 90 L 176 92 L 177 94 L 177 97 L 178 99 L 178 102 L 179 104 L 179 106 L 179 109 L 180 111 L 180 114 L 181 116 L 181 119 L 182 121 L 182 123 L 183 126 L 183 128 L 184 131 L 184 133 L 185 135 L 185 138 L 185 140 L 186 143 L 186 145 L 187 148 L 187 150 L 188 152 L 188 155 L 189 157 L 189 160 L 190 162 L 190 164 L 191 167 L 191 169 L 191 172 L 192 174 L 192 176 L 193 179 L 193 181 L 194 184 L 194 186 L 195 188 L 195 191 L 196 193 L 196 196 L 197 198 L 197 200 L 197 203 L 198 205 L 198 208 L 199 210 L 199 212 L 200 215 L 200 217 L 201 220 L 201 222 L 202 224 L 202 227 L 203 229 L 203 232 L 204 234 L 204 236 L 204 239 L 205 241 L 205 244 L 206 246 L 206 248 L 207 251 L 207 253 L 208 255 L 208 258 L 209 260 L 209 263 L 210 265 L 210 267 L 210 270 L 211 272 L 211 274 L 212 277 L 212 279 L 213 281 L 213 284 L 214 286 L 214 289 L 215 291 L 215 293 L 216 296 L 216 298 L 216 300 L 217 303 L 217 305 L 218 307 L 218 310 L 219 312 L 219 314 L 220 317 L 220 319 L 221 321 L 221 324 L 222 326 L 222 328 L 222 330 L 223 333 L 223 335 L 224 337 L 224 339 L 225 342 L 225 344 L 226 346 L 226 348 L 227 351 L 227 353 L 228 355 L 228 357 L 229 359 L 229 361 L 229 363 L 230 366 L 230 368 L 231 370 L 231 372 L 232 373 L 232 375 L 233 377 L 233 379 L 234 380 L 234 382 L 235 383 L 235 384 L 235 385 L 236 385 L 236 386 L 237 386 L 238 387 L 239 387 L 240 387 L 241 387 L 242 387 L 243 387 L 244 387 L 245 387 L 246 387 L 247 387 L 248 387 L 249 387 L 250 387 L 251 387 L 252 387 L 253 387 L 254 387 L 255 387 L 256 387 L 257 387 L 258 387 L 259 387 L 260 387 L 261 387 L 262 387 L 263 387 L 264 387 L 265 387 L 266 387 L 267 387 L 268 387 L 269 387 L 270 387 L 271 387 L 272 387 L 273 387 L 274 387 L 275 387 L 276 387 L 277 387 L 278 387 L 279 387 L 280 387 L 281 387 L 282 387 L 283 387 L 284 387 L 285 387 L 286 387 L 287 387 L 288 387 L 289 387 L 290 387 L 291 387 L 292 387 L 293 387 L S N 293 387 M 294 387 L 295 387 L 296 387 L 297 387 L 298 387 L 299 387 L 300 387 L 301 387 L 302 387 L 303 387 L 304 387 L 305 387 L 306 387 L 307 387 L 308 387 L 309 387 L 310 387 L 311 387 L 312 387 L 313 387 L 314 387 L 315 387 L 316 387 L 317 387 L 318 387 L 319 387 L 320 387 L 321 387 L 322 387 L 323 387 L 324 387 L 325 387 L 326 387 L 327 387 L 328 387 L 329 387 L 330 387 L 331 387 L 332 387 L 333 387 L 334 387 L 335 387 L 336 387 L 337 387 L 338 387 L 339 387 L 340 387 L 341 387 L 342 387 L 343 387 L 344 387 L 345 387 L 346 387 L 347 387 L 348 387 L 349 387 L 350 387 L 351 387 L 352 387 L 353 387 L 354 387 L 355 387 L 356 387 L 357 387 L 358 387 L 359 387 L 360 387 L 361 387 L 362 387 L 363 387 L 364 387 L 365 387 L 366 387 L 367 387 L 368 387 L 369 387 L 370 387 L 371 387 L 372 387 L 373 387 L 374 387 L 375 387 L 376 387 L 377 387 L 378 387 L 379 387 L 380 387 L 381 387 L 382 387 L 383 387 L 384 387 L 385 387 L 386 387 L 387 387 L 388 387 L 389 387 L 390 387 L 391 387 L 392 387 L 393 387 L 394 387 L 395 387 L 396 387 L 397 387 L 398 387 L 399 387 L 400 387 L 401 387 L 402 387 L 403 387 L 404 387 L 405 387 L 406 387 L 407 387 L 408 387 L 409 387 L 410 387 L 411 387 L 412 387 L 413 387 L 414 387 L 415 387 L 416 387 L 417 387 L 418 387 L 419 387 L 420 387 L 421 387 L 422 387 L 423 387 L 424 387 L 425 387 L 426 387 L 427 387 L 428 387 L 429 387 L 430 387 L 431 387 L 432 387 L 433 387 L 434 387 L 435 387 L 436 387 L 437 387 L 438 387 L 439 387 L 440 387 L 441 387 L 442 387 L 443 387 L 444 387 L 445 387 L 446 387 L 447 387 L 448 387 L 449 387 L 450 387 L 451 387 L 452 387 L 453 387 L 454 387 L 455 387 L 456 387 L 457 387 L 458 387 L 459 387 L 460 387 L 461 387 L 462 387 L 463 387 L 464 387 L 465 387 L 466 387 L 467 387 L 468 387 L 469 387 L 470 387 L 471 387 L 472 387 L 473 387 L 474 387 L 475 387 L 476 387 L 477 387 L 478 387 L 479 387 L 480 387 L 481 387 L 482 387 L 483 387 L 484 387 L 485 387 L 486 387 L 487 387 L 488 387 L 489 387 L 490 387 L 491 387 L 492 387 L 493 387 L S N 493 387 M 494 387 L 495 387 L 496 387 L 497 387 L 498 387 L 499 387 L 500 387 L 501 387 L 502 387 L 503 387 L 504 387 L 505 387 L 506 387 L 507 387 L 508 387 L 509 387 L 510 387 L 511 387 L 512 387 L 513 387 L 514 387 L 515 387 L 516 387 L 517 387 L 518 387 L 519 387 L 520 387 L 521 387 L 522 387 L 523 387 L 524 387 L 525 387 L 526 387 L 527 387 L 528 387 L 529 387 L 530 387 L 531 387 L 532 387 L 533 387 L 534 387 L 535 387 L 536 387 L 537 387 L 538 387 L 539 387 L 540 387 L 541 387 L 542 387 L 543 387 L 544 387 L 545 387 L 546 387 L 547 387 L 548 387 L 549 387 L 550 387 L 551 387 L 552 387 L 553 387 L 554 387 L 555 387 L 556 387 L 557 387 L 558 387 L 559 387 L 560 387 L 561 387 L 562 387 L 563 387 L 564 387 L 565 387 L S N 565 387 M 566 387 L 567 387 L S N [] 0 D 563 387 M 565 390 L 568 390 L 570 387 L 568 383 L 565 383 L 563 387 L S 0 0 M showpage restore %%Trailer %%EndDocument FMENDEPSF 72 303 540 576 C 0 0 612 792 C FMENDPAGE %%EndPage: "5" 5 %%Page: "6" 6 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] [ 0 0 0 0 1 1 1] [ 0 0 0 1 0 0 0] 9 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 72 748.8 540 768.6 R 7 X 0 0 0 1 0 0 0 K V 0 11.2 Q 0 X (METHOD 2) 72 755.24 T 72 18 540 54 R 7 X V 0 10 Q 0 X (Measuring Pulldown Currents in CMOS devices) 328.83 35.33 T 1 12 Q (6) 72 23.33 T 0 10 Q (April 15, 1994 2:01 pm) 439.39 23.33 T 72 765.96 539.67 765.96 2 L 1 H 2 Z N 72 751.89 540 751.89 2 L N 72.33 46 540 46 2 L N 72 72 540 720 R 7 X V 0 0 0 1 0 0 0 K 2 12 Q 0 X (Under these conditions the Bulk currents differences can be neglected and the) 144 393 T 0 0 0 1 0 0 0 K 0 F (Figure 8:) 162.28 425 T (IV curve of test \336xture 2 with bulk resistance) 215.63 425 T 72 441 540 720 C 72 441 540 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 90 0 0 612 792 276.03 351 172.49 406.49 FMBEGINEPSF %%BeginDocument: %!PS-Adobe-2.0 EPSF-2.0 %%BoundingBox: 0 0 612 792 %%DocumentFonts: %%EndComments %%BeginProcSet: /D /setdash load def /L /lineto load def /M /moveto load def /N /newpath load def /S /stroke load def %%EndProcSet %%EndProlog %%Page: 0 1 save 0.50000E+00 setlinewidth 1 setlinecap 1 setlinejoin 612 0 translate -90 rotate 0 -576 translate -720 0 translate N [] 0 D 60 490 M 56 490 L 56 497 L 60 497 L S N 56 493 M 58 493 L S N 64 490 M 64 497 L 68 490 L 68 497 L S N 72 490 M 72 497 L 72 493 L 76 493 L 76 490 L 76 497 L S N 80 490 M 80 493 L 81 497 L 83 497 L 84 493 L 84 490 L S N 80 492 M 84 492 L S N 88 490 M 88 497 L 92 490 L 92 497 L S N 100 491 M 99 490 L 97 490 L 96 491 L 96 496 L 97 497 L 99 497 L 100 496 L S N 108 490 M 104 490 L 104 497 L 108 497 L S N 104 493 M 106 493 L S N 112 490 M 112 497 L 115 497 L 116 496 L 116 491 L 115 490 L 112 490 L S N 128 497 M 128 490 L 132 490 L S N 137 490 M 136 491 L 136 496 L 137 497 L 139 497 L 140 496 L 140 491 L 139 490 L 137 490 L S N 144 497 M 145 490 L 146 497 L 147 490 L 148 497 L S N 153 493 M 155 493 L S N 164 496 M 163 497 L 161 497 L 160 496 L 160 494 L 161 493 L 163 493 L 164 492 L 164 491 L 163 490 L 161 490 L 160 491 L S N 170 490 M 170 497 L 168 497 L 172 497 L S N 176 490 M 176 493 L 177 497 L 179 497 L 180 493 L 180 490 L S N 176 492 M 180 492 L S N 186 490 M 186 497 L 184 497 L 188 497 L S N 196 490 M 192 490 L 192 497 L 196 497 L S N 192 493 M 194 493 L S N 208 497 M 210 490 L 212 497 L S N 216 490 M 220 497 L S N 225 490 M 227 490 L 226 490 L 226 497 L 225 497 L 227 497 L S N 240 490 M 240 497 L 243 497 L 244 496 L 244 494 L 243 493 L 240 493 L S N 248 497 M 248 490 L 252 490 L S N 257 490 M 256 491 L 256 496 L 257 497 L 259 497 L 260 496 L 260 491 L 259 490 L 257 490 L S N 266 490 M 266 497 L 264 497 L 268 497 L S N 274 490 M 273 489 L S N 289 490 M 291 490 L 290 490 L 290 497 L 289 497 L 291 497 L S N 296 490 M 296 497 L 300 490 L 300 497 L S N 308 491 M 307 490 L 305 490 L 304 491 L 304 496 L 305 497 L 307 497 L 308 496 L S N 312 497 M 312 490 L 316 490 L S N 320 497 M 320 491 L 321 490 L 323 490 L 324 491 L 324 497 L S N 328 490 M 328 497 L 331 497 L 332 496 L 332 491 L 331 490 L 328 490 L S N 337 490 M 339 490 L 338 490 L 338 497 L 337 497 L 339 497 L S N 344 490 M 344 497 L 348 490 L 348 497 L S N 356 496 M 355 497 L 353 497 L 352 496 L 352 491 L 353 490 L 355 490 L 356 491 L 356 493 L 354 493 L 354 492 L S N 369 496 M 370 497 L 370 490 L 369 490 L 371 490 L S N 378 490 M 379 490 L S N 386 490 M 385 491 L 385 496 L 386 497 L 387 497 L 388 496 L 388 491 L 387 490 L 386 490 L S N 401 490 M 400 491 L 400 496 L 401 497 L 403 497 L 404 496 L 404 491 L 403 490 L 401 490 L S N 408 490 M 408 497 L 408 493 L 412 493 L 412 490 L 412 497 L S N 416 490 M 416 497 L 418 493 L 420 497 L 420 490 L S N 428 496 M 427 497 L 425 497 L 424 496 L 424 494 L 425 493 L 427 493 L 428 492 L 428 491 L 427 490 L 425 490 L 424 491 L S N 444 496 M 443 497 L 441 497 L 440 496 L 440 494 L 441 493 L 443 493 L 444 492 L 444 491 L 443 490 L 441 490 L 440 491 L S N 448 497 M 448 491 L 449 490 L 451 490 L 452 491 L 452 497 L S N 456 490 M 456 497 L 459 497 L 460 496 L 460 494 L 459 493 L 456 493 L 459 493 L 460 492 L 460 491 L 459 490 L 456 490 L S N 468 496 M 467 497 L 465 497 L 464 496 L 464 494 L 465 493 L 467 493 L 468 492 L 468 491 L 467 490 L 465 490 L 464 491 L S N 474 490 M 474 497 L 472 497 L 476 497 L S N 480 490 M 480 497 L 483 497 L 484 496 L 484 494 L 483 493 L 480 493 L 482 493 L 484 490 L S N 488 490 M 488 493 L 489 497 L 491 497 L 492 493 L 492 490 L S N 488 492 M 492 492 L S N 498 490 M 498 497 L 496 497 L 500 497 L S N 508 490 M 504 490 L 504 497 L 508 497 L S N 504 493 M 506 493 L S N 520 490 M 520 497 L 523 497 L 524 496 L 524 494 L 523 493 L 520 493 L 522 493 L 524 490 L S N 532 490 M 528 490 L 528 497 L 532 497 L S N 528 493 M 530 493 L S N 540 496 M 539 497 L 537 497 L 536 496 L 536 494 L 537 493 L 539 493 L 540 492 L 540 491 L 539 490 L 537 490 L 536 491 L S N 545 490 M 547 490 L 546 490 L 546 497 L 545 497 L 547 497 L S N 556 496 M 555 497 L 553 497 L 552 496 L 552 494 L 553 493 L 555 493 L 556 492 L 556 491 L 555 490 L 553 490 L 552 491 L S N 562 490 M 562 497 L 560 497 L 564 497 L S N 568 490 M 568 493 L 569 497 L 571 497 L 572 493 L 572 490 L S N 568 492 M 572 492 L S N 576 490 M 576 497 L 580 490 L 580 497 L S N 588 491 M 587 490 L 585 490 L 584 491 L 584 496 L 585 497 L 587 497 L 588 496 L S N 596 490 M 592 490 L 592 497 L 596 497 L S N 592 493 M 594 493 L S N 273 487 M 272 483 L 276 483 L S N 275 487 M 275 480 L S N 281 483 M 283 483 L S N 288 480 M 288 483 L 289 487 L 291 487 L 292 483 L 292 480 L S N 288 482 M 292 482 L S N 296 480 M 296 487 L 299 487 L 300 486 L 300 484 L 299 483 L 296 483 L S N 304 480 M 304 487 L 307 487 L 308 486 L 308 484 L 307 483 L 304 483 L 306 483 L 308 480 L S N 312 481 M 313 480 L 315 480 L 316 481 L 316 486 L 315 487 L 313 487 L 312 486 L 312 484 L 313 483 L 315 483 L 316 484 L S N 321 487 M 320 483 L 324 483 L S N 323 487 M 323 480 L S N 337 486 M 338 487 L 338 480 L 337 480 L 339 480 L S N 344 481 M 345 480 L 347 480 L 348 481 L 348 486 L 347 487 L 345 487 L 344 486 L 344 484 L 345 483 L 347 483 L 348 484 L S N 354 481 M 354 482 L S N 354 484 M 354 486 L S N 361 487 M 360 483 L 364 483 L S N 363 487 M 363 480 L S N 369 483 M 368 484 L 368 486 L 369 487 L 371 487 L 372 486 L 372 484 L 371 483 L 369 483 L 368 482 L 368 481 L 369 480 L 371 480 L 372 481 L 372 482 L 371 483 L S N 378 481 M 378 482 L S N 378 484 M 378 486 L S N 388 487 M 384 487 L 384 483 L 385 484 L 387 484 L 388 483 L 388 481 L 387 480 L 385 480 L 384 481 L S N 392 481 M 393 480 L 395 480 L 396 481 L 396 486 L 395 487 L 393 487 L 392 486 L 392 484 L 393 483 L 395 483 L 396 484 L S N [] 0 D 98 40 M 97 41 L 97 46 L 98 47 L 99 47 L 100 46 L 100 41 L 99 40 L 98 40 L S N 106 40 M 107 40 L S N 536 46 M 537 47 L 537 40 L 536 40 L 538 40 L S N 545 40 M 544 41 L 544 46 L 545 47 L 546 47 L 547 46 L 547 41 L 546 40 L 545 40 L S N 553 40 M 552 41 L 552 46 L 553 47 L 554 47 L 555 46 L 555 41 L 554 40 L 553 40 L S N 561 40 M 562 40 L S N 569 40 M 568 41 L 568 46 L 569 47 L 570 47 L 571 46 L 571 41 L 570 40 L 569 40 L S N 575 40 M 575 47 L 577 43 L 579 47 L 579 40 L S N 290 40 M 290 47 L 288 47 L 292 47 L S N 297 40 M 299 40 L 298 40 L 298 47 L 297 47 L 299 47 L S N 304 40 M 304 47 L 306 43 L 308 47 L 308 40 L S N 316 40 M 312 40 L 312 47 L 316 47 L S N 312 43 M 314 43 L S N 331 47 M 330 47 L 329 46 L 329 41 L 330 40 L 331 40 L S N 336 47 M 336 40 L 340 40 L S N 345 40 M 347 40 L 346 40 L 346 47 L 345 47 L 347 47 L S N 352 40 M 352 47 L 356 40 L 356 47 L S N 361 47 M 362 47 L 363 46 L 363 41 L 362 40 L 361 40 L S N [] 0 D 127 60 M 127 64 L S N 150 60 M 150 64 L S N 173 60 M 173 64 L S N 196 60 M 196 64 L S N [] 0 D 188 56 M 189 57 L 191 57 L 192 56 L 192 54 L 191 53 L 189 53 L 188 52 L 188 50 L 192 50 L S N 198 50 M 197 51 L 197 56 L 198 57 L 199 57 L 200 56 L 200 51 L 199 50 L 198 50 L S N 206 50 M 207 50 L S N 214 50 M 213 51 L 213 56 L 214 57 L 215 57 L 216 56 L 216 51 L 215 50 L 214 50 L S N 220 50 M 220 57 L 222 53 L 224 57 L 224 50 L S N [.5 4] 0 D 196 469 M 196 60 L S N [] 0 D 196 60 M 196 68 L S N 219 60 M 219 64 L S N 242 60 M 242 64 L S N 266 60 M 266 64 L S N 289 60 M 289 64 L S N [] 0 D 282 57 M 281 53 L 285 53 L S N 284 57 M 284 50 L S N 291 50 M 290 51 L 290 56 L 291 57 L 292 57 L 293 56 L 293 51 L 292 50 L 291 50 L S N 299 50 M 300 50 L S N 307 50 M 306 51 L 306 56 L 307 57 L 308 57 L 309 56 L 309 51 L 308 50 L 307 50 L S N 313 50 M 313 57 L 315 53 L 317 57 L 317 50 L S N [.5 4] 0 D 289 469 M 289 60 L S N [] 0 D 289 60 M 289 68 L S N 312 60 M 312 64 L S N 335 60 M 335 64 L S N 358 60 M 358 64 L S N 381 60 M 381 64 L S N [] 0 D 377 56 M 376 57 L 374 57 L 373 56 L 373 51 L 374 50 L 376 50 L 377 51 L 377 52 L 376 53 L 374 53 L 373 52 L S N 383 50 M 382 51 L 382 56 L 383 57 L 384 57 L 385 56 L 385 51 L 384 50 L 383 50 L S N 391 50 M 392 50 L S N 399 50 M 398 51 L 398 56 L 399 57 L 400 57 L 401 56 L 401 51 L 400 50 L 399 50 L S N 405 50 M 405 57 L 407 53 L 409 57 L 409 50 L S N [.5 4] 0 D 381 469 M 381 60 L S N [] 0 D 381 60 M 381 68 L S N 404 60 M 404 64 L S N 428 60 M 428 64 L S N 451 60 M 451 64 L S N 474 60 M 474 64 L S N [] 0 D 467 53 M 466 54 L 466 56 L 467 57 L 469 57 L 470 56 L 470 54 L 469 53 L 467 53 L 466 52 L 466 51 L 467 50 L 469 50 L 470 51 L 470 52 L 469 53 L S N 476 50 M 475 51 L 475 56 L 476 57 L 477 57 L 478 56 L 478 51 L 477 50 L 476 50 L S N 484 50 M 485 50 L S N 492 50 M 491 51 L 491 56 L 492 57 L 493 57 L 494 56 L 494 51 L 493 50 L 492 50 L S N 498 50 M 498 57 L 500 53 L 502 57 L 502 50 L S N [.5 4] 0 D 474 469 M 474 60 L S N [] 0 D 474 60 M 474 68 L S N 497 60 M 497 64 L S N 520 60 M 520 64 L S N 543 60 M 543 64 L S N 567 60 M 567 64 L S N [] 0 D 560 56 M 561 57 L 561 50 L 560 50 L 562 50 L S N 569 50 M 568 51 L 568 56 L 569 57 L 570 57 L 571 56 L 571 51 L 570 50 L 569 50 L S N 577 50 M 576 51 L 576 56 L 577 57 L 578 57 L 579 56 L 579 51 L 578 50 L 577 50 L S N 585 50 M 586 50 L S N 593 50 M 592 51 L 592 56 L 593 57 L 594 57 L 595 56 L 595 51 L 594 50 L 593 50 L S N 599 50 M 599 57 L 601 53 L 603 57 L 603 50 L S N [.5 4] 0 D 567 469 M 567 60 L S N [] 0 D 567 60 M 567 68 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 16 310 M 16 313 L 17 317 L 19 317 L 20 313 L 20 310 L S N 16 312 M 20 312 L S N 16 300 M 16 307 L 18 303 L 20 307 L 20 300 L S N 16 290 M 16 297 L 19 297 L 20 296 L 20 294 L 19 293 L 16 293 L S N 16 277 M 16 270 L 20 270 L S N 17 260 M 19 260 L 18 260 L 18 267 L 17 267 L 19 267 L S N 16 250 M 16 257 L 20 250 L 20 257 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N [] 0 D 69 57 M 71 57 L S N 76 60 M 77 61 L 79 61 L 80 60 L 80 58 L 79 57 L 77 57 L 76 56 L 76 54 L 80 54 L S N 86 54 M 87 54 L S N 94 54 M 93 55 L 93 60 L 94 61 L 95 61 L 96 60 L 96 55 L 95 54 L 94 54 L S N [.5 4] 0 D 567 60 M 104 60 L S N [] 0 D 104 60 M 112 60 L S N 104 68 M 108 68 L S N 104 76 M 108 76 L S N 104 84 M 108 84 L S N 104 92 M 108 92 L S N [] 0 D 61 89 M 63 89 L S N 69 92 M 70 93 L 70 86 L 69 86 L 71 86 L S N 78 86 M 79 86 L S N 85 89 M 84 90 L 84 92 L 85 93 L 87 93 L 88 92 L 88 90 L 87 89 L 85 89 L 84 88 L 84 87 L 85 86 L 87 86 L 88 87 L 88 88 L 87 89 L S N 94 86 M 93 87 L 93 92 L 94 93 L 95 93 L 96 92 L 96 87 L 95 86 L 94 86 L S N [.5 4] 0 D 567 92 M 104 92 L S N [] 0 D 104 92 M 112 92 L S N 104 100 M 108 100 L S N 104 109 M 108 109 L S N 104 117 M 108 117 L S N 104 125 M 108 125 L S N [] 0 D 61 122 M 63 122 L S N 69 125 M 70 126 L 70 119 L 69 119 L 71 119 L S N 78 119 M 79 119 L S N 88 125 M 87 126 L 85 126 L 84 125 L 84 120 L 85 119 L 87 119 L 88 120 L 88 121 L 87 122 L 85 122 L 84 121 L S N 94 119 M 93 120 L 93 125 L 94 126 L 95 126 L 96 125 L 96 120 L 95 119 L 94 119 L S N [.5 4] 0 D 567 125 M 104 125 L S N [] 0 D 104 125 M 112 125 L S N 104 133 M 108 133 L S N 104 141 M 108 141 L S N 104 149 M 108 149 L S N 104 158 M 108 158 L S N [] 0 D 61 155 M 63 155 L S N 69 158 M 70 159 L 70 152 L 69 152 L 71 152 L S N 78 152 M 79 152 L S N 85 159 M 84 155 L 88 155 L S N 87 159 M 87 152 L S N 94 152 M 93 153 L 93 158 L 94 159 L 95 159 L 96 158 L 96 153 L 95 152 L 94 152 L S N [.5 4] 0 D 567 158 M 104 158 L S N [] 0 D 104 158 M 112 158 L S N 104 166 M 108 166 L S N 104 174 M 108 174 L S N 104 182 M 108 182 L S N 104 190 M 108 190 L S N [] 0 D 61 187 M 63 187 L S N 69 190 M 70 191 L 70 184 L 69 184 L 71 184 L S N 78 184 M 79 184 L S N 84 190 M 85 191 L 87 191 L 88 190 L 88 188 L 87 187 L 85 187 L 84 186 L 84 184 L 88 184 L S N 94 184 M 93 185 L 93 190 L 94 191 L 95 191 L 96 190 L 96 185 L 95 184 L 94 184 L S N [.5 4] 0 D 567 190 M 104 190 L S N [] 0 D 104 190 M 112 190 L S N 104 199 M 108 199 L S N 104 207 M 108 207 L S N 104 215 M 108 215 L S N 104 223 M 108 223 L S N [] 0 D 69 220 M 71 220 L S N 77 223 M 78 224 L 78 217 L 77 217 L 79 217 L S N 86 217 M 87 217 L S N 94 217 M 93 218 L 93 223 L 94 224 L 95 224 L 96 223 L 96 218 L 95 217 L 94 217 L S N [.5 4] 0 D 567 223 M 104 223 L S N [] 0 D 104 223 M 112 223 L S N 104 231 M 108 231 L S N 104 239 M 108 239 L S N 104 248 M 108 248 L S N 104 256 M 108 256 L S N [] 0 D 45 253 M 47 253 L S N 53 253 M 52 254 L 52 256 L 53 257 L 55 257 L 56 256 L 56 254 L 55 253 L 53 253 L 52 252 L 52 251 L 53 250 L 55 250 L 56 251 L 56 252 L 55 253 L S N 62 250 M 61 251 L 61 256 L 62 257 L 63 257 L 64 256 L 64 251 L 63 250 L 62 250 L S N 70 250 M 69 251 L 69 256 L 70 257 L 71 257 L 72 256 L 72 251 L 71 250 L 70 250 L S N 78 250 M 79 250 L S N 86 250 M 85 251 L 85 256 L 86 257 L 87 257 L 88 256 L 88 251 L 87 250 L 86 250 L S N 92 250 M 92 257 L 94 253 L 96 257 L 96 250 L S N [.5 4] 0 D 567 256 M 104 256 L S N [] 0 D 104 256 M 112 256 L S N 104 264 M 108 264 L S N 104 272 M 108 272 L S N 104 280 M 108 280 L S N 104 289 M 108 289 L S N [] 0 D 45 286 M 47 286 L S N 56 289 M 55 290 L 53 290 L 52 289 L 52 284 L 53 283 L 55 283 L 56 284 L 56 285 L 55 286 L 53 286 L 52 285 L S N 62 283 M 61 284 L 61 289 L 62 290 L 63 290 L 64 289 L 64 284 L 63 283 L 62 283 L S N 70 283 M 69 284 L 69 289 L 70 290 L 71 290 L 72 289 L 72 284 L 71 283 L 70 283 L S N 78 283 M 79 283 L S N 86 283 M 85 284 L 85 289 L 86 290 L 87 290 L 88 289 L 88 284 L 87 283 L 86 283 L S N 92 283 M 92 290 L 94 286 L 96 290 L 96 283 L S N [.5 4] 0 D 567 289 M 104 289 L S N [] 0 D 104 289 M 112 289 L S N 104 297 M 108 297 L S N 104 305 M 108 305 L S N 104 313 M 108 313 L S N 104 321 M 108 321 L S N [] 0 D 45 318 M 47 318 L S N 53 322 M 52 318 L 56 318 L S N 55 322 M 55 315 L S N 62 315 M 61 316 L 61 321 L 62 322 L 63 322 L 64 321 L 64 316 L 63 315 L 62 315 L S N 70 315 M 69 316 L 69 321 L 70 322 L 71 322 L 72 321 L 72 316 L 71 315 L 70 315 L S N 78 315 M 79 315 L S N 86 315 M 85 316 L 85 321 L 86 322 L 87 322 L 88 321 L 88 316 L 87 315 L 86 315 L S N 92 315 M 92 322 L 94 318 L 96 322 L 96 315 L S N [.5 4] 0 D 567 321 M 104 321 L S N [] 0 D 104 321 M 112 321 L S N 104 329 M 108 329 L S N 104 338 M 108 338 L S N 104 346 M 108 346 L S N 104 354 M 108 354 L S N [] 0 D 45 351 M 47 351 L S N 52 354 M 53 355 L 55 355 L 56 354 L 56 352 L 55 351 L 53 351 L 52 350 L 52 348 L 56 348 L S N 62 348 M 61 349 L 61 354 L 62 355 L 63 355 L 64 354 L 64 349 L 63 348 L 62 348 L S N 70 348 M 69 349 L 69 354 L 70 355 L 71 355 L 72 354 L 72 349 L 71 348 L 70 348 L S N 78 348 M 79 348 L S N 86 348 M 85 349 L 85 354 L 86 355 L 87 355 L 88 354 L 88 349 L 87 348 L 86 348 L S N 92 348 M 92 355 L 94 351 L 96 355 L 96 348 L S N [.5 4] 0 D 567 354 M 104 354 L S N [] 0 D 104 354 M 112 354 L S N 104 362 M 108 362 L S N 104 370 M 108 370 L S N 104 379 M 108 379 L S N 104 387 M 108 387 L S N [] 0 D 86 381 M 85 382 L 85 387 L 86 388 L 87 388 L 88 387 L 88 382 L 87 381 L 86 381 L S N 94 381 M 95 381 L S N [.5 4] 0 D 567 387 M 104 387 L S N [] 0 D 104 387 M 112 387 L S N 104 395 M 108 395 L S N 104 403 M 108 403 L S N 104 411 M 108 411 L S N 104 419 M 108 419 L S N [] 0 D 52 419 M 53 420 L 55 420 L 56 419 L 56 417 L 55 416 L 53 416 L 52 415 L 52 413 L 56 413 L S N 62 413 M 61 414 L 61 419 L 62 420 L 63 420 L 64 419 L 64 414 L 63 413 L 62 413 L S N 70 413 M 69 414 L 69 419 L 70 420 L 71 420 L 72 419 L 72 414 L 71 413 L 70 413 L S N 78 413 M 79 413 L S N 86 413 M 85 414 L 85 419 L 86 420 L 87 420 L 88 419 L 88 414 L 87 413 L 86 413 L S N 92 413 M 92 420 L 94 416 L 96 420 L 96 413 L S N [.5 4] 0 D 567 419 M 104 419 L S N [] 0 D 104 419 M 112 419 L S N 104 428 M 108 428 L S N 104 436 M 108 436 L S N 104 444 M 108 444 L S N 104 452 M 108 452 L S N [] 0 D 53 453 M 52 449 L 56 449 L S N 55 453 M 55 446 L S N 62 446 M 61 447 L 61 452 L 62 453 L 63 453 L 64 452 L 64 447 L 63 446 L 62 446 L S N 70 446 M 69 447 L 69 452 L 70 453 L 71 453 L 72 452 L 72 447 L 71 446 L 70 446 L S N 78 446 M 79 446 L S N 86 446 M 85 447 L 85 452 L 86 453 L 87 453 L 88 452 L 88 447 L 87 446 L 86 446 L S N 92 446 M 92 453 L 94 449 L 96 453 L 96 446 L S N [.5 4] 0 D 567 452 M 104 452 L S N [] 0 D 104 452 M 112 452 L S N 104 460 M 108 460 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 559 60 L S N 567 68 M 563 68 L S N 567 76 M 563 76 L S N 567 84 M 563 84 L S N 567 92 M 563 92 L S N 567 92 M 559 92 L S N 567 100 M 563 100 L S N 567 109 M 563 109 L S N 567 117 M 563 117 L S N 567 125 M 563 125 L S N 567 125 M 559 125 L S N 567 133 M 563 133 L S N 567 141 M 563 141 L S N 567 149 M 563 149 L S N 567 158 M 563 158 L S N 567 158 M 559 158 L S N 567 166 M 563 166 L S N 567 174 M 563 174 L S N 567 182 M 563 182 L S N 567 190 M 563 190 L S N 567 190 M 559 190 L S N 567 199 M 563 199 L S N 567 207 M 563 207 L S N 567 215 M 563 215 L S N 567 223 M 563 223 L S N 567 223 M 559 223 L S N 567 231 M 563 231 L S N 567 239 M 563 239 L S N 567 248 M 563 248 L S N 567 256 M 563 256 L S N 567 256 M 559 256 L S N 567 264 M 563 264 L S N 567 272 M 563 272 L S N 567 280 M 563 280 L S N 567 289 M 563 289 L S N 567 289 M 559 289 L S N 567 297 M 563 297 L S N 567 305 M 563 305 L S N 567 313 M 563 313 L S N 567 321 M 563 321 L S N 567 321 M 559 321 L S N 567 329 M 563 329 L S N 567 338 M 563 338 L S N 567 346 M 563 346 L S N 567 354 M 563 354 L S N 567 354 M 559 354 L S N 567 362 M 563 362 L S N 567 370 M 563 370 L S N 567 379 M 563 379 L S N 567 387 M 563 387 L S N 567 387 M 559 387 L S N 567 395 M 563 395 L S N 567 403 M 563 403 L S N 567 411 M 563 411 L S N 567 419 M 563 419 L S N 567 419 M 559 419 L S N 567 428 M 563 428 L S N 567 436 M 563 436 L S N 567 444 M 563 444 L S N 567 452 M 563 452 L S N 567 452 M 559 452 L S N 567 460 M 563 460 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 584 467 M 588 460 L S N 584 460 M 588 467 L S N 592 467 M 596 460 L S N 592 460 M 596 467 L S N 600 467 M 604 460 L S N 600 460 M 604 467 L S N 608 467 M 612 460 L S N 608 460 M 612 467 L S N 618 460 M 619 460 L S N 626 460 M 626 467 L 624 467 L 628 467 L S N 632 460 M 632 467 L 635 467 L 636 466 L 636 464 L 635 463 L 632 463 L 634 463 L 636 460 L S N 642 460 M 641 461 L 641 466 L 642 467 L 643 467 L 644 466 L 644 461 L 643 460 L 642 460 L S N 585 450 M 587 450 L 586 450 L 586 457 L 585 457 L 587 457 L S N 595 457 M 594 457 L 593 456 L 593 451 L 594 450 L 595 450 L S N 600 457 M 602 450 L 604 457 L S N 608 450 M 608 457 L 611 457 L 612 456 L 612 451 L 611 450 L 608 450 L S N 616 456 M 617 457 L 619 457 L 620 456 L 620 454 L 619 453 L 617 453 L 616 452 L 616 450 L 620 450 L S N 576 441 M 580 448 L 583 441 L 576 441 L S N 580 445 M 663 445 L S N 174 60 M 175 63 L 175 66 L 176 68 L 176 71 L 177 73 L 177 76 L 178 79 L 178 81 L 179 84 L 179 87 L 179 89 L 180 92 L 180 95 L 181 97 L 181 100 L 182 102 L 182 105 L 183 108 L 183 110 L 184 113 L 184 115 L 185 118 L 185 121 L 185 123 L 186 126 L 186 129 L 187 131 L 187 134 L 188 136 L 188 139 L 189 142 L 189 144 L 190 147 L 190 149 L 191 152 L 191 155 L 191 157 L 192 160 L 192 162 L 193 165 L 193 168 L 194 170 L 194 173 L 195 175 L 195 178 L 196 181 L 196 183 L 197 186 L 197 188 L 197 191 L 198 194 L 198 196 L 199 199 L 199 201 L 200 204 L 200 206 L 201 209 L 201 212 L 202 214 L 202 217 L 203 219 L 203 222 L 204 224 L 204 227 L 204 230 L 205 232 L 205 235 L 206 237 L 206 240 L 207 242 L 207 245 L 208 247 L 208 250 L 209 252 L 209 255 L 210 258 L 210 260 L 210 263 L 211 265 L 211 268 L 212 270 L 212 273 L 213 275 L 213 278 L 214 280 L 214 283 L 215 285 L 215 288 L 216 290 L 216 293 L 216 295 L 217 298 L 217 300 L 218 303 L 218 305 L 219 308 L 219 310 L 220 313 L 220 315 L 221 317 L 221 320 L 222 322 L 222 325 L 222 327 L 223 330 L 223 332 L 224 334 L 224 337 L 225 339 L 225 341 L 226 344 L 226 346 L 227 348 L 227 351 L 228 353 L 228 355 L 229 357 L 229 360 L 229 362 L 230 364 L 230 366 L 231 368 L 231 370 L 232 372 L 232 374 L 233 376 L 233 378 L 234 379 L 234 381 L 235 382 L 235 383 L 235 384 L 236 385 L 236 386 L 237 386 L 238 386 L 239 387 L 240 387 L 241 387 L 242 387 L 243 387 L 244 387 L 245 387 L 246 387 L 247 387 L 248 387 L 249 387 L 250 387 L 251 387 L 252 387 L 253 387 L 254 387 L 255 387 L 256 387 L 257 387 L 258 387 L 259 387 L 260 387 L 261 387 L 262 387 L 263 387 L 264 387 L 265 387 L 266 387 L 267 387 L 268 387 L 269 387 L 270 387 L 271 387 L 272 387 L 273 387 L 274 387 L 275 387 L 276 387 L 277 387 L 278 387 L 279 387 L 280 387 L 281 387 L 282 387 L 283 387 L 284 387 L 285 387 L 286 387 L 287 387 L 288 387 L 289 387 L 290 387 L 291 387 L 292 387 L 293 387 L 294 387 L 295 387 L 296 387 L 297 387 L 298 387 L 299 387 L 300 387 L 301 387 L 302 387 L S N 302 387 M 303 387 L 304 387 L 305 387 L 306 387 L 307 387 L 308 387 L 309 387 L 310 387 L 311 387 L 312 387 L 313 387 L 314 387 L 315 387 L 316 387 L 317 387 L 318 387 L 319 387 L 320 387 L 321 387 L 322 387 L 323 387 L 324 387 L 325 387 L 326 387 L 327 387 L 328 387 L 329 387 L 330 387 L 331 387 L 332 387 L 333 387 L 334 387 L 335 387 L 336 387 L 337 387 L 338 387 L 339 387 L 340 387 L 341 387 L 342 387 L 343 387 L 344 387 L 345 387 L 346 387 L 347 387 L 348 387 L 349 387 L 350 387 L 351 387 L 352 387 L 353 387 L 354 387 L 355 387 L 356 387 L 357 387 L 358 387 L 359 387 L 360 387 L 361 387 L 362 387 L 363 387 L 364 387 L 365 387 L 366 387 L 367 387 L 368 387 L 369 387 L 370 387 L 371 387 L 372 387 L 373 387 L 374 387 L 375 387 L 376 387 L 377 387 L 378 387 L 379 387 L 380 387 L 381 387 L 382 387 L 383 387 L 384 387 L 385 387 L 386 387 L 387 387 L 388 387 L 389 387 L 390 387 L 391 387 L 392 387 L 393 387 L 394 387 L 395 387 L 396 387 L 397 387 L 398 387 L 399 387 L 400 387 L 401 387 L 402 387 L 403 387 L 404 387 L 405 387 L 406 387 L 407 387 L 408 387 L 409 387 L 410 387 L 411 387 L 412 387 L 413 387 L 414 387 L 415 387 L 416 387 L 417 387 L 418 387 L 419 387 L 420 387 L 421 387 L 422 387 L 423 387 L 424 387 L 425 387 L 426 387 L 427 387 L 428 387 L 429 387 L 430 387 L 431 387 L 432 387 L 433 387 L 434 387 L 435 387 L 436 387 L 437 387 L 438 387 L 439 387 L 440 387 L 441 387 L 442 387 L 443 387 L 444 387 L 445 387 L 446 387 L 447 387 L 448 387 L 449 387 L 450 387 L 451 387 L 452 387 L 453 387 L 454 387 L 455 387 L 456 387 L 457 387 L 458 387 L 459 387 L 460 387 L 461 387 L 462 387 L 463 387 L 464 387 L 465 387 L 466 387 L 467 387 L 468 387 L 469 387 L 470 387 L 471 387 L 472 387 L 473 387 L 474 387 L 475 387 L 476 387 L 477 387 L 478 387 L 479 387 L 480 387 L 481 387 L 482 387 L 483 387 L 484 387 L 485 387 L 486 387 L 487 387 L 488 387 L 489 387 L 490 387 L 491 387 L 492 387 L 493 387 L 494 387 L 495 387 L 496 387 L 497 387 L 498 387 L 499 387 L 500 387 L 501 387 L 502 387 L S N 502 387 M 503 387 L 504 387 L 505 387 L 506 387 L 507 387 L 508 387 L 509 387 L 510 387 L 511 387 L 512 387 L 513 387 L 514 387 L 515 387 L 516 387 L 517 387 L 518 387 L 519 387 L 520 387 L 521 387 L 522 387 L 523 387 L 524 387 L 525 387 L 526 387 L 527 387 L 528 387 L 529 387 L 530 387 L 531 387 L 532 387 L 533 387 L 534 387 L 535 387 L 536 387 L 537 387 L 538 387 L 539 387 L 540 387 L 541 387 L 542 387 L 543 387 L 544 387 L 545 387 L 546 387 L 547 387 L 548 387 L 549 387 L 550 387 L 551 387 L 552 387 L 553 387 L 554 387 L 555 387 L 556 387 L 557 387 L 558 387 L 559 387 L 560 387 L 561 387 L 562 387 L 563 387 L 564 387 L 565 387 L S N 565 387 M 566 387 L 567 387 L S N 563 383 M 567 390 L 570 383 L 563 383 L S N 585 430 M 587 430 L 586 430 L 586 437 L 585 437 L 587 437 L S N 595 437 M 594 437 L 593 436 L 593 431 L 594 430 L 595 430 L S N 600 437 M 602 430 L 604 437 L S N 612 436 M 611 437 L 609 437 L 608 436 L 608 434 L 609 433 L 611 433 L 612 432 L 612 431 L 611 430 L 609 430 L 608 431 L S N 616 436 M 617 437 L 619 437 L 620 436 L 620 434 L 619 433 L 617 433 L 616 432 L 616 430 L 620 430 L S N 576 421 M 576 428 L 583 428 L 583 421 L 576 421 L S N [15 3] 0 D 580 425 M 663 425 L S N 104 329 M 104 330 L 105 330 L 106 331 L 107 331 L 108 332 L 109 332 L 110 333 L 111 333 L 111 334 L 112 334 L 113 334 L 114 335 L 115 335 L 116 336 L 117 336 L 117 337 L 118 337 L 119 337 L 119 338 L 120 338 L 121 338 L 121 339 L 122 339 L 123 340 L 124 340 L 125 340 L 125 341 L 126 341 L 127 341 L 127 342 L 128 342 L 129 342 L 129 343 L 130 343 L 131 344 L 132 344 L 133 345 L 134 345 L 135 345 L 135 346 L 136 346 L 137 347 L 138 347 L 139 348 L 140 348 L 141 348 L 141 349 L 142 349 L 143 350 L 144 350 L 145 351 L 146 351 L 147 351 L 147 352 L 148 352 L 149 353 L 150 353 L 151 354 L 152 354 L 153 354 L 153 355 L 154 355 L 155 356 L 156 356 L 157 356 L 157 357 L 158 357 L 159 357 L 159 358 L 160 358 L 161 358 L 161 359 L 162 359 L 163 359 L 163 360 L 164 360 L 165 360 L 166 361 L 167 361 L 167 362 L 168 362 L 169 362 L 170 363 L 171 363 L 172 363 L 172 364 L 173 364 L 174 365 L 175 365 L 176 365 L 176 366 L 177 366 L 178 366 L 179 367 L 180 367 L 181 368 L 182 368 L 183 369 L 184 369 L 185 369 L 185 370 L 186 370 L 187 370 L 187 371 L 188 371 L 189 371 L 190 372 L 191 372 L 192 373 L 193 373 L 194 373 L 195 374 L 196 374 L 197 374 L 197 375 L 198 375 L 199 375 L 199 376 L 200 376 L 201 376 L 202 376 L 202 377 L 203 377 L 204 377 L 205 378 L 206 378 L 207 378 L 207 379 L 208 379 L 209 379 L 210 379 L 210 380 L 211 380 L 212 380 L 213 380 L 213 381 L 214 381 L 215 381 L 216 381 L 216 382 L 217 382 L 218 382 L 219 382 L 219 383 L 220 383 L 221 383 L 222 383 L 223 384 L 224 384 L 225 384 L 226 384 L 227 385 L 228 385 L 229 385 L 230 385 L 231 385 L 232 386 L 233 386 L 234 386 L 235 386 L 236 386 L 237 386 L 238 386 L 238 387 L 239 387 L 240 387 L 241 387 L 242 387 L 243 387 L 244 387 L 245 387 L 246 387 L 247 387 L 248 387 L 249 387 L 250 387 L 251 387 L 252 387 L 253 387 L 254 387 L 255 387 L 256 387 L 257 387 L 258 387 L 259 387 L 260 387 L 261 387 L 262 387 L 263 387 L 264 387 L 265 387 L 266 387 L 267 387 L 268 387 L 269 387 L 270 387 L 271 387 L 272 387 L 273 387 L 274 387 L S N 274 387 M 275 387 L 276 387 L 277 387 L 278 387 L 279 387 L 280 387 L 281 387 L 282 387 L 283 387 L 284 387 L 285 387 L 286 387 L 287 387 L 288 387 L 289 387 L 290 387 L 291 387 L 292 387 L 293 387 L 294 387 L 295 387 L 296 387 L 297 387 L 298 387 L 299 387 L 300 387 L 301 387 L 302 387 L 303 387 L 304 387 L 305 387 L 306 387 L 307 387 L 308 387 L 309 387 L 310 387 L 311 387 L 312 387 L 313 387 L 314 387 L 315 387 L 316 387 L 317 387 L 318 387 L 319 387 L 320 387 L 321 387 L 322 387 L 323 387 L 324 387 L 325 387 L 326 387 L 327 387 L 328 387 L 329 387 L 330 387 L 331 387 L 332 387 L 333 387 L 334 387 L 335 387 L 336 387 L 337 387 L 338 387 L 339 387 L 340 387 L 341 387 L 342 387 L 343 387 L 344 387 L 345 387 L 346 387 L 347 387 L 348 387 L 349 387 L 350 387 L 351 387 L 352 387 L 353 387 L 354 387 L 355 387 L 356 387 L 357 387 L 358 387 L 359 387 L 360 387 L 361 387 L 362 387 L 363 387 L 364 387 L 365 387 L 366 387 L 367 387 L 368 387 L 369 387 L 370 387 L 371 387 L 372 387 L 373 387 L 374 387 L 375 387 L 376 387 L 377 387 L 378 387 L 379 387 L 380 387 L 381 387 L 382 387 L 383 387 L 384 387 L 385 387 L 386 387 L 387 387 L 388 387 L 389 387 L 390 387 L 391 387 L 392 387 L 393 387 L 394 387 L 395 387 L 396 387 L 397 387 L 398 387 L 399 387 L 400 387 L 401 387 L 402 387 L 403 387 L 404 387 L 405 387 L 406 387 L 407 387 L 408 387 L 409 387 L 410 387 L 411 387 L 412 387 L 413 387 L 414 387 L 415 387 L 416 387 L 417 387 L 418 387 L 419 387 L 420 387 L 421 387 L 422 387 L 423 387 L 424 387 L 425 387 L 426 387 L 427 387 L 428 387 L 429 387 L 430 387 L 431 387 L 432 387 L 433 387 L 434 387 L 435 387 L 436 387 L 437 387 L 438 387 L 439 387 L 440 387 L 441 387 L 442 387 L 443 387 L 444 387 L 445 387 L 446 387 L 447 387 L 448 387 L 449 387 L 450 387 L 451 387 L 452 387 L 453 387 L 454 387 L 455 387 L 456 387 L 457 387 L 458 387 L 459 387 L 460 387 L 461 387 L 462 387 L 463 387 L 464 387 L 465 387 L 466 387 L 467 387 L 468 387 L 469 387 L 470 387 L 471 387 L 472 387 L 473 387 L 474 387 L S N 474 387 M 475 387 L 476 387 L 477 387 L 478 387 L 479 387 L 480 387 L 481 387 L 482 387 L 483 387 L 484 387 L 485 387 L 486 387 L 487 387 L 488 387 L 489 387 L 490 387 L 491 387 L 492 387 L 493 387 L 494 387 L 495 387 L 496 387 L 497 387 L 498 387 L 499 387 L 500 387 L 501 387 L 502 387 L 503 387 L 504 387 L 505 387 L 506 387 L 507 387 L 508 387 L 509 387 L 510 387 L 511 387 L 512 387 L 513 387 L 514 387 L 515 387 L 516 387 L 517 387 L 518 387 L 519 387 L 520 387 L 521 387 L 522 387 L 523 387 L 524 387 L 525 387 L 526 387 L 527 387 L 528 387 L 529 387 L 530 387 L 531 387 L 532 387 L 533 387 L 534 387 L 535 387 L 536 387 L 537 387 L 538 387 L 539 387 L 540 387 L 541 387 L 542 387 L 543 387 L 544 387 L 545 387 L 546 387 L 547 387 L 548 387 L 549 387 L 550 387 L 551 387 L 552 387 L 553 387 L 554 387 L 555 387 L 556 387 L 557 387 L 558 387 L 559 387 L 560 387 L 561 387 L 562 387 L 563 387 L 564 387 L 565 387 L S N 565 387 M 566 387 L 567 387 L S N [] 0 D 563 383 M 563 390 L 570 390 L 570 383 L 563 383 L S N 585 410 M 587 410 L 586 410 L 586 417 L 585 417 L 587 417 L S N 595 417 M 594 417 L 593 416 L 593 411 L 594 410 L 595 410 L S N 600 417 M 602 410 L 604 417 L S N 608 410 M 608 417 L 611 417 L 612 416 L 612 414 L 611 413 L 608 413 L 611 413 L 612 412 L 612 411 L 611 410 L 608 410 L S N 616 416 M 617 417 L 619 417 L 620 416 L 620 414 L 619 413 L 617 413 L 616 412 L 616 410 L 620 410 L S N 576 405 M 578 408 L 581 408 L 583 405 L 581 401 L 578 401 L 576 405 L S N [10 3 1 3] 0 D 580 405 M 663 405 L S N 170 60 M 171 63 L 171 65 L 172 68 L 172 70 L 172 73 L 173 75 L 173 77 L 174 80 L 174 82 L 175 85 L 175 87 L 176 90 L 176 92 L 177 94 L 177 97 L 178 99 L 178 102 L 179 104 L 179 106 L 179 109 L 180 111 L 180 114 L 181 116 L 181 119 L 182 121 L 182 123 L 183 126 L 183 128 L 184 131 L 184 133 L 185 135 L 185 138 L 185 140 L 186 143 L 186 145 L 187 148 L 187 150 L 188 152 L 188 155 L 189 157 L 189 160 L 190 162 L 190 164 L 191 167 L 191 169 L 191 172 L 192 174 L 192 176 L 193 179 L 193 181 L 194 184 L 194 186 L 195 188 L 195 191 L 196 193 L 196 196 L 197 198 L 197 200 L 197 203 L 198 205 L 198 208 L 199 210 L 199 212 L 200 215 L 200 217 L 201 220 L 201 222 L 202 224 L 202 227 L 203 229 L 203 232 L 204 234 L 204 236 L 204 239 L 205 241 L 205 244 L 206 246 L 206 248 L 207 251 L 207 253 L 208 255 L 208 258 L 209 260 L 209 263 L 210 265 L 210 267 L 210 270 L 211 272 L 211 274 L 212 277 L 212 279 L 213 281 L 213 284 L 214 286 L 214 289 L 215 291 L 215 293 L 216 296 L 216 298 L 216 300 L 217 303 L 217 305 L 218 307 L 218 310 L 219 312 L 219 314 L 220 317 L 220 319 L 221 321 L 221 324 L 222 326 L 222 328 L 222 330 L 223 333 L 223 335 L 224 337 L 224 339 L 225 342 L 225 344 L 226 346 L 226 348 L 227 351 L 227 353 L 228 355 L 228 357 L 229 359 L 229 361 L 229 363 L 230 366 L 230 368 L 231 370 L 231 372 L 232 373 L 232 375 L 233 377 L 233 379 L 234 380 L 234 382 L 235 383 L 235 384 L 235 385 L 236 385 L 236 386 L 237 386 L 238 387 L 239 387 L 240 387 L 241 387 L 242 387 L 243 387 L 244 387 L 245 387 L 246 387 L 247 387 L 248 387 L 249 387 L 250 387 L 251 387 L 252 387 L 253 387 L 254 387 L 255 387 L 256 387 L 257 387 L 258 387 L 259 387 L 260 387 L 261 387 L 262 387 L 263 387 L 264 387 L 265 387 L 266 387 L 267 387 L 268 387 L 269 387 L 270 387 L 271 387 L 272 387 L 273 387 L 274 387 L 275 387 L 276 387 L 277 387 L 278 387 L 279 387 L 280 387 L 281 387 L 282 387 L 283 387 L 284 387 L 285 387 L 286 387 L 287 387 L 288 387 L 289 387 L 290 387 L 291 387 L 292 387 L 293 387 L S N 293 387 M 294 387 L 295 387 L 296 387 L 297 387 L 298 387 L 299 387 L 300 387 L 301 387 L 302 387 L 303 387 L 304 387 L 305 387 L 306 387 L 307 387 L 308 387 L 309 387 L 310 387 L 311 387 L 312 387 L 313 387 L 314 387 L 315 387 L 316 387 L 317 387 L 318 387 L 319 387 L 320 387 L 321 387 L 322 387 L 323 387 L 324 387 L 325 387 L 326 387 L 327 387 L 328 387 L 329 387 L 330 387 L 331 387 L 332 387 L 333 387 L 334 387 L 335 387 L 336 387 L 337 387 L 338 387 L 339 387 L 340 387 L 341 387 L 342 387 L 343 387 L 344 387 L 345 387 L 346 387 L 347 387 L 348 387 L 349 387 L 350 387 L 351 387 L 352 387 L 353 387 L 354 387 L 355 387 L 356 387 L 357 387 L 358 387 L 359 387 L 360 387 L 361 387 L 362 387 L 363 387 L 364 387 L 365 387 L 366 387 L 367 387 L 368 387 L 369 387 L 370 387 L 371 387 L 372 387 L 373 387 L 374 387 L 375 387 L 376 387 L 377 387 L 378 387 L 379 387 L 380 387 L 381 387 L 382 387 L 383 387 L 384 387 L 385 387 L 386 387 L 387 387 L 388 387 L 389 387 L 390 387 L 391 387 L 392 387 L 393 387 L 394 387 L 395 387 L 396 387 L 397 387 L 398 387 L 399 387 L 400 387 L 401 387 L 402 387 L 403 387 L 404 387 L 405 387 L 406 387 L 407 387 L 408 387 L 409 387 L 410 387 L 411 387 L 412 387 L 413 387 L 414 387 L 415 387 L 416 387 L 417 387 L 418 387 L 419 387 L 420 387 L 421 387 L 422 387 L 423 387 L 424 387 L 425 387 L 426 387 L 427 387 L 428 387 L 429 387 L 430 387 L 431 387 L 432 387 L 433 387 L 434 387 L 435 387 L 436 387 L 437 387 L 438 387 L 439 387 L 440 387 L 441 387 L 442 387 L 443 387 L 444 387 L 445 387 L 446 387 L 447 387 L 448 387 L 449 387 L 450 387 L 451 387 L 452 387 L 453 387 L 454 387 L 455 387 L 456 387 L 457 387 L 458 387 L 459 387 L 460 387 L 461 387 L 462 387 L 463 387 L 464 387 L 465 387 L 466 387 L 467 387 L 468 387 L 469 387 L 470 387 L 471 387 L 472 387 L 473 387 L 474 387 L 475 387 L 476 387 L 477 387 L 478 387 L 479 387 L 480 387 L 481 387 L 482 387 L 483 387 L 484 387 L 485 387 L 486 387 L 487 387 L 488 387 L 489 387 L 490 387 L 491 387 L 492 387 L 493 387 L S N 493 387 M 494 387 L 495 387 L 496 387 L 497 387 L 498 387 L 499 387 L 500 387 L 501 387 L 502 387 L 503 387 L 504 387 L 505 387 L 506 387 L 507 387 L 508 387 L 509 387 L 510 387 L 511 387 L 512 387 L 513 387 L 514 387 L 515 387 L 516 387 L 517 387 L 518 387 L 519 387 L 520 387 L 521 387 L 522 387 L 523 387 L 524 387 L 525 387 L 526 387 L 527 387 L 528 387 L 529 387 L 530 387 L 531 387 L 532 387 L 533 387 L 534 387 L 535 387 L 536 387 L 537 387 L 538 387 L 539 387 L 540 387 L 541 387 L 542 387 L 543 387 L 544 387 L 545 387 L 546 387 L 547 387 L 548 387 L 549 387 L 550 387 L 551 387 L 552 387 L 553 387 L 554 387 L 555 387 L 556 387 L 557 387 L 558 387 L 559 387 L 560 387 L 561 387 L 562 387 L 563 387 L 564 387 L 565 387 L S N 565 387 M 566 387 L 567 387 L S N [] 0 D 563 387 M 565 390 L 568 390 L 570 387 L 568 383 L 565 383 L 563 387 L S 0 0 M showpage restore %%Trailer %%EndDocument FMENDEPSF 72 441 540 720 C 0 0 612 792 C FMENDPAGE %%EndPage: "6" 6 %%Page: "7" 7 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] [ 0 0 0 0 1 1 1] [ 0 0 0 1 0 0 0] 9 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 72 748.77 540 768.57 R 7 X 0 0 0 1 0 0 0 K V 0 11.2 Q 0 X (Conclusions) 72 755.2 T 72 18 540 54 R 7 X V 0 10 Q 0 X (Measuring Pulldown Currents in CMOS devices) 72 35.33 T (April 15, 1994 2:01 pm) 72 23.33 T 1 12 Q (7) 533.33 23.33 T 72.33 46 540 46 2 L 1 H 2 Z N 72 765.96 539.67 765.96 2 L N 72 751.89 540 751.89 2 L N 72 72 540 720 R 7 X V 0 0 0 1 0 0 0 K 2 F 0 X (subtraction of the Drain currents gives the IV curve shown in Figure 9 on page 7.) 144 712 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 1 F (9.4. Conclusions) 72 302 T 0 0 0 1 0 0 0 K 2 F (Due to the nature of SPICE it is possible to generate non-monotonic models that do not) 108 276 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.21 (measure the true behavior of physical devices. Though there are some devices that exhibit) 108 262 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.17 (non-monotonic behavior, CMOS pulldown devices in the 0 to -5V range do NOT fall into) 108 248 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (this class.) 108 234 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.45 (However, the indicated measurement for Drain current is easy to make, and if one is aware) 108 208 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (of the inherent error in the data, corrections can easily be applied.) 108 194 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.22 (Also, the cumulative percentage error in the Non-monotonic current is almost 0 due to the) 108 168 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (large value of the shunt currents at the time of the non-monotonicity.) 108 154 T 0 0 0 1 0 0 0 K 1 F (9.5. Rebuttals and Clarifications) 72 116 T 0 0 0 1 0 0 0 K 2 F (The simulations in this paper were run on HSPICE and Berkeley spice. If you have) 108 90 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (questions or evidence that this information is wrong, please contact:) 108 76 T 0 0 0 1 0 0 0 K 0 F (Figure 9:) 161.61 398 T (Subtraction of IV curves with bulk resistance) 214.96 398 T 72 414 540 688 C 72 414 540 688 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 90 0 0 612 792 270 349.41 176.3 378.3 FMBEGINEPSF %%BeginDocument: %!PS-Adobe-2.0 EPSF-2.0 %%BoundingBox: 0 0 612 792 %%DocumentFonts: %%EndComments %%BeginProcSet: /D /setdash load def /L /lineto load def /M /moveto load def /N /newpath load def /S /stroke load def %%EndProcSet %%EndProlog %%Page: 0 1 save 0.50000E+00 setlinewidth 1 setlinecap 1 setlinejoin 612 0 translate -90 rotate 0 -576 translate -720 0 translate N [] 0 D 60 490 M 56 490 L 56 497 L 60 497 L S N 56 493 M 58 493 L S N 64 490 M 64 497 L 68 490 L 68 497 L S N 72 490 M 72 497 L 72 493 L 76 493 L 76 490 L 76 497 L S N 80 490 M 80 493 L 81 497 L 83 497 L 84 493 L 84 490 L S N 80 492 M 84 492 L S N 88 490 M 88 497 L 92 490 L 92 497 L S N 100 491 M 99 490 L 97 490 L 96 491 L 96 496 L 97 497 L 99 497 L 100 496 L S N 108 490 M 104 490 L 104 497 L 108 497 L S N 104 493 M 106 493 L S N 112 490 M 112 497 L 115 497 L 116 496 L 116 491 L 115 490 L 112 490 L S N 128 497 M 128 490 L 132 490 L S N 137 490 M 136 491 L 136 496 L 137 497 L 139 497 L 140 496 L 140 491 L 139 490 L 137 490 L S N 144 497 M 145 490 L 146 497 L 147 490 L 148 497 L S N 153 493 M 155 493 L S N 164 496 M 163 497 L 161 497 L 160 496 L 160 494 L 161 493 L 163 493 L 164 492 L 164 491 L 163 490 L 161 490 L 160 491 L S N 170 490 M 170 497 L 168 497 L 172 497 L S N 176 490 M 176 493 L 177 497 L 179 497 L 180 493 L 180 490 L S N 176 492 M 180 492 L S N 186 490 M 186 497 L 184 497 L 188 497 L S N 196 490 M 192 490 L 192 497 L 196 497 L S N 192 493 M 194 493 L S N 208 497 M 210 490 L 212 497 L S N 216 490 M 220 497 L S N 225 490 M 227 490 L 226 490 L 226 497 L 225 497 L 227 497 L S N 240 490 M 240 497 L 243 497 L 244 496 L 244 494 L 243 493 L 240 493 L S N 248 497 M 248 490 L 252 490 L S N 257 490 M 256 491 L 256 496 L 257 497 L 259 497 L 260 496 L 260 491 L 259 490 L 257 490 L S N 266 490 M 266 497 L 264 497 L 268 497 L S N 274 490 M 273 489 L S N 289 490 M 291 490 L 290 490 L 290 497 L 289 497 L 291 497 L S N 296 490 M 296 497 L 300 490 L 300 497 L S N 308 491 M 307 490 L 305 490 L 304 491 L 304 496 L 305 497 L 307 497 L 308 496 L S N 312 497 M 312 490 L 316 490 L S N 320 497 M 320 491 L 321 490 L 323 490 L 324 491 L 324 497 L S N 328 490 M 328 497 L 331 497 L 332 496 L 332 491 L 331 490 L 328 490 L S N 337 490 M 339 490 L 338 490 L 338 497 L 337 497 L 339 497 L S N 344 490 M 344 497 L 348 490 L 348 497 L S N 356 496 M 355 497 L 353 497 L 352 496 L 352 491 L 353 490 L 355 490 L 356 491 L 356 493 L 354 493 L 354 492 L S N 369 496 M 370 497 L 370 490 L 369 490 L 371 490 L S N 378 490 M 379 490 L S N 386 490 M 385 491 L 385 496 L 386 497 L 387 497 L 388 496 L 388 491 L 387 490 L 386 490 L S N 401 490 M 400 491 L 400 496 L 401 497 L 403 497 L 404 496 L 404 491 L 403 490 L 401 490 L S N 408 490 M 408 497 L 408 493 L 412 493 L 412 490 L 412 497 L S N 416 490 M 416 497 L 418 493 L 420 497 L 420 490 L S N 428 496 M 427 497 L 425 497 L 424 496 L 424 494 L 425 493 L 427 493 L 428 492 L 428 491 L 427 490 L 425 490 L 424 491 L S N 444 496 M 443 497 L 441 497 L 440 496 L 440 494 L 441 493 L 443 493 L 444 492 L 444 491 L 443 490 L 441 490 L 440 491 L S N 448 497 M 448 491 L 449 490 L 451 490 L 452 491 L 452 497 L S N 456 490 M 456 497 L 459 497 L 460 496 L 460 494 L 459 493 L 456 493 L 459 493 L 460 492 L 460 491 L 459 490 L 456 490 L S N 468 496 M 467 497 L 465 497 L 464 496 L 464 494 L 465 493 L 467 493 L 468 492 L 468 491 L 467 490 L 465 490 L 464 491 L S N 474 490 M 474 497 L 472 497 L 476 497 L S N 480 490 M 480 497 L 483 497 L 484 496 L 484 494 L 483 493 L 480 493 L 482 493 L 484 490 L S N 488 490 M 488 493 L 489 497 L 491 497 L 492 493 L 492 490 L S N 488 492 M 492 492 L S N 498 490 M 498 497 L 496 497 L 500 497 L S N 508 490 M 504 490 L 504 497 L 508 497 L S N 504 493 M 506 493 L S N 520 490 M 520 497 L 523 497 L 524 496 L 524 494 L 523 493 L 520 493 L 522 493 L 524 490 L S N 532 490 M 528 490 L 528 497 L 532 497 L S N 528 493 M 530 493 L S N 540 496 M 539 497 L 537 497 L 536 496 L 536 494 L 537 493 L 539 493 L 540 492 L 540 491 L 539 490 L 537 490 L 536 491 L S N 545 490 M 547 490 L 546 490 L 546 497 L 545 497 L 547 497 L S N 556 496 M 555 497 L 553 497 L 552 496 L 552 494 L 553 493 L 555 493 L 556 492 L 556 491 L 555 490 L 553 490 L 552 491 L S N 562 490 M 562 497 L 560 497 L 564 497 L S N 568 490 M 568 493 L 569 497 L 571 497 L 572 493 L 572 490 L S N 568 492 M 572 492 L S N 576 490 M 576 497 L 580 490 L 580 497 L S N 588 491 M 587 490 L 585 490 L 584 491 L 584 496 L 585 497 L 587 497 L 588 496 L S N 596 490 M 592 490 L 592 497 L 596 497 L S N 592 493 M 594 493 L S N 273 487 M 272 483 L 276 483 L S N 275 487 M 275 480 L S N 281 483 M 283 483 L S N 288 480 M 288 483 L 289 487 L 291 487 L 292 483 L 292 480 L S N 288 482 M 292 482 L S N 296 480 M 296 487 L 299 487 L 300 486 L 300 484 L 299 483 L 296 483 L S N 304 480 M 304 487 L 307 487 L 308 486 L 308 484 L 307 483 L 304 483 L 306 483 L 308 480 L S N 312 481 M 313 480 L 315 480 L 316 481 L 316 486 L 315 487 L 313 487 L 312 486 L 312 484 L 313 483 L 315 483 L 316 484 L S N 321 487 M 320 483 L 324 483 L S N 323 487 M 323 480 L S N 337 486 M 338 487 L 338 480 L 337 480 L 339 480 L S N 344 481 M 345 480 L 347 480 L 348 481 L 348 486 L 347 487 L 345 487 L 344 486 L 344 484 L 345 483 L 347 483 L 348 484 L S N 354 481 M 354 482 L S N 354 484 M 354 486 L S N 361 487 M 360 483 L 364 483 L S N 363 487 M 363 480 L S N 369 483 M 368 484 L 368 486 L 369 487 L 371 487 L 372 486 L 372 484 L 371 483 L 369 483 L 368 482 L 368 481 L 369 480 L 371 480 L 372 481 L 372 482 L 371 483 L S N 378 481 M 378 482 L S N 378 484 M 378 486 L S N 388 487 M 384 487 L 384 483 L 385 484 L 387 484 L 388 483 L 388 481 L 387 480 L 385 480 L 384 481 L S N 392 481 M 393 480 L 395 480 L 396 481 L 396 486 L 395 487 L 393 487 L 392 486 L 392 484 L 393 483 L 395 483 L 396 484 L S N [] 0 D 98 40 M 97 41 L 97 46 L 98 47 L 99 47 L 100 46 L 100 41 L 99 40 L 98 40 L S N 106 40 M 107 40 L S N 536 46 M 537 47 L 537 40 L 536 40 L 538 40 L S N 545 40 M 544 41 L 544 46 L 545 47 L 546 47 L 547 46 L 547 41 L 546 40 L 545 40 L S N 553 40 M 552 41 L 552 46 L 553 47 L 554 47 L 555 46 L 555 41 L 554 40 L 553 40 L S N 561 40 M 562 40 L S N 569 40 M 568 41 L 568 46 L 569 47 L 570 47 L 571 46 L 571 41 L 570 40 L 569 40 L S N 575 40 M 575 47 L 577 43 L 579 47 L 579 40 L S N 290 40 M 290 47 L 288 47 L 292 47 L S N 297 40 M 299 40 L 298 40 L 298 47 L 297 47 L 299 47 L S N 304 40 M 304 47 L 306 43 L 308 47 L 308 40 L S N 316 40 M 312 40 L 312 47 L 316 47 L S N 312 43 M 314 43 L S N 331 47 M 330 47 L 329 46 L 329 41 L 330 40 L 331 40 L S N 336 47 M 336 40 L 340 40 L S N 345 40 M 347 40 L 346 40 L 346 47 L 345 47 L 347 47 L S N 352 40 M 352 47 L 356 40 L 356 47 L S N 361 47 M 362 47 L 363 46 L 363 41 L 362 40 L 361 40 L S N [] 0 D 127 60 M 127 64 L S N 150 60 M 150 64 L S N 173 60 M 173 64 L S N 196 60 M 196 64 L S N [] 0 D 188 56 M 189 57 L 191 57 L 192 56 L 192 54 L 191 53 L 189 53 L 188 52 L 188 50 L 192 50 L S N 198 50 M 197 51 L 197 56 L 198 57 L 199 57 L 200 56 L 200 51 L 199 50 L 198 50 L S N 206 50 M 207 50 L S N 214 50 M 213 51 L 213 56 L 214 57 L 215 57 L 216 56 L 216 51 L 215 50 L 214 50 L S N 220 50 M 220 57 L 222 53 L 224 57 L 224 50 L S N [.5 4] 0 D 196 469 M 196 60 L S N [] 0 D 196 60 M 196 68 L S N 219 60 M 219 64 L S N 242 60 M 242 64 L S N 266 60 M 266 64 L S N 289 60 M 289 64 L S N [] 0 D 282 57 M 281 53 L 285 53 L S N 284 57 M 284 50 L S N 291 50 M 290 51 L 290 56 L 291 57 L 292 57 L 293 56 L 293 51 L 292 50 L 291 50 L S N 299 50 M 300 50 L S N 307 50 M 306 51 L 306 56 L 307 57 L 308 57 L 309 56 L 309 51 L 308 50 L 307 50 L S N 313 50 M 313 57 L 315 53 L 317 57 L 317 50 L S N [.5 4] 0 D 289 469 M 289 60 L S N [] 0 D 289 60 M 289 68 L S N 312 60 M 312 64 L S N 335 60 M 335 64 L S N 358 60 M 358 64 L S N 381 60 M 381 64 L S N [] 0 D 377 56 M 376 57 L 374 57 L 373 56 L 373 51 L 374 50 L 376 50 L 377 51 L 377 52 L 376 53 L 374 53 L 373 52 L S N 383 50 M 382 51 L 382 56 L 383 57 L 384 57 L 385 56 L 385 51 L 384 50 L 383 50 L S N 391 50 M 392 50 L S N 399 50 M 398 51 L 398 56 L 399 57 L 400 57 L 401 56 L 401 51 L 400 50 L 399 50 L S N 405 50 M 405 57 L 407 53 L 409 57 L 409 50 L S N [.5 4] 0 D 381 469 M 381 60 L S N [] 0 D 381 60 M 381 68 L S N 404 60 M 404 64 L S N 428 60 M 428 64 L S N 451 60 M 451 64 L S N 474 60 M 474 64 L S N [] 0 D 467 53 M 466 54 L 466 56 L 467 57 L 469 57 L 470 56 L 470 54 L 469 53 L 467 53 L 466 52 L 466 51 L 467 50 L 469 50 L 470 51 L 470 52 L 469 53 L S N 476 50 M 475 51 L 475 56 L 476 57 L 477 57 L 478 56 L 478 51 L 477 50 L 476 50 L S N 484 50 M 485 50 L S N 492 50 M 491 51 L 491 56 L 492 57 L 493 57 L 494 56 L 494 51 L 493 50 L 492 50 L S N 498 50 M 498 57 L 500 53 L 502 57 L 502 50 L S N [.5 4] 0 D 474 469 M 474 60 L S N [] 0 D 474 60 M 474 68 L S N 497 60 M 497 64 L S N 520 60 M 520 64 L S N 543 60 M 543 64 L S N 567 60 M 567 64 L S N [] 0 D 560 56 M 561 57 L 561 50 L 560 50 L 562 50 L S N 569 50 M 568 51 L 568 56 L 569 57 L 570 57 L 571 56 L 571 51 L 570 50 L 569 50 L S N 577 50 M 576 51 L 576 56 L 577 57 L 578 57 L 579 56 L 579 51 L 578 50 L 577 50 L S N 585 50 M 586 50 L S N 593 50 M 592 51 L 592 56 L 593 57 L 594 57 L 595 56 L 595 51 L 594 50 L 593 50 L S N 599 50 M 599 57 L 601 53 L 603 57 L 603 50 L S N [.5 4] 0 D 567 469 M 567 60 L S N [] 0 D 567 60 M 567 68 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 567 60 M 567 64 L S N 16 310 M 16 313 L 17 317 L 19 317 L 20 313 L 20 310 L S N 16 312 M 20 312 L S N 16 300 M 16 307 L 18 303 L 20 307 L 20 300 L S N 16 290 M 16 297 L 19 297 L 20 296 L 20 294 L 19 293 L 16 293 L S N 16 277 M 16 270 L 20 270 L S N 17 260 M 19 260 L 18 260 L 18 267 L 17 267 L 19 267 L S N 16 250 M 16 257 L 20 250 L 20 257 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N 104 60 M 108 60 L S N [] 0 D 69 57 M 71 57 L S N 76 60 M 77 61 L 79 61 L 80 60 L 80 58 L 79 57 L 77 57 L 76 56 L 76 54 L 80 54 L S N 86 54 M 87 54 L S N 94 54 M 93 55 L 93 60 L 94 61 L 95 61 L 96 60 L 96 55 L 95 54 L 94 54 L S N [.5 4] 0 D 567 60 M 104 60 L S N [] 0 D 104 60 M 112 60 L S N 104 68 M 108 68 L S N 104 76 M 108 76 L S N 104 84 M 108 84 L S N 104 92 M 108 92 L S N [] 0 D 61 89 M 63 89 L S N 69 92 M 70 93 L 70 86 L 69 86 L 71 86 L S N 78 86 M 79 86 L S N 85 89 M 84 90 L 84 92 L 85 93 L 87 93 L 88 92 L 88 90 L 87 89 L 85 89 L 84 88 L 84 87 L 85 86 L 87 86 L 88 87 L 88 88 L 87 89 L S N 94 86 M 93 87 L 93 92 L 94 93 L 95 93 L 96 92 L 96 87 L 95 86 L 94 86 L S N [.5 4] 0 D 567 92 M 104 92 L S N [] 0 D 104 92 M 112 92 L S N 104 100 M 108 100 L S N 104 109 M 108 109 L S N 104 117 M 108 117 L S N 104 125 M 108 125 L S N [] 0 D 61 122 M 63 122 L S N 69 125 M 70 126 L 70 119 L 69 119 L 71 119 L S N 78 119 M 79 119 L S N 88 125 M 87 126 L 85 126 L 84 125 L 84 120 L 85 119 L 87 119 L 88 120 L 88 121 L 87 122 L 85 122 L 84 121 L S N 94 119 M 93 120 L 93 125 L 94 126 L 95 126 L 96 125 L 96 120 L 95 119 L 94 119 L S N [.5 4] 0 D 567 125 M 104 125 L S N [] 0 D 104 125 M 112 125 L S N 104 133 M 108 133 L S N 104 141 M 108 141 L S N 104 149 M 108 149 L S N 104 158 M 108 158 L S N [] 0 D 61 155 M 63 155 L S N 69 158 M 70 159 L 70 152 L 69 152 L 71 152 L S N 78 152 M 79 152 L S N 85 159 M 84 155 L 88 155 L S N 87 159 M 87 152 L S N 94 152 M 93 153 L 93 158 L 94 159 L 95 159 L 96 158 L 96 153 L 95 152 L 94 152 L S N [.5 4] 0 D 567 158 M 104 158 L S N [] 0 D 104 158 M 112 158 L S N 104 166 M 108 166 L S N 104 174 M 108 174 L S N 104 182 M 108 182 L S N 104 190 M 108 190 L S N [] 0 D 61 187 M 63 187 L S N 69 190 M 70 191 L 70 184 L 69 184 L 71 184 L S N 78 184 M 79 184 L S N 84 190 M 85 191 L 87 191 L 88 190 L 88 188 L 87 187 L 85 187 L 84 186 L 84 184 L 88 184 L S N 94 184 M 93 185 L 93 190 L 94 191 L 95 191 L 96 190 L 96 185 L 95 184 L 94 184 L S N [.5 4] 0 D 567 190 M 104 190 L S N [] 0 D 104 190 M 112 190 L S N 104 199 M 108 199 L S N 104 207 M 108 207 L S N 104 215 M 108 215 L S N 104 223 M 108 223 L S N [] 0 D 69 220 M 71 220 L S N 77 223 M 78 224 L 78 217 L 77 217 L 79 217 L S N 86 217 M 87 217 L S N 94 217 M 93 218 L 93 223 L 94 224 L 95 224 L 96 223 L 96 218 L 95 217 L 94 217 L S N [.5 4] 0 D 567 223 M 104 223 L S N [] 0 D 104 223 M 112 223 L S N 104 231 M 108 231 L S N 104 239 M 108 239 L S N 104 248 M 108 248 L S N 104 256 M 108 256 L S N [] 0 D 45 253 M 47 253 L S N 53 253 M 52 254 L 52 256 L 53 257 L 55 257 L 56 256 L 56 254 L 55 253 L 53 253 L 52 252 L 52 251 L 53 250 L 55 250 L 56 251 L 56 252 L 55 253 L S N 62 250 M 61 251 L 61 256 L 62 257 L 63 257 L 64 256 L 64 251 L 63 250 L 62 250 L S N 70 250 M 69 251 L 69 256 L 70 257 L 71 257 L 72 256 L 72 251 L 71 250 L 70 250 L S N 78 250 M 79 250 L S N 86 250 M 85 251 L 85 256 L 86 257 L 87 257 L 88 256 L 88 251 L 87 250 L 86 250 L S N 92 250 M 92 257 L 94 253 L 96 257 L 96 250 L S N [.5 4] 0 D 567 256 M 104 256 L S N [] 0 D 104 256 M 112 256 L S N 104 264 M 108 264 L S N 104 272 M 108 272 L S N 104 280 M 108 280 L S N 104 289 M 108 289 L S N [] 0 D 45 286 M 47 286 L S N 56 289 M 55 290 L 53 290 L 52 289 L 52 284 L 53 283 L 55 283 L 56 284 L 56 285 L 55 286 L 53 286 L 52 285 L S N 62 283 M 61 284 L 61 289 L 62 290 L 63 290 L 64 289 L 64 284 L 63 283 L 62 283 L S N 70 283 M 69 284 L 69 289 L 70 290 L 71 290 L 72 289 L 72 284 L 71 283 L 70 283 L S N 78 283 M 79 283 L S N 86 283 M 85 284 L 85 289 L 86 290 L 87 290 L 88 289 L 88 284 L 87 283 L 86 283 L S N 92 283 M 92 290 L 94 286 L 96 290 L 96 283 L S N [.5 4] 0 D 567 289 M 104 289 L S N [] 0 D 104 289 M 112 289 L S N 104 297 M 108 297 L S N 104 305 M 108 305 L S N 104 313 M 108 313 L S N 104 321 M 108 321 L S N [] 0 D 45 318 M 47 318 L S N 53 322 M 52 318 L 56 318 L S N 55 322 M 55 315 L S N 62 315 M 61 316 L 61 321 L 62 322 L 63 322 L 64 321 L 64 316 L 63 315 L 62 315 L S N 70 315 M 69 316 L 69 321 L 70 322 L 71 322 L 72 321 L 72 316 L 71 315 L 70 315 L S N 78 315 M 79 315 L S N 86 315 M 85 316 L 85 321 L 86 322 L 87 322 L 88 321 L 88 316 L 87 315 L 86 315 L S N 92 315 M 92 322 L 94 318 L 96 322 L 96 315 L S N [.5 4] 0 D 567 321 M 104 321 L S N [] 0 D 104 321 M 112 321 L S N 104 329 M 108 329 L S N 104 338 M 108 338 L S N 104 346 M 108 346 L S N 104 354 M 108 354 L S N [] 0 D 45 351 M 47 351 L S N 52 354 M 53 355 L 55 355 L 56 354 L 56 352 L 55 351 L 53 351 L 52 350 L 52 348 L 56 348 L S N 62 348 M 61 349 L 61 354 L 62 355 L 63 355 L 64 354 L 64 349 L 63 348 L 62 348 L S N 70 348 M 69 349 L 69 354 L 70 355 L 71 355 L 72 354 L 72 349 L 71 348 L 70 348 L S N 78 348 M 79 348 L S N 86 348 M 85 349 L 85 354 L 86 355 L 87 355 L 88 354 L 88 349 L 87 348 L 86 348 L S N 92 348 M 92 355 L 94 351 L 96 355 L 96 348 L S N [.5 4] 0 D 567 354 M 104 354 L S N [] 0 D 104 354 M 112 354 L S N 104 362 M 108 362 L S N 104 370 M 108 370 L S N 104 379 M 108 379 L S N 104 387 M 108 387 L S N [] 0 D 86 381 M 85 382 L 85 387 L 86 388 L 87 388 L 88 387 L 88 382 L 87 381 L 86 381 L S N 94 381 M 95 381 L S N [.5 4] 0 D 567 387 M 104 387 L S N [] 0 D 104 387 M 112 387 L S N 104 395 M 108 395 L S N 104 403 M 108 403 L S N 104 411 M 108 411 L S N 104 419 M 108 419 L S N [] 0 D 52 419 M 53 420 L 55 420 L 56 419 L 56 417 L 55 416 L 53 416 L 52 415 L 52 413 L 56 413 L S N 62 413 M 61 414 L 61 419 L 62 420 L 63 420 L 64 419 L 64 414 L 63 413 L 62 413 L S N 70 413 M 69 414 L 69 419 L 70 420 L 71 420 L 72 419 L 72 414 L 71 413 L 70 413 L S N 78 413 M 79 413 L S N 86 413 M 85 414 L 85 419 L 86 420 L 87 420 L 88 419 L 88 414 L 87 413 L 86 413 L S N 92 413 M 92 420 L 94 416 L 96 420 L 96 413 L S N [.5 4] 0 D 567 419 M 104 419 L S N [] 0 D 104 419 M 112 419 L S N 104 428 M 108 428 L S N 104 436 M 108 436 L S N 104 444 M 108 444 L S N 104 452 M 108 452 L S N [] 0 D 53 453 M 52 449 L 56 449 L S N 55 453 M 55 446 L S N 62 446 M 61 447 L 61 452 L 62 453 L 63 453 L 64 452 L 64 447 L 63 446 L 62 446 L S N 70 446 M 69 447 L 69 452 L 70 453 L 71 453 L 72 452 L 72 447 L 71 446 L 70 446 L S N 78 446 M 79 446 L S N 86 446 M 85 447 L 85 452 L 86 453 L 87 453 L 88 452 L 88 447 L 87 446 L 86 446 L S N 92 446 M 92 453 L 94 449 L 96 453 L 96 446 L S N [.5 4] 0 D 567 452 M 104 452 L S N [] 0 D 104 452 M 112 452 L S N 104 460 M 108 460 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 104 469 M 108 469 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 563 60 L S N 567 60 M 559 60 L S N 567 68 M 563 68 L S N 567 76 M 563 76 L S N 567 84 M 563 84 L S N 567 92 M 563 92 L S N 567 92 M 559 92 L S N 567 100 M 563 100 L S N 567 109 M 563 109 L S N 567 117 M 563 117 L S N 567 125 M 563 125 L S N 567 125 M 559 125 L S N 567 133 M 563 133 L S N 567 141 M 563 141 L S N 567 149 M 563 149 L S N 567 158 M 563 158 L S N 567 158 M 559 158 L S N 567 166 M 563 166 L S N 567 174 M 563 174 L S N 567 182 M 563 182 L S N 567 190 M 563 190 L S N 567 190 M 559 190 L S N 567 199 M 563 199 L S N 567 207 M 563 207 L S N 567 215 M 563 215 L S N 567 223 M 563 223 L S N 567 223 M 559 223 L S N 567 231 M 563 231 L S N 567 239 M 563 239 L S N 567 248 M 563 248 L S N 567 256 M 563 256 L S N 567 256 M 559 256 L S N 567 264 M 563 264 L S N 567 272 M 563 272 L S N 567 280 M 563 280 L S N 567 289 M 563 289 L S N 567 289 M 559 289 L S N 567 297 M 563 297 L S N 567 305 M 563 305 L S N 567 313 M 563 313 L S N 567 321 M 563 321 L S N 567 321 M 559 321 L S N 567 329 M 563 329 L S N 567 338 M 563 338 L S N 567 346 M 563 346 L S N 567 354 M 563 354 L S N 567 354 M 559 354 L S N 567 362 M 563 362 L S N 567 370 M 563 370 L S N 567 379 M 563 379 L S N 567 387 M 563 387 L S N 567 387 M 559 387 L S N 567 395 M 563 395 L S N 567 403 M 563 403 L S N 567 411 M 563 411 L S N 567 419 M 563 419 L S N 567 419 M 559 419 L S N 567 428 M 563 428 L S N 567 436 M 563 436 L S N 567 444 M 563 444 L S N 567 452 M 563 452 L S N 567 452 M 559 452 L S N 567 460 M 563 460 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 567 469 M 563 469 L S N 584 467 M 588 460 L S N 584 460 M 588 467 L S N 592 467 M 596 460 L S N 592 460 M 596 467 L S N 600 467 M 604 460 L S N 600 460 M 604 467 L S N 608 467 M 612 460 L S N 608 460 M 612 467 L S N 618 460 M 619 460 L S N 626 460 M 626 467 L 624 467 L 628 467 L S N 632 460 M 632 467 L 635 467 L 636 466 L 636 464 L 635 463 L 632 463 L 634 463 L 636 460 L S N 642 460 M 641 461 L 641 466 L 642 467 L 643 467 L 644 466 L 644 461 L 643 460 L 642 460 L S N 585 450 M 587 450 L 586 450 L 586 457 L 585 457 L 587 457 L S N 595 457 M 594 457 L 593 456 L 593 451 L 594 450 L 595 450 L S N 600 457 M 602 450 L 604 457 L S N 608 450 M 608 457 L 611 457 L 612 456 L 612 451 L 611 450 L 608 450 L S N 617 456 M 618 457 L 618 450 L 617 450 L 619 450 L S N 625 457 M 626 457 L 627 456 L 627 451 L 626 450 L 625 450 L S N 633 453 M 635 453 L S N 641 450 M 643 450 L 642 450 L 642 457 L 641 457 L 643 457 L S N 651 457 M 650 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%%+ Helvetica-Bold %%+ Times-Roman %%+ Times-Italic %%+ Symbol %%EOF From bracken@bacon.performance.com Sun Apr 17 14:55:26 1994 Return-Path: Received: from bacon.performance.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA27245; Sun, 17 Apr 94 14:55:26 PDT Received: by bacon.performance.com (4.1/SMI-4.1) id AA00222; Sun, 17 Apr 94 17:54:20 EDT Message-Id: <9404172154.AA00222@bacon.performance.com> To: ibis@vhdl.org Subject: Bird 10.1 Date: Sun, 17 Apr 94 17:54:19 -0400 From: bracken@bacon.performance.com All, Included below is the revised version of Bird 10. It incorporates some changes that were discussed at the last meeting, regarding the ability to put package models EITHER in the .ibs file or in the .pkg file. Also included is specific language which permits alphanumeric pin names and "suffix" notation for numbers. I've also included notes about the definition of signs for currents and voltages, on scope rules for package model definitions, about what's allowed and not allowed in a .pkg file, etc. If you have access to "diff" and the old version of the BIRD, that might be an efficient way to evaluate this revision. ================================================================ Eric Bracken Performance Signal Integrity, Inc. ================================================================ ******************************************************************************* ******************************************************************************* Buffer Issue Resolution Document (BIRD) BIRD ID#: 10.1 ISSUE TITLE: Describing coupling effects in package models (revised) REQUESTOR: Eric Bracken, Performance Signal Integrity, Inc. DATE SUBMITTED: 17 March 1994 DATE REVISED: 17 April 1994 DATE ACCEPTED BY IBIS OPEN FORUM: {status or date BIRD accepted} ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: For a more thorough signal integrity analysis, a mechanism is needed for describing electromagnetic couplings between the different pins of a package. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: Summary: ------- A new keyword, [Package Model], is added to the .ibs file. This keyword is used within a [Component] to indicate (by name) the package model that should be used for a part. Package models can be found either in separate package model files, which bear the .pkg extension, or within the same .ibs file as the [Component]. An additional new keyword, [Define Package Model], is also added to the specification; this is used to mark the beginning of the actual package model data. The purpose of breaking up the package model and the component model is to make associations between the two more flexible: several components may share a single package model, or one component may have several different incarnations which use different packages (and thus, different package models). Use of [Package Model] is OPTIONAL. If it is not provided, then the table of RLC values listed in the [Pin] section of the [Component] is used as the "package model" for the part. On the other hand, if the [Package Model] IS given, then the R_pin, L_pin and C_pin values in the [Pin] section may either be ignored, or may be used for less detailed simulations without coupling. Probably this data will simply be left out of the [Pin] section when a [Package Model] is used; this practice is permitted by the IBIS Ver. 1.1 specification since [Pin] data may contain either 3 or 6 columns. A .pkg file is just an ordinary IBIS file, with the restriction that it cannot contain [Component]'s or [Model]'s. Only package models declared by the [Define Package Model] keyword may be contained within these files. Of course, all of the necessary components of an IBIS file ([IBIS Ver], [File Name], [File Rev], etc. through [End]) must still be included within a .pkg file. The package model to be used treats every package as a collection of current carrying "paths," which lead from the board, through the packages pins, leadframe traces and bonding wires to a bonding pad on the die itself. Each path has a self-resistance, self-inductance and self-capacitance associated with it. In addition, there is the flexibility to describe mutual inductance, mutual resistance and coupling capacitance drops between every path. This data can be listed concisely as three RLC parameter matrices. This BIRD describes how these matrices are to be formatted. I. Syntax for the .IBS File. ---------------------------- The following syntax is used for specifying a package model: |============================================================================== | | Keyword: [Package Model] | | Required: No | | Description: Used to indicate the name of the package model | | Usage Rules: The Package_Model_Name is limited to 40 characters. | Spaces are allowed in the name. | |------------------------------------------------------------------------------ | [Package Model] Package_Model_Name The [Package_Model] keyword is used within a [Component] to indicate which package model should be used for that part. The resolved specification permits .ibs files to contain [Define Package Model] keywords as well. These are described in Section II, "Syntax for the .PKG file", below. When package model definitions occur within a .ibs file, their scope is "local"--they are known only within that .ibs file and no other. In addition, within that .ibs file, they override any globally defined package models which have the same name. II. Syntax for the .PKG File ----------------------------- Package models are stored in a file whose name looks like .pkg The provided must adhere to the venerable MS-DOS file name conventions: it must not exceed 8 characters in length. All of these characters must be lower case. The extension ".pkg" is used to identify files containing package models. The .pkg file must contain all of the Required elements of a normal .ibs file, including [IBIS Ver], [File Name], [File Rev], and the [End] keywords. Optional elements include the [Date], [Source], [Notes], [Disclaimer] and [Comment char] keywords. All of the above elements follow the exact same rules as those for a normal .ibs file. Items which are FORBIDDEN in the .pkg file are [Component] and [Model] keywords. The .pkg file is only for package models. A. Package Models ------------------ Each package model is preceded by the [Define Package Model] keyword. |============================================================================== | | Keyword: [Define Package Model] | | Required: Yes | | Description: Used to mark the beginning of a package model description. | | Usage Rules: If the .pkg file contains data for more than one package, | each section must begin with a new [Define Package Model] | keyword. The length of the Package_Model_Name must not | exceed 40 characters in length and blank characters ARE | allowed. | |------------------------------------------------------------------------------ | [Define Package Model] Package_Model_Name The [Manufacturer] keyword is used to declare the manufacturer of the part(s) which use this package model. This would typically be the name of the semiconductor vendor. The syntax is identical to that of the [Manufacturer] keyword in the .ibs file, e.g. [Manufacturer] Bozonics Semiconductors Ltd. An additional optional keyword, [OEM], is used to indicate the name of the PACKAGE's manufacturer. This is useful if the semiconductor vendor sells a single IC in packages from different manufacturers (e.g. AMP, Kyocera). The [OEM] keyword's syntax is analogous to that of the [Manufacturer] keyword. [OEM] Pkgs'R'Us The [Description] keyword is used to indicate to a human being what the model is describing. |============================================================================== | | Keyword: [Description] | | Required: Yes | | Description: This is used to provide a concise yet easily human-readable | description of what kind of package the [Package_Model] | is representing. An example Description_Text might be: | "220-Pin Quad Ceramic Flat Pack". | | Usage Rules: The description must be less than 60 characters in length, | must fit on a single line, and MAY contain spaces. | |------------------------------------------------------------------------------ | [Description] Description_Text The [Number of Pins] keyword identifies how many pins the package has. |============================================================================== | | Keyword: [Number of Pins] | | Required: Yes | | Description: This is used to tell the parser how many pins to expect. | | Usage Rules: The How_Many field must be a positive integer less than 60 | characters long. | |------------------------------------------------------------------------------ | [Number of Pins] How_Many The [Pin Names] keyword is used to list the names of the pins of the package, and to define an "ordering" among them. If the integers 1, 2, 3, ... are used as pin names, then the ordering is probably the obvious one. However, this is not the case when alphanumeric pin names are used. Since the ordering is very important for the RLC matrix information to be described shortly, we require that it be made explicit before those matrices are given. |============================================================================== | | Keyword: [Pin Names] | | Required: Yes | | Description: This is used to tell the parser the set of names that | will be used for the package pins, and to define an | ordering of them. The first pin name given is the | "lowest" pin, and the last pin given is the "highest." | The pin names may not exceed 5 characters in length. | | Usage Rules: Following the [Pin Names] field, the names of the pins are | listed. There must be as many names listed as there are | pins (as given by the preceding [Number of Pins].) | |------------------------------------------------------------------------------ | [Pin Names] | A1 A2 | . | . | . A22 B1 | . | . | . | etc. The beginning of the actual model data is marked with the [Model Data] keyword. |============================================================================== | | Keyword: [Model Data] | | Required: Yes | | Description: This is used to indicate the beginning of the formatted | model data. | | Usage Rules: This is pretty simple. | |------------------------------------------------------------------------------ | [Model Data] Similarly, the end of the model data is marked with an [End Model Data] keyword: |============================================================================== | | Keyword: [End Model Data] | | Required: Yes | | Description: This is used to indicate the end of the formatted | model data. | | Usage Rules: This is pretty simple too. | |------------------------------------------------------------------------------ | [End Model Data] In between these two keywords is the package model data itself. The data to be supplied is a set of 3 matrices: the resistance (R), inductance (L), and capacitance (C) matrices. Each matrix may be formatted differently (see below). A special keyword is used to mark the beginning of each new matrix: |============================================================================== | | Keywords: [Resistance Matrix], [Inductance Matrix], [Capacitance Matrix] | | Required: [Resistance Matrix] is optional. If it's not present, its | entries are assumed to be zero. [Inductance Matrix] and | [Capacitance Matrix] are required. | | Description: These are used to mark the beginning of a matrix, and to | specify how the matrix data will be formatted. | | Usage Rules: There are 3 choices for the Format_Keyword: | Banded Matrix, Sparse Matrix, and Full Matrix. | | After each of these keywords, the matrix data will follow | in the appropriate format. | | These formats are described in detail below. | |------------------------------------------------------------------------------ | [Resistance Matrix] Format_Keyword [Inductance Matrix] Format_Keyword [Capacitance Matrix] Format_Keyword C. Matrix Formats ------------------ For each [Resistance Matrix], [Inductance Matrix], or [Capacitance Matrix] a different format may be used for the data. The choice of formats is provided to satisfy different simulation accuracy and speed requirements. Also, there are many packages in which the resistance matrix may have no coupling terms at all; in this case, the most concise format (Banded_Matrix) may be used. One common aspect of all the different formats is that they exploit the symmetry of the matrices they describe. This means that the entries below the main diagonal of the matrix are identical to the corresponding entries above the main diagonal. Therefore, only roughly one-half of the matrix needs to be described. By convention, the main diagonal and the UPPER half of the matrix will be provided. The available formats are Banded_Matrix, Sparse_Matrix, and Full_Matrix. We describe each of the formats separately below. In the following, we use the notation [I, J] to refer to the entry in row I and column J of the matrix. Note that I and J are allowed to be alphanumeric strings as well as integers. An ordering of these strings has been defined earlier in the [Pin Names] section. The reader is advised that the following text sometimes refers to "Row 1", by which we mean the row corresponding to the first pin. Also, please note that the numeric entries of the RLC matrices are standard IBIS floating point numbers. As such, it is permissible to use metrix "suffix" notation. Thus, an entry of the C matrix could be given as "1.23e-12" or as "1.23p" or "1.23pF". 1. Full_Matrix When the Full_Matrix format is used, the couplings between every pair of elements will be specified explicitly. We assume that the matrix has N rows and N columns. The Full_Matrix is specified one row at a time, starting with Row 1 and continuing down to Row N. Each new row is identified with the Row keyword. |============================================================================== | | Keyword: [Row] | | Required: Yes | | Description: This is used to indicate the beginning of a new row of | the matrix. The Row_Number field must be a pin name, | | Usage Rules: This is pretty simple. | |------------------------------------------------------------------------------ | [Row] Row_Number Following a [Row] keyword is a block of numbers which represent the entries for that row. Suppose that the current row is number M. Then the first number listed is the diagonal entry, [M,M]. Following this are the entries of the upper half of the matrix that belong to row M: [M, M+1], [M, M+2], ... up to [M,N]. For even a modest-sized package, this data will not all fit on one line. Since each line of an IBIS file must be 80 characters long or less, it is permissible to break the data up with newlines so that this limit is observed. An example: suppose the package has 40 pins and that we are currently working on Row 19. There will be 1 diagonal entry, plus 40 - 19 = 21 entries in the upper half of the matrix to be specified, for 22 entries total. The data might be formatted as follows: [Row] 19 5.67e-9 1.1e-9 0.8e-9 0.6e-9 0.4e-9 0.2e-9 0.1e-9 0.09e-9 8e-10 7e-10 6e-10 5e-10 4e-10 3e-10 2e-10 1e-10 9e-11 8e-11 7e-11 6e-11 5e-11 4e-11 In the above example, the entry 5.67e-9 is on the diagonal of row 19. It will be observed that Row 1 always has the most entries, and that each successive row has one fewer entry than the last; the last row will always have just a single entry. 2. Banded_Matrix A Banded_Matrix is one whose entries are guaranteed to be zero if they are farther away from the main diagonal than a certain distance, known as the "bandwidth." Again let the matrix size be N, and let the bandwidth be B. An entry [I,J] of the matrix will be zero if | I - J | > B where |.| denotes the absolute value. The bandwidth for a Banded_Matrix must be specified using the [Bandwidth] keyword: |============================================================================== | | Keyword: [Bandwidth] | | Required: Yes (for banded matrices only) | | Description: This is used to indicate the bandwidth of the matrix. | The BW field below must be a nonnegative integer. This | keyword occurs after the [Resistance Matrix], etc. | keyword, and BEFORE the matrix data is given. | | Usage Rules: This is pretty simple. | |------------------------------------------------------------------------------ | [Bandwidth] BW The banded matrix is specified one row at a time, starting with row 1 and working up to higher rows. Each row is marked with the [Row] keyword, as above. As before, symmetry is exploited: entries below the main diagonal are never given. The first row will only need to specify the entries [1,1] through [1,1+B] since any other entries are guaranteed to be zero. The second row will need to specify the entries [2,2] through [2, 2+B], and so on. In general, for row M the entries [M,M] through [M,M+B] are given. Unlike the Full_Matrix, each successive row will _typically_ have the same number of entries, except for the last few rows. When M + B finally exceeds the size of the matrix N, then the number of entries in each row will start to decrease; the last row (row N) will have only 1 entry. As in the Full_Matrix, if all the entries for a particular row will not fit into a single 80-character line, the entries may be broken across several lines. It is possible to use a bandwidth of 0 to specify a diagonal matrix (a matrix with no coupling terms.) This is sometimes useful for resistance matrices. 3. Sparse_Matrix The final option for specifying the entries of the matrix is the Sparse_Matrix format. A sparse matrix is expected to consist mostly of zero-valued entries, except for a few nonzeros. Unlike the Banded_Matrix, there is no restriction on where the nonzero entries may occur. This is useful in certain situations, such as for Pin Grid Arrays (PGA's.) As usual, symmetry may be exploited to reduce the amount of data by eliminating from the matrix any entries below the main diagonal. An N x N Sparse_Matrix is specified one row at a time, starting with row 1 and continuing down to row N. Each new row is marked with [Row] keyword, as in the other matrix formats. Data for the entries of a row is given in a slightly different format, however. For the entry [I, J] of a row, it is necessary to explicitly list the name of pin J before the value of the entry is given. This serves to indicate to the parser where the entry is put into the matrix. The proper location is not otherwise obvious because of the lack of restrictions on where nonzeros may occur. Each (Index, Value) pair is listed upon a separate line. An example follows. Suppose that row 10 has nonzero entries [10,10], [10,11], [10,15] and [10,25]. The following row data would be provided: [Row] 10 | Index Value 10 5.7e-9 11 1.1e-9 15 1.1e-9 25 1.1e-9 Please note that each of the column indices listed for any row must be greater than or equal to the row index, because they always come from the upper half of the matrix. When alphanumeric pin names are used, special care must be taken to ensure that the ordering defined in the [Pin Names] section is observed. Also, please note that it is again necessarily the case that the N'th row of an N x N matrix will have just a single entry (the diagonal entry.) D. An Example The following is an example of a package model file following the above specifications. For the sake of brevity, an 8-pin package has been described. For purposes of illustration, each of the matrices is specified using a different format. | |================================================================ | [IBIS Ver] 2.0 [File Name] example.pkg [File Rev] 0.1 [Date] 17 April 1994 [Source] fervid imaginings [Notes] Example for a BIRD on couplings in packaging [Disclaimer] The models given below may not represent any physically realizable 8-pin package. They are provided solely for the purpose of illustrating the .pkg file format. Read at your own risk. See your dentist regularly. | |================================================================ | [Define Package Model] Bozo-SMT-cer-8-pin-pkgs [Manufacturer] Bozonics Semiconductors Ltd. [OEM] Pkgs'R'Us [Description] 8-Pin ceramic SMT package [Number of Pins] 8 | [Pin Names] 1 2 3 4 5 6 7 8 | [Model Data] | | The resistance matrix for this package has no coupling | [Resistance Matrix] Banded_Matrix [Bandwidth] 0 [Row] 1 10.0 [Row] 2 15.0 [Row] 3 15.0 [Row] 4 10.0 [Row] 5 10.0 [Row] 6 15.0 [Row] 7 15.0 [Row] 8 10.0 | | The inductance matrix has loads of coupling | [Inductance Matrix] Full_Matrix [Row] 1 3.04859e-07 4.73185e-08 1.3428e-08 6.12191e-09 1.74022e-07 7.35469e-08 2.73201e-08 1.33807e-08 [Row] 2 3.04859e-07 4.73185e-08 1.3428e-08 7.35469e-08 1.74022e-07 7.35469e-08 2.73201e-08 [Row] 3 3.04859e-07 4.73185e-08 2.73201e-08 7.35469e-08 1.74022e-07 7.35469e-08 [Row] 4 3.04859e-07 1.33807e-08 2.73201e-08 7.35469e-08 1.74022e-07 [Row] 5 4.70049e-07 1.43791e-07 5.75805e-08 2.95088e-08 [Row] 6 4.70049e-07 1.43791e-07 5.75805e-08 [Row] 7 4.70049e-07 1.43791e-07 [Row] 8 4.70049e-07 | | The capacitance matrix has sparse coupling | [Capacitance Matrix] Sparse_Matrix [Row] 1 1 2.48227e-10 2 -1.56651e-11 5 -9.54158e-11 6 -7.15684e-12 [Row] 2 2 2.51798e-10 3 -1.56552e-11 5 -6.85199e-12 6 -9.0486e-11 7 -6.82003e-12 [Row] 3 3 2.51798e-10 4 -1.56651e-11 6 -6.82003e-12 7 -9.0486e-11 8 -6.85199e-12 [Row] 4 4 2.48227e-10 7 -7.15684e-12 8 -9.54158e-11 [Row] 5 5 1.73542e-10 6 -3.38247e-11 [Row] 6 6 1.86833e-10 7 -3.27226e-11 [Row] 7 7 1.86833e-10 8 -3.38247e-11 [Row] 8 8 1.73542e-10 | | All done! | [End Model Data] [End] III. Note on Measurement ------------------------- When measuring the entries of the RLC matrices, either with laboratory equipment or field solver software, the following fact should be kept in mind: Currents are defined as ENTERING the pins of the package from the board. The corresponding voltage drops are to be measured with the current pointing "in" to the "+" sign and "out" of the "-" sign. I1 +-----+ I2 -----> | | <------ board 0--------| Pkg |---------0 board + V1 - | | - V2 + +-----+ It is important to observe this convention in order to get the correct signs for the mutual inductances and resistances. ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: This is an attempt to add more electromagnetic information to the packaging models. The main element missing from the original IBIS packaging models are couplings between pins. These couplings can change the effective inductances of power and ground pins, affecting the amount of ground bounce that occurs in the model. The couplings can also lead to increased noise between signal pins. For these reasons (and more), they are worth considering. There are many ways one might approach the description of the coupling information. The choices made will certainly impact the efficiency and the accuracy of the signal integrity simulations that are carried out. To meet a wide variety of needs, several different options have been provided for specifying the coupling data. Full-matrix formats may be used for maximum electromagnetic rigorousness, or descriptions with limited amounts of coupling can be used to speed up simulation. This BIRD permits detailed package model information to be stored either in the .ibs file, along with [Component]'s and [Model]'s, or in a separate .pkg file. In the case where the package model is defined in the .ibs file, that definition is local to that single file. When a .pkg file is used, the model definition is exported, so that it can be used by IBIS [Component]'s in other files. Note that this is a departure from standard IBIS practice--in .ibs files, the "model" names, at least, are not exported from the file that contains them. Keeping package model data in separate files leads to the possibility of naming conflicts when different vendors (or even different groups within a large vendor company) provide files independently. Hopefully this can be managed by using long names for package models, and by using an official "name server" which keeps track of existing model names and warns of conflicts. What is still missing from this spec is the ability to handle models with arbitrary topologies of RLC circuit elements. This would be useful, for example, in the modelling of large packages where the traces are long enough to exhibit some "transmission-line" effects. In these cases, it would be useful to be able to break the single series RL element up into a ladder (or some more complex structure) of RLC elements. This capability will become more important as the signal speeds of the IC's rise. Therefore, this spec may need to be overhauled and updated at some time in the not-too-distant future. It is certainly true that the Full_Matrix format is a special case of both the Banded_Matrix and the Sparse_Matrix formats. It can be regarded as "syntactic sugar" which may or may not appeal to everyone. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: The classic electromagnetics text by Ramo, Whinnery and Van Duzer provides some nice background theory on how one goes about defining resistance, inductance and capacitance values for arbitrary structures, and also describes the high-frequency limitations to this approach. ******************************************************************************* From bala@parcom.ernet.in Mon Apr 18 05:47:55 1994 Return-Path: Received: from relay2.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06299; Mon, 18 Apr 94 05:47:55 PDT Received: from uucp4.uu.net by relay2.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwmdv25756; Mon, 18 Apr 94 08:45:38 -0400 Received: from sangam.UUCP by uucp4.uu.net with UUCP/RMAIL ; Mon, 18 Apr 1994 08:45:37 -0400 Received: from parcom.UUCP (uucp@localhost) by sangam.ncst.ernet.in (8.6.8.1/8.6.6) with UUCP id SAA01328 for ibis@vhdl.org; Mon, 18 Apr 1994 18:08:33 +0530 Received: from parcom.UUCP by iucaa (4.1/SMI-4.1) id AA02045; Mon, 18 Apr 94 18:10:30+050 Received: by parcom (4.1/SMI-4.1) id AA02905; Mon Apr 18 14:25:04 1994 (GMT + 0530) Date: Mon Apr 18 14:25:04 1994 (GMT + 0530) From: bala@parcom.ernet.in (S Balachandran) Message-Id: <9404180855.AA02905@parcom> Organisation: To: ibis@vhdl.org Subject: unsubscribe pls unsubscribe me bala@parcom.ernet.in From chuck_catto@rainbow.mentorg.com Mon Apr 18 10:47:23 1994 Return-Path: Received: from mgc.mentorg.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA08329; Mon, 18 Apr 94 10:47:23 PDT Received: from rainbow.mentorg.com by mgc.mentorg.com with SMTP (16.6/15.5+MGC-TD 2.20) id AA02404; Mon, 18 Apr 94 10:45:02 -0700 Received: from wv.mentorg.com by rainbow.mentorg.com with SMTP (15.11.1.6/15.5+MGC-TD 2.08) id AA26957; Mon, 18 Apr 94 10:45:00 -0700 Received: from em-sj01.MENTORG.COM by wv.mentorg.com (8.6.4/CF5.11R) id KAA07556; Mon, 18 Apr 1994 10:44:59 -0700 Received: from hpcatto.MENTORG.COM by em-sj01.MENTORG.COM (4.1/CF3.5) id AA11047; Mon, 18 Apr 94 10:45:34 PDT From: chuck_catto@rainbow.mentorg.com (Chuck Catto @ PCB x5506) Received: by hpcatto.MENTORG.COM (1.37.109.4/CF2.9) id AA15826; Mon, 18 Apr 94 10:51:08 -0700 Date: Mon, 18 Apr 94 10:51:08 -0700 Message-Id: <9404181051.ZM15824@hpcatto> X-Mailer: Z-Mail (3.0.0 15dec93) To: ibis@vhdl.org Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 pls unsubscribe me catto@mentorg.com From pzc@Cadence.COM Mon Apr 18 13:07:22 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09223; Mon, 18 Apr 94 13:07:22 PDT Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id NAA14213 for ; Mon, 18 Apr 1994 13:05:05 -0700 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma014159; Mon Apr 18 13:04:38 1994 Received: from valideast by cadence.Cadence.COM (5.61/3.14) id AA08666; Mon, 18 Apr 94 12:56:28 -0700 Received: from [158.140.113.10] by valideast (5.65+/1.5) id AA23560; Mon, 18 Apr 94 16:16:37 -0400 Date: Mon, 18 Apr 94 16:16:37 -0400 Message-Id: <9404182016.AA23560@valideast> To: ibis@vhdl.org From: pzc@cadence.com (Pawel Z. Chadzynski) Subject: unsubscribe pls unsubscribe me pzc@cadence.com From bward@dadhb1.ti.com Mon Apr 18 13:32:19 1994 Return-Path: Received: from lobby2b.ti.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09393; Mon, 18 Apr 94 13:32:19 PDT Received: from tilde.csc.ti.com by lobby2b.ti.com with SMTP (8.6.8.1/LAI-3.2) id PAA26137; Mon, 18 Apr 1994 15:27:51 -0500 Received: from isis.dadhb1.ti.com (dadhb1_0.sc.ti.com) by tilde.csc.ti.com id AA02105; Mon, 18 Apr 1994 15:29:34 -0500 Received: from emu.dadhb1.ti.com by isis.dadhb1.ti.com with SMTP (1.37.109.4/IDA1.4.4.1-Domain/OS) id AA03406; Mon, 18 Apr 94 15:29:19 -0500 From: Bob Ward Received: by emu.dadhb1.ti.com id ; Mon, 18 Apr 94 15:29:49 -0500 Date: Mon, 18 Apr 94 15:29:49 -0500 Message-Id: <9404182029.AA02578@emu.dadhb1.ti.com> To: ibis@vhdl.org Subject: Non monotonic currents from simulation Hi, all - I have just read Jon's report, and he has the right idea. But I would point out that also because of the nature of spice we can measure the Ib for each case, which in the real world we would be hard put to do accurately. So we _should_ be able to plug all this into the complete formulation of KCL equation around the transistor and still come out right. Right? If there is a flaw in what I just said feel quite free to point it out to me, since I too truth, etc. Thanks, Bob bward@dadhb1.ti.com or bward@neosoft.com From katz@blazng.enet.dec.com Mon Apr 18 14:56:00 1994 Return-Path: Received: from inet-gw-2.pa.dec.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09840; Mon, 18 Apr 94 14:56:00 PDT Received: from us1rmc.bb.dec.com by inet-gw-2.pa.dec.com (5.65/21Mar94) id AA12822; Mon, 18 Apr 94 14:48:56 -0700 Received: from blazng.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA07866; Mon, 18 Apr 94 17:49:08 -0400 Message-Id: <9404182149.AA07866@us1rmc.bb.dec.com> Received: from blazng.enet; by us1rmc.enet; Mon, 18 Apr 94 17:49:09 EDT Date: Mon, 18 Apr 94 17:49:09 EDT From: Barry Katz To: ibis@vhdl.org Cc: katz@decsim.enet.dec.com Apparently-To: ibis@vhdl.org, katz@decsim.enet.dec.com Subject: Re: Non-monotonic Pulldown curves Hi Jon and fellow IBISers, I just finished looking through your report. Everything you presented makes sense to me. In the results you presented it was clear that failure to compensate for the unequal bulk currents resulted in a nonmonotonic I-V curve. However, I'm still not 100% sure that non-monotonic pulldown I-V curves are invalid. I would like to hear what Arpad has to tell us -- specifically what are his bulk currents. Thanks for sending out the report, Barry- From spsun5!kt@aluxpo.att.com Mon Apr 18 18:27:23 1994 Return-Path: Received: from gw1.att.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11126; Mon, 18 Apr 94 18:27:23 PDT Received: from aluxpo!spsun5.UUCP by ig1.att.att.com id AA14079; Mon, 18 Apr 94 21:24:54 EDT From: spsun5!kt@aluxpo.att.com (Kenneth Tan) Received: from alux3.cnet.att.com by aluxpo (4.1/DCS-aluxpo-M2.2) id AA07543; Mon, 18 Apr 94 21:24:39 EDT Received: from spsun5.spsun4yp (spsun5.cnet.att.com) by alux3.cnet.att.com (4.1/DCS-aluxpo_client-S2.2) id AA22382; Mon, 18 Apr 94 21:24:35 EDT Received: from spsun3.spsun4yp by spsun5.spsun4yp (4.1/SMI-4.1) id AA21658; Tue, 19 Apr 94 09:27:40 SST Date: Tue, 19 Apr 94 09:27:40 SST Original-From: aluxpo!spsun5!kt (Kenneth Tan) Message-Id: <9404190127.AA21658@spsun5.spsun4yp> To: aluxpo!ibis@vhdl.org Subject: unsubscribe pls unsubscribe me kenneth.s.y.tan@att.com thank you kenneth From bward@sugar.NeoSoft.COM Mon Apr 18 19:15:47 1994 Return-Path: Received: from sugar.NeoSoft.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11477; Mon, 18 Apr 94 19:15:47 PDT Received: by sugar.NeoSoft.COM id AA19469 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Mon, 18 Apr 1994 21:12:50 -0500 Message-Id: <199404190212.AA19469@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: Correction to subtraction of IV curves Date: Mon, 18 Apr 94 21:12:46 CDT All - When do my algebra, I get a result like the following for the "subtraction" of two IV curves in the presence of non-equal bulk currents: Following Jon's nomenclature in his paper ... let Is be the transistor current. Then -Is1 = Id1 - 2*Id2 + Ib1 Since it seems a good assumption is that Is2 is indeed zero and so Id2 = Ib2... Seem like a reasonable correction term? This is still not a very bad expression to evaluate, as long as it seems right with the world. Comments? Thanks, Bob bward@neosoft.com or bward@dadhb1.ti.com From Will_Hobbs@ccm2.jf.intel.com Mon Apr 18 20:51:17 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11973; Mon, 18 Apr 94 20:51:17 PDT Received: from ccm.jf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pt6o1-000MNuC; Mon, 18 Apr 94 20:49 PDT Received: by ccm.jf.intel.com (ccmgate 3.0) Mon, 18 Apr 94 20:49:00 PST Date: Mon, 18 Apr 94 20:49:00 PST From: Will Hobbs Message-Id: <940418204900_1@ccm.jf.intel.com> To: ibis@vhdl.org Cc: Will_Hobbs@ccm2.jf.intel.com Subject: ibis-request To minimize traffic on the network, if you wish to unsubscribe to this reflector, send the request to ibis-request@vhdl.org rather than the ibis reflector. Thanks. Will Hobbs Intel Corp. From bward@sugar.NeoSoft.COM Tue Apr 19 14:32:55 1994 Return-Path: Received: from sugar.NeoSoft.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA21777; Tue, 19 Apr 94 14:32:55 PDT Received: by sugar.NeoSoft.COM id AA29169 (5.65c/IDA-1.4.4 for ibis@vhdl.org); Tue, 19 Apr 1994 16:29:59 -0500 Message-Id: <199404192129.AA29169@sugar.NeoSoft.COM> From: bward@sugar.NeoSoft.Com (Bob Ward) X-Mailer: SCO System V Mail (version 3.2) To: ibis@vhdl.org Subject: Followup on correction term for transistor current Date: Tue, 19 Apr 94 16:29:54 CDT Hi! As jon points out Arpad is using a correction term for non tristating buffers, I have thought such a term is possible, I need to convince myself of it yet. And unfortunately I fully agree with Jon that it is ruddy hard to measure Ib on a real transistor on a real chip! Sure shoots the stuffin's out of a nice elegant correction term, doesn't it. My request was mostly a sanity check, but it may still have use as things go on. Thanks, Bob bward@neosoft.com or bward@dadhb1.ti.com From katz@blazng.enet.dec.com Wed Apr 20 06:54:53 1994 Return-Path: Received: from inet-gw-2.pa.dec.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04780; Wed, 20 Apr 94 06:54:53 PDT Received: from us1rmc.bb.dec.com by inet-gw-2.pa.dec.com (5.65/21Mar94) id AA01405; Wed, 20 Apr 94 06:40:35 -0700 Received: from blazng.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA09045; Wed, 20 Apr 94 09:40:50 -0400 Message-Id: <9404201340.AA09045@us1rmc.bb.dec.com> Received: from blazng.enet; by us1rmc.enet; Wed, 20 Apr 94 09:40:51 EDT Date: Wed, 20 Apr 94 09:40:51 EDT From: Barry Katz To: ibis@vhdl.org Cc: katz@blazng.enet.dec.com Apparently-To: ibis@vhdl.org Subject: Re: Nonmonotonic Pulldown I-V curves After further review of Jon's report and some addition experimentation on my part I think I may have identified a problem with the presented results. In my experiments, I found that the bulk currents were on the order of picoAmps and that the difference on the order of femptoAmps. This leads me to believe that the currents shown in Figure 5 of the report are in fact the parasitic diode currents not the transistor Bulk currents. This may just be a terminology issue. However, something does appears to be inconsistent because even if we were talking about diode currents the difference in these diode currents should still be zero. This is based on the fact the the transistor bulk currents are effectively zero and the current through the diode is voltage dependent. Therefore, since both the "on" and "off" cases have the same sweep, the difference between the currents for these cases will be zero. This is regardless of your definition of i_bulk. Comments anyone? Jon, can you put the spice decks corresponding to your report on the reflector? Barry- My test structure is shown below. i_drain --------- <--- | | ---------------------------------|Ammeter| SWEEP | | | | | | |i_clamp --------- | | | | i_g ---- i_bulk --- V | --> | | <--- ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | | | | ( - ) | |i_s | | | \ / | V | | | | | | | | --- --- --- --- --- - - - - - I think Jon's test structure was as follows i_drain --------- <--- | | ---------------------------------|Ammeter| SWEEP | | | | | | |i_clamp --------- | | | | i_g ---- --- V | --> | | ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | ------------| | ( - ) | |i_s ------- | | \ / | V |Ammeter| | i_bulk | | | ------- V | --- --- | --- - - --- - - From jonp@qdt.com Wed Apr 20 10:17:26 1994 Return-Path: Received: from relay2.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06226; Wed, 20 Apr 94 10:17:26 PDT Received: from uucp4.uu.net by relay2.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwmlx15733; Wed, 20 Apr 94 13:15:07 -0400 Received: from qdt.UUCP by uucp4.uu.net with UUCP/RMAIL ; Wed, 20 Apr 1994 13:15:07 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00645; Wed, 20 Apr 94 09:47:10 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA28067; Wed, 20 Apr 94 09:47:10 PDT Date: Wed, 20 Apr 94 09:47:10 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404201647.AA28067@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA24696; Wed, 20 Apr 94 09:47:16 PDT To: katz@blazng.enet.dec.com Cc: ibis@vhdl.org In-Reply-To: Barry Katz's message of Wed, 20 Apr 94 09:40:51 EDT <9404201340.AA09045@us1rmc.bb.dec.com> Subject: Nonmonotonic Pulldown I-V curves If I understand your drawing correctly it does not properly reflect my test structure. My test circuit is as shown in Figure 1 and 2 of the memo. There was no clamp diode, just one CMOS transistor. We simulated bulk current (Ib) (as shown) in the Amp range. jonp From katz@blazng.enet.dec.com Wed Apr 20 10:37:41 1994 Return-Path: Received: from inet-gw-2.pa.dec.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06383; Wed, 20 Apr 94 10:37:41 PDT Received: from us1rmc.bb.dec.com by inet-gw-2.pa.dec.com (5.65/21Mar94) id AA16983; Wed, 20 Apr 94 10:25:23 -0700 Received: from blazng.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA18089; Wed, 20 Apr 94 13:25:21 -0400 Message-Id: <9404201725.AA18089@us1rmc.bb.dec.com> Received: from blazng.enet; by us1rmc.enet; Wed, 20 Apr 94 13:25:29 EDT Date: Wed, 20 Apr 94 13:25:29 EDT From: Barry Katz To: ibis@vhdl.org Cc: katz@decsim.enet.dec.com Apparently-To: ibis@vhdl.org, katz@decsim.enet.dec.com Subject: Re: Nonmonotonic Pulldown I-V curves Sorry if this message gets posted twice. After further review of Jon's report and some addition experimentation on my part I think I may have identified a problem with the presented results. In my experiments, I found that the bulk currents were on the order of picoAmps and that the difference on the order of femptoAmps. This leads me to believe that the currents shown in Figure 5 of the report are in fact the parasitic diode currents not the transistor Bulk currents. This may just be a terminology issue. However, something does appears to be inconsistent because even if we were talking about diode currents the difference in these diode currents should still be zero. This is based on the fact the the transistor bulk currents are effectively zero and the current through the diode is voltage dependent. Therefore, since both the "on" and "off" cases have the same sweep, the difference between the currents for these cases will be zero. This is regardless of your definition of i_bulk. Comments anyone? Jon, can you put the spice decks corresponding to your report on the reflector? Barry- My test structure is shown below. i_drain --------- <--- | | ---------------------------------|Ammeter| SWEEP | | | | | | |i_clamp --------- | | | | i_g ---- i_bulk --- V | --> | | <--- ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | | | | ( - ) | |i_s | | | \ / | V | | | | | | | | --- --- --- --- --- - - - - - I think Jon's test structure was as follows i_drain --------- <--- | | ---------------------------------|Ammeter| SWEEP | | | | | | |i_clamp --------- | | | | i_g ---- --- V | --> | | ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | ------------| | ( - ) | |i_s ------- | | \ / | V |Ammeter| | i_bulk | | | ------- V | --- --- | --- - - --- - - From katz@blazng.enet.dec.com Wed Apr 20 11:58:35 1994 Return-Path: Received: from inet-gw-2.pa.dec.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06932; Wed, 20 Apr 94 11:58:35 PDT Received: from us1rmc.bb.dec.com by inet-gw-2.pa.dec.com (5.65/21Mar94) id AA22055; Wed, 20 Apr 94 11:47:13 -0700 Received: from blazng.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA20609; Wed, 20 Apr 94 14:47:17 -0400 Message-Id: <9404201847.AA20609@us1rmc.bb.dec.com> Received: from blazng.enet; by us1rmc.enet; Wed, 20 Apr 94 14:47:19 EDT Date: Wed, 20 Apr 94 14:47:19 EDT From: Barry Katz To: jonp@qdt.com (jon powell 20-apr-1994 1347 -0500) Cc: ibis@vhdl.org, katz@decsim.enet.dec.com Apparently-To: jonp@qdt.com, ibis@vhdl.org, katz@decsim.enet.dec.com Subject: Re: Nonmonotonic Pulldown I-V curves Jon, It is my understanding that you were attempting to separate the bulk diode currents from the pulldown I-V curves. Therfore, I'm assuming that the one CMOS transistor in the report must have the parasitic diodes internal to its model. Is this correct? This would explain the huge (Amp range) bulk currents. If it is, then isn't the test circuit I have drawn representative of what you were modeling in the report(ignoring the parasitic diode from source to bulk since it is shorted). My Id is the same as your Id etc. I guess my question still is, given that you agree with everything I have said above, how can the bulk currents between the "on" and "off" cases be different? I'm assuming that Ib = i_parasitic_diode and the diode current is a function of the sweep voltage. Id --------- <--- | | -------------------------------------|Ammeter| SWEEP | | | | | | |i_parasitic --------- | | | diode | ---- --- V | | | ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | ------------| | ( - ) | |Is ------- | | \ / | V |Ammeter| | Ib | | | ------- V | --- --- | --- - - --- - - Barry Katz- From Arpad_Muranyi@ccm.fm.intel.com Wed Apr 20 13:45:51 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07901; Wed, 20 Apr 94 13:45:51 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0ptj5t-000MNoC; Wed, 20 Apr 94 13:42 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Wed, 20 Apr 94 13:42:01 PST Date: Wed, 20 Apr 94 13:42:01 PST From: Arpad Muranyi Message-Id: <940420134201_1@ccm.hf.intel.com> To: katz@blazng.enet.dec.com Cc: ibis@vhdl.org Subject: Re[2]: Nonmonotonic Pulldown I-V curves They are different, because the ON transistor adds a parallel (resistive) path with its channel to the calmping diode. Arpad Jon, It is my understanding that you were attempting to separate the bulk diode currents from the pulldown I-V curves. Therfore, I'm assuming that the one CMOS transistor in the report must have the parasitic diodes internal to its model. Is this correct? This would explain the huge (Amp range) bulk currents. If it is, then isn't the test circuit I have drawn representative of what you were modeling in the report(ignoring the parasitic diode from source to bulk since it is shorted). My Id is the same as your Id etc. I guess my question still is, given that you agree with everything I have said above, how can the bulk currents between the "on" and "off" cases be different? I'm assuming that Ib = i_parasitic_diode and the diode current is a function of the sweep voltage. Id --------- <--- | | -------------------------------------|Ammeter| SWEEP | | | | | | |i_parasitic --------- | | | diode | ---- --- V | | | ^ | --| | |-------- / \ | | | | | --- | / \ ---- | | | ( + ) | | ------------| | ( - ) | |Is ------- | | \ / | V |Ammeter| | Ib | | | ------- V | --- --- | --- - - --- - - Barry Katz- From 71436.1314@CompuServe.COM Thu Apr 21 00:41:05 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from arl-img-2.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11947; Thu, 21 Apr 94 00:41:05 PDT Received: from localhost by arl-img-2.compuserve.com (8.6.4/5.930129sam) id DAA16314; Thu, 21 Apr 1994 03:38:47 -0400 Date: 21 Apr 94 03:35:57 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Bird 11.2 (new revision) Message-Id: <940421073557_71436.1314_HHB36-1@CompuServe.COM> From: Kellee Crisafulli To: IBIS world at large and growing Re: Bird 11.2 modified per inputs from Bob Ross and last meeting Date: April 21, 1994 I have made the changes per inputs from Bob Ross and per feedback from the last IBIS meeting as retold to me by Bob. See the end of this file for change discussion. Change 2: 'IF-ELSE' conditions were modified to add equal Change 3: Added equal condition to verification requirment Change 4: Removed requirment to stop IBIS_CHK on first error. Sorry I missed the last meeting, UNCLE SAM was calling. I was one of those procrasting people still working on my personal TAXES at the last minute. ******************************************************************************* ******************************************************************************* Buffer Issue Resolution Document (BIRD) BIRD ID#: 11.2 ISSUE TITLE: Improving common error detection in IBIS_CHK program. REQUESTOR: Kellee Crisafulli, HyperLynx Inc. DATE SUBMITTED: 03-28-94 DATE REVISED: 04-21-94 DATE ACCEPTED BY IBIS OPEN FORUM: TBD ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: Several common problems with IBIS models are not detected with the present version of IBIS_CHK. Two main problems include: 1) Incorrect 'I'(current) signs in the V/I tables. 2) Pullup and POWER_clamp V/I tables are not VCC relative. This BIRD is directed at problem 1 only. A 2nd separate BIRD will be generated to address problem 2. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: The following changes apply to version 1.1 and forward versions of the IBIS_CHK program and including testing of some parameters for BIRD 7.2 for ECL model types *************************************************************************** Change 1- Add verbage on current direction. *************************************************************************** Keywords: [Pullup], [Pulldown], [GND_clamp], [POWER_clamp] Required: Yes, if they exist in the device Description: The data points under these keywords define the V/I curves of the pulldown and pullup structures of an output buffer and the V/I curves of the clamping diodes connected to the GND and the POWER pins, respectively. Currents are considered positive when their direction is into the component. *************************************************************************** Change 2- Add detection to IBIS_CHK program for V/I table 'I' sign errors. *************************************************************************** For each of the following V/I tables: Pullup, Pulldown, POWER_clamp, GND_clamp 1) Find the minimum and maximum voltage points (Vmin, Vmax) in the table. 2) IF:The current in the TYPICAL column corresponding to Vmax is less than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have decreasing current. ELSE IF:The current in the TYPICAL column corresponding to Vmax is greater than the current in the TYPICAL column corresponding to Vmin than the table is assumed to have increasing current. ELSE: The table is assumed to have equal current." Note: This works for all cases of discontinuities unless the magnitude of discontinuity is such that this model is in all probability competely unrealistic. Examples: *** example with non-monotonic data at the end point V: I: 0.00 0.0 4.90 50.0ma 4.91 49.9ma 4.93 56.7ma 5.00 3.0ma -> V/I table has increasing current (3.0 > 0) Vmax = 5.0, I =3.0mA Vmin = 0.0, I =0.0 *** example with negative to positve voltages with negative first V: I: -5.00 -0.1ma 0.00 0.0 5.00 100.0ma -> V/I table has increasing current (100 > -0.1) Vmax = 5.0, I=100mA Vmin = -5.0, I=-0.1mA *** example with table data entered postive voltages first V: I: 5.00 10.1ma 0.00 0.0 -5.00 -10.1ma -> V/I table has increasing current (10.1 > -10.1) Vmax = 5.0, I=10.1mA Vmin = -5.0, I=-10.1mA *** example with only two entrys V: I: 0.00 0.0 -5.00 10.1ma -> V/I table has decreasing current (0 < 10.1) Vmax = 0.0, I=0 Vmin = -5.0, I=10.1mA *** ECL example [Pullup] Voltage I(typ) I(min) I(max) 0.0 0 0 0 0.7 -0.2m -0.2m -0.2m 0.73 -0.4m -0.4m -0.4m 0.75 -0.8m -0.8m -0.8m 0.76 -1.2m -1.2m -1.2m 0.77 -1.6m -1.6m -1.6m 0.8 -4.4m -4.4m -4.4m 0.82 -7.6m -7.6m -7.6m 0.85 -14.2m -14.2m -14.2m 0.9 -30.0m -30.0m -30.0m 1.0 -58.0m -50.0m -68.0m -> V/I table has decreasing current ( -58 < 0) Vmax = 1.0, Ityp=-58mA Vmin = 0, Ityp=0 [Pulldown] Voltage I(typ) I(min) I(max) 0.0 0 0 0 1.6 -0.2m -0.2m -0.2m 1.62 -0.4m -0.4m -0.4m 1.64 -0.6m -0.6m -0.6m 1.65 -0.8m -0.8m -0.8m 1.66 -1.2m -1.2m -1.2m 1.67 -1.6m -1.6m -1.6m 1.68 -2.4m -2.4m -2.4m 1.69 -3.2m -3.2m -3.2m 1.70 -4.4m -4.4m -4.4m 1.72 -7.4m -7.4m -7.4m 1.75 -14.2m -14.2m -14.2m 1.8 -30.5m -30.5m -30.5m 1.9 -65.0m -60.0m -75.0m -> V/I table has decreasing current ( -65 < 0) Vmax = 1.9, Ityp=-65mA Vmin = 0.0, Ityp= 0 *** An abreviated INTEL model for a CMOS output |**************************************************************************** [Pulldown] | Voltage I(typ) I(min) I(max) -5.00V -38.70mA -29.47mA -51.22mA -1.00V -24.88mA -19.18mA -32.90mA -0.50V -14.35mA -11.06mA -19.05mA 0.00V -11.84pA -554.66pA -11.03pA 100.00mV 3.20mA 2.47mA 4.27mA 200.00mV 6.24mA 4.80mA 8.30mA 4.90V 38.68mA 29.45mA 51.18mA 5.00V 38.70mA 29.47mA 51.22mA 10.00V 39.96mA 30.37mA 53.06mA -> V/I table increasing [GND_clamp] | Voltage I(typ) I(min) I(max) -5.00V -680.00mA NA NA -1.10V -75.50mA NA NA -600.00mV -950.00uA NA NA -500.00mV -78.00uA NA NA -200.00mV 0.00pA NA NA -100.00mV 0.00pA NA NA 0.00V 0.00pA NA NA 5.00V 0.00pA NA NA -> V/I table increasing (0 > -680) [Pullup] | Voltage I(typ) I(min) I(max) -5.00V 38.14mA 27.33mA 54.76mA -4.50V 37.49mA 26.87mA 53.79mA -1.00V 17.13mA 12.81mA 23.55mA -0.50V 9.26mA 6.96mA 12.66mA 0.00V 13.57pA 613.51pA 11.04pA 100.00mV -1.96mA -1.48mA -2.67mA 200.00mV -3.87mA -2.92mA -5.27mA 500.00mV -9.26mA -6.96mA -12.66mA 1.80V -26.79mA -19.79mA -37.25mA 1.90V -27.74mA -20.46mA -38.64mA 4.60V -37.62mA -26.97mA -54.00mA 4.70V -37.76mA -27.06mA -54.20mA 5.00V -38.14mA -27.33mA -54.76mA 10.00V -44.52mA -33.72mA -61.15mA -> V/I table decreasing [POWER_clamp] | Voltage I(typ) I(min) I(max) -5.00V 1.05A NA NA -1.10V 79.00mA NA NA -1.00V 54.00mA NA NA -900.00mV 29.00mA NA NA -800.00mV 10.40mA NA NA -200.00mV 0.00uA NA NA -100.00mV 0.00uA NA NA 0.00V 0.00pA NA NA -> V/I table decreasing 3) IF the model is any of the following types:(Input_ECL, Output_ECL, I/O_ECL) { Verify that: - Pullup V/I table has equal or decreasing current - POWER_clamp V/I table has equal or decreasing current - Pulldown V/I table has equal or decreasing current - GND_clamp V/I table has equal or increasing current } ELSE { Verify that: - Pullup V/I table has equal or decreasing current - POWER_clamp V/I table has equal or decreasing current - Pulldown V/I table has equal or increasing current - GND_clamp V/I table has equal or increasing current } Note: This specifically allows constant current generators and 0 current tables. 0 current tables may be used to indicate table is unused. 4) If any table verification fails report the following error message: 'Error found in xxx V/I table at line number nnn!'. Where xxx is one of the following Pullup, Pulldown, POWER_clamp, GND_clamp. Where nnn is the line number. *************************************************************************** Change 3- Add a header comment statement at the TOP of the IBIS_CHK program to insure that new changes to the IBIS_CHK program donot break tests that worked in old MAJOR versions. This approach makes the program larger however it insures the parser always works the same on older versions of IBIS. This apporach uses more memory, but has the reward of low maintaining costs. The IBIS_CHK program is very small and would not be effected by this until many revisions have occured. *************************************************************************** NOTICE TO ANY PERSON MODIFING THIS PROGRAM! ------------------------------------------- This program SHALL NOT BE MODIFIED unless there is an associated IBIS BIRD. Said BIRD shall be agreed upon by IBIS committee vote. Only the currently elected IBIS_CHK 'czar and programmer' is allowed to modify the source code. The present CZAR is Jon Powell (April 1994). The IBIS committee may also hire programmers from time to time to make major changes to the source code. Note: Source licensees are free to modify their own copies of this source code in any way they choose. Source licensees shall not redistribute the source code modified or otherwise. Source licensing is available from the IBIS open forum. The IBIS open forum is non-profit. The code for each MAJOR version of the IBIS_CHK program SHALL NOT BE MODIFIED when adding code for the next version of the IBIS specification. Instead completely new code for all functions and features shall be created. This may require duplication of numerous functions. Each function shall be preceded by VXX_ where XX is the MAJOR version of the IBIS specification which is being parsed and tested. A MAJOR version would for example be 1.x going to 2.x. A MINOR version would for example be 1.1 to 1.2. Functions using the above syntax would look as follows: V01_GetValue MINOR revisions DO NOT required new code. Startup code shall be provided at the top of the program which reads the version number from the IBIS file and runs the portion of the program corresponding to that MAJOR version. Code which is used only by the program startup function is not duplicated. ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Change 1) Suggested from inputs of several people in Email and at the at previous IBIS meetings. Change 2) Defective IBIS models are slipping through the IBIS_CHK program. A method for determining sign errors in V/I table was determined based on inputs from several people including: Kellee Crisafulli, HyperLynx Jon Powell, Quad Design Arpad, Intel Bob Ward, TI Bob Ross, Interconnectix Maah Sango, Contec I reviewed all the comments that have been submitted and I believe this method will work with all conditions mentioned so far. Change 3) I am proposing a method of insuring that future IBIS_CHK modifications donot effect the parsing of older IBIS files. This only applies to MAJOR revisions in the specification, like 2.0 comming up. This would not apply to this update, it would however be added to the program header information now and would apply to all future MAJOR updates to the IBIS specification. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: Comments about EMAIL leading up to this BIRD -------------------------------------------- From: Jon Powel, qdt Cases that will not work for proposed algorithm V: I: 0.0 0.0 3.5 50.0 3.51 49.9 3.52 49.8 3.53 49.7 5.0 100.0 any OC any OD If current is not negative at GND for the pullup then it cannot pullup? (except for ECL OC etc?). Action: problems fixed in BIRD 11.0 ****************** From: Arpad, Intel What happens if there are equal number of increases and decreases in a curve? Most of the curves I am generating lately do that and I do not think I am doing it wrong. Action: problems fixed in BIRD 11.0 ******************** Bob Ward, TI I think the proposed method of current sign determination might run into trouble in at least two cases. One is when there are exactly the same number of rising and falling segments. The other is the same problem one runs into testing for monotonicity of the independent variable. That problem is that very small oscillations occur on the "flat" part of a numerically generated curve, not so much because they are real, but because of the nature of small numbers, finite precision, and floating point round off. Action: Problems fixed in BIRD 11.0 ****************************** Bob Ross, Interconnectix, Inc. If this proposal is adopted, it would apply to just IBIS Version1.1. The polarity rules do not comply with proposed IBIS extensions BIRDS 3 and 4 for ECL type devices. For ECL type devices, the polarities of both the Pullup and Pulldown tables will go in the same (decreasing) direction because BOTH tables are tabulated referenced to Vcc using Vtable = Vcc - Vout. I am sure this will become another area of confusion, justifying a test. Action: Problem fixed BIRD 11.0 ************************** Maah Sango, Contec Microelectronics USA Inc 2. I agree with Bob Ross that the proposed scheme for enforcing data integrity will not work for ECL, nor for a few other device types. (See item 3 of the proposal). Either the "pullup" or the "pulldown" data for the ECL and other device types will violate these requirements. Action: Problem fixed Bird 11.0 3. The proposed scheme, item 3, will not always work even for CMOS unless we use only the magnitudes of the currents. Existing data for ageing (old) devices is sometimes presented with positive currents and sometimes with negative currents for CMOS pullup devices. Action: Problem fixed Bird 11.0 4. I am not sure that checking only the two end points will always guarantee the conclusions we are assuming here. Current(I) data in between these two points may increase or decrease and still be perfectly valid, particularly if we think of device types other than CMOS. Action: Numerous examples cited, none found that present a problem ******************************* Arpad, Intel If we JUST want a polarity checker for the MOST COMMON error, I have another most common error to check for: VCC-relative! That needed more explaining than the polarity of the current in my experience, and I have seen more people being confused about that. Should that also be checked for then? Action: Another Bird needs to be generated separate from Bird 11 ******************************************************************************* Changes from the April-1-94 IBIS meeting BIRD 11, IBIS_CHK Changes Kellee Crisafulli proposes three changes in this BIRD, each related to the sign of VI table data, which has proven to be a common pitfall among new modelers. First, the BIRD proposes adding a comment to the IBIS specification discussing the sign of VI table data; second, add checking to ibis_chk for the correct sign, using the algorithm tuned through reflector feedback; and third, add a note to the ibis_chk source saying a BIRD is required to change the source. Proposed changes 1 and 3 appear OK to group, with the additional comment that source licensees are free to modify their own source, but not to post the result. Only the ibis_chk czar (Jon Powell) can post modified versions of ibis_chk, and that requires a ratified BIRD to initiate. AR:Kellee, change the proposed ibis_chk notice to indicate that it is OK to change your own source code, but not the global one without a supporting BIRD. Action: Done Regarding change 2, there is controversy about the sign of the ECL example. Kellee pulled the example out of the IBIS V1.1 spec, which was a CMOS example, and indicated that if this was an ECL example then there would be a sign error because for ECL pulldown, VI is Vcc-V per BIRD 4. Kellee feels that right thing to do is to change the sign and use ECL type data and present a correct ECL table, but doesn't have ECL data. Kumar has ECL data which he offered to supply for inclusion in the BIRD. AR:Kumar, post ECL model to reflector, Kellee, use that data in the BIRD. Action: I have incorporated the model. AR Kellee, Two people noted that the directions of the current tests for the ECL were wrong. Kellee thought they were correct during the phone conversation. Action: I was wrong, and have changed them to correct the problem. ******************************************************************************* Changes April 15 meeting and inputs from Bob Ross, Interconnectix Inc. Will tables composed of only 0 mA entries or of only constant current entries be flagged as an error in Version 2.0? They are acceptable in Version 1.1, and could be useful to get around some Model_type omissions and do some (beyond IBIS) constant current source modeling or biasing of tables modeling. Input at the meeting 4-15-94 indicated that 0mA and constant current should be allowed. Change 2, section 4) states: If any table moves in the wrong direction report the following error message: 'Error found in xxx V/I table at line number nnn!'. Where xxx is one of the following: Pullup, Pulldown, POWER_clamp, GND_clamp. Where nnn is the line number. Note: It is acceptable to stop the parser after the first line found with this error." I could technically be very happy with the wording as is, and yet we may have entirely different expectations. To me "If any table MOVES in the wrong direction ..." means an error is NOT reported if there is NO table movement - e.g., NO error is reported if the tests reveal EQUAL currents. I believe you really intended "If any table verification fails ...". I would prefer that the IBIS_CHK parser not stop, but continue to check the file for all errors (including other occurances of this error). So I would delete the "Note" entirely. AR Kellee, Modify the test to allow constant current and 0mA as valid. Action: I have made changes in the V/I table tests to allow 0mA and constant current. AR Kellee, Clarify wording and remove requirment to stop IBIS_CHK on first error. Action: Modified wording to say "If any table verification fails..." Deleted the Note requiring the parser to stop after the first error line. ************************************************************************************* From bob@icx.com Fri Apr 22 17:41:18 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04301; Fri, 22 Apr 94 17:41:18 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA02248 for ; Fri, 22 Apr 94 20:18:40 -0400 Date: Fri, 22 Apr 94 17:14:45 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA06086; Fri, 22 Apr 94 17:14:45 PDT Message-Id: <9404230014.AA06086@icx.com> To: ibis@vhdl.org Subject: NEW EGG5.3 To Eric Bracken, C. Kumar and IBIS Committee BIRD5.2 is suitable as an extension to IBIS Version 1.1, but I feel it needs some additional columns to be FULLY compatible with BIRD3 which supports up to 4 DIFFERENT Voltage References. I would like to propose an extension tentatively designated "EGG5.3". The extension consists of two additional, OPTIONAL columns for specifically designating [GND_clamp] and [POWER_clamp] connections. They will be rarely used. But in cases where the [PULLUP] is referenced to 3.3V, and the [POWER_clamp] to 5V, this extension would be useful. Also, there may need to be some clarification for ECL model types. Using BIRD5.2 as a basis and showing it completely for reference, the only changes consist of "optional extension" and "explanation of optional extension" in the STATEMENT OF THE RESOLVED SPECIFICATIONS section. Do you have any comments? Bob Ross, Interconnectix, Inc. "EGG5.3" USING BIRD 5.2 for format ***************************************************************************** ***************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 5.2 ISSUE TITLE: Pin Mapping for Ground Bounce Simulation REQUESTOR: J. Eric Bracken, Performance Signal Integrity, Inc. and C. Kumar, Cadence Design Systems, Inc. DATE SUBMITTED: 6 December 1993 DATE REVISED: 17 December 1993 DATE ACCEPTED BY IBIS OPEN FORUM: Jan 7, 1994 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: To be better able to simulate the ground bounce effect, it is necessary to know which pins of a part are connected to a common ground or power bus. This BIRD provides a simple mechanism for identifying these common buses. This improves the simulation of ground bounce by limiting the noise effects of switching drivers to other drivers and receivers on the same bus. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Each power and ground bus is given a unique name which must not exceed 20 characters. An additional OPTIONAL keyword, [Pin_Mapping], is added to the specification. Following this keyword is information indicating to which power and ground buses a given driver or receiver is connected. As an example of the new format, say that we have two ground buses (named GNDBUS1 and GNDBUS2) which each bus together 3 pins: Pins: 11 12 13 21 22 23 + + + + + + | | | | | | | | | | | | Buses: +-----+------+-----> to a few +-----+------+-----> to a few GNDBUS1 drivers GNDBUS2 more and two similarly structured power buses (PWRBUS1 and PWRBUS2): Pins: 31 32 33 41 42 43 + + + + + + | | | | | | | | | | | | Buses: +-----+------+-----> to a few +-----+------+-----> to a few PWRBUS1 drivers PWRBUS2 more We assume that the "signal name" for pins 11-13 and 21-23 are all "GND", and that the names for pins 31-33 and 41-43 are all "VDD". The new [Pin_Mapping] specification would be as follows: [Pin_Mapping] gnd pwr 1 GNDBUS1 PWRBUS1 2 GNDBUS2 PWRBUS2 ..... .... .... 11 GNDBUS1 NC 12 GNDBUS1 NC 13 GNDBUS1 NC ..... 21 GNDBUS2 NC 22 GNDBUS2 NC 23 GNDBUS2 NC ..... 31 NC PWRBUS1 32 NC PWRBUS1 33 NC PWRBUS1 ..... 41 NC PWRBUS2 42 NC PWRBUS2 43 NC PWRBUS2 Explanation: In the above example, the first column contains a pin number; each pin number must match one of the pin numbers declared previously in the [Pin] section of the IBIS file. The second column, "gnd", designates the ground bus connection for that pin; similarly, the third column, "pwr", designates the power bus connection. For a GND pin, such as pins 11-13 and 21-23, the entry in the "gnd" column indicates the ground bus to which it is attached. The entry in the "pwr" column is NC because there is, of course, no connection to any power bus. The situation for a POWER pin (e.g. pins 31-33 and 41-43) is analogous. The above example also contains two ordinary signal pins (pins 1 and 2). For these pins, the entries in the "gnd" and "pwr" columns designate the power and ground buses to which their buffer models are connected. Thus, for pin 1 there is an instance of the associated I-V model which connects to PWRBUS1 and GNDBUS1. Pin 2 creates an instance of an I-V model which connects to PWRBUS2 and GNDBUS2. If the [Pin_Mapping] keyword is present, then the bus connections for EVERY pin listed in the [Pin] section must be given. If a pin has no connection, then both the "pwr" and "gnd" entries for it may be NC. Optional Extension: [Pin_Mapping] gnd pwr gnd_clamp pwr_clamp 1 GNDBUS1 PWRBUS1 2 GNDBUS2 PWRBUS2 3 GNDBUS1 PWRBUS1 GNDCLMP PWRCLAMP 4 GNDBUS2 PWRBUS2 GNDCLMP PWRCLAMP ..... .... .... 11 GNDBUS1 NC 12 GNDBUS1 NC 13 GNDBUS1 NC ..... 21 GNDBUS2 NC 22 GNDBUS2 NC 23 GNDBUS2 NC ..... 31 NC PWRBUS1 32 NC PWRBUS1 33 NC PWRBUS1 ..... 41 NC PWRBUS2 42 NC PWRBUS2 43 NC PWRBUS2 ..... 51 GNDCLMP NC 52 NC PWRCLMP Explanation of Optional Extension: This extension illustrates a hypothetical situation where the clamping circuitry is connected to different rails than those of the pullup and pulldown tables. Pins 51 and 52 are hypothetical clamping supplies, and their attachments are shown at pins 3 and 4. While the nomenclature can lead to some potential confusion, the intended operation is according to this interpretation: The "gnd" column contains the power connection for the [Pulldown] table for non-ECL type [Models]. This is also the power connection for the [GND_clamp] table unless overriden by a specification in the gnd_clamp column. The "pwr" column contains the power connection for the [Pullup] table and for ECL type models, the [Pulldown] table. This is also the power connection for the [POWER_clamp] table unless overriden by a specification in the pwr_clamp column. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: One of the more serious causes of noise in digital circuits is the voltage spike created on a device's power or ground line due to the sudden switching of a very large current into that line. This can occur when other drivers share a power or ground bus with the device in question. Most modern packages incorporate many different power and ground pins and then internally connect them to several different power and ground buses. The drivers and receivers are carefully assigned to certain buses to minimize the potential impact of switching noise on the part's operation. Without a knowledge of this device-to-bus assignment, it becomes impossible to perform even a first-order simulation of the ground bounce effect. One cannot know which pins will influence any given driver or receiver. The proposed BIRD attempts to rectify this situation, while still observing an 80-character-per-line limit. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: Please note that, in order to make the simulation possible, the modelling engineer must specify the (self-)resistance and inductance for each power and ground pin in the model. The present BIRD does not address any inductive or resistive drops along the internal bus--these are assumed to be zero (the bus is treated as a perfect short between pins). Under this assumption, the equivalent impedance seen by the drivers on the bus can be found by taking the parallel combination of the series R-L impedances for each of the GND or POWER pins connected to the bus. Bird 5.2 has been issued in response to comments from the Forum members over the use of the term "NA" in Bird to indicate the lack of a connection. NA = "not available," which would have caused confusion. This version of the Bird has been updated to use "NC" (= "no connection") instead. Otherrwise, there are no changes from Bird 5.1. ****************************************************************************** From bob@icx.com Fri Apr 22 20:28:35 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05227; Fri, 22 Apr 94 20:28:35 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA00513 for ; Fri, 22 Apr 94 23:18:05 -0400 Date: Fri, 22 Apr 94 19:55:49 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA06326; Fri, 22 Apr 94 19:55:49 PDT Message-Id: <9404230255.AA06326@icx.com> To: ibis@vhdl.org Subject: BIRD9.2 Hello IBIS members: This is a further evolution of a terminator specification based on some input at the April 15, 1994 Forum. The [Rseries] has been removed because of technical complications based on its need for two connection points. The whole structure no longer can be used with [Pullup] or [Pulldown] and [Ramp]. To Differentiate these structures from others, a Model_type parameter "Discrete" is introduced. It is required to work with [Rgnd], [Rpower] [Rac] and [Cac]. It is optional when used with [Gnd_clamp] and [Power_ clamp] keywords, since these keywords also are supported by the other available Model_type selections. This allows clamping structures to be included with "Discrete" devices, and also that shottkey diode terminator packs can be designated as "Discrete" for the purposes of termination operation rather than "Input" operation. For many terminators, the POWER and GND pin attachments are left to the user. For example, a resistor array could be used for pullup attachments with an Open_drain [Model] or as a terminator to ground. So the user is expected to provide most of the [Model]s based on the connection configuration. Bob Ross, Interconnectix, Inc. ***************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 9.2 ISSUE TITLE: Terminator Specification REQUESTOR: Bob Ross, Interconnectix, Inc. DATE SUBMITTED: 2 February 1994 DATE REVISED: 21 February 1994, 22 April 1994 DATE ACCEPTED BY IBIS OPEN FORUM: {will be filled in when accepted} ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Terminators are used in design and can exist as packaged parts. Therefore they are candidates for IBIS modeling. **************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The additional keywords, [Rpower] and [Rgnd], are proposed to represent resistors connected to power (VCC) and ground (GND) or to the voltages based on the voltage reference rules in BIRD3 as they apply to [POWER_clamp] and [GND_clamp]. An AC terminator requiring both [Rac] and [Cac] to GND is proposed. For new keyword usage, a new Model_type parameter within [Model] called "Discrete" is proposed. |============================================================================== | Keywords: [Rgnd], [Rpower], [Rac], [Cac] | Required: Yes, if they exist in the device | Description: The data for these keywords define the resistance values of | Rgnd and Rpower connected to GND and the POWER pins, | respectively. | Usage Rules: For each of these sections the three columns hold the | typical, minimum, and maximum resistance values. The three | entries for R(typ), R(min), and R(max) or C(typ), C(min), | and C(max) must be placed on a single line and must be | separated by at least one white space or tab character. | All three columns are required under these keywords, however | data is only required in the typical column. If minimum | and/or maximum values are not available, the reserved word | "NA" must be used indicating the R(typ) or C(typ) value by | default. | Other Notes: It should be noted that [Rpower] is connected to 'Vcc' and | [Rgnd] is connected to 'GND'. However, [GND_clamp reference] | voltages, if defined, apply to [Rgnd]. [POWER_clamp reference] | voltages, if defined, apply to [Rpower]. | Either or both [Rgnd] and [Rpower] may be defined and may | co-exist with [GND_clamp] and [POWER_clamp] structures. | If an AC terminator is specified, then both [Rac] and [Cac] | are required. | When [Rgnd], [Rpower], or [Rac] and [Cac] are specified, the | Model_type must be Discrete. |------------------------------------------------------------------------------ | variable R(typ) R(min) R(max) | [Rgnd] 330Ohm 300Ohm 360Ohm | Parallel Terminator [Rpower] 220Ohm 200Ohm NA | | [Rac] 30Ohm NA NA | | | | variable C(typ) C(min) C(max) | AC terminator | | [Cac] 50pF NA NA | |============================================================================== The [Model] keyword text has "Discrete" added to the list of Model_types. A modification to the Other Notes section refers to the the new keywords. |==============================================================================| | Keyword: [Model] | | Required: Yes | | Description: Used to define a model, and its attributes. | | Sub-Params: Model_type, Polarity, Enable, Vinl, Vinh, C_comp | |* |* BIRD7.2 and 9.2 modifications |* Usage Rules: Each Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, |* Open_sink, I/O_open_sink, Open_source, I/O_open_source, |* Input_ECL, Output_ECL, I/O_ECL and Discrete model must |* | begin with the keyword [Model]. The model_name must match | | the one that is listed under the [Pin] keyword and must not | | contain more than 20 characters. An .ibs file must contain | | enough [Model] keywords to cover all of the model_names | | specified under the [Pin] keyword, except for those | | model_names which use reserved words (POWER, GND and NC). | | Model_names with reserved words are an exception and | | they do not have to have a corresponding [Model] keyword. | | C_comp is allowed to use "NA" for the min and max values only. | |* |* BIRD9.2 change |* Other Notes: A complete [Model] description normally contains the following |* keywords: [Voltage range], [Pullup], [Pulldown], [GND_clamp], |* [POWER_clamp], [Rgnd], [Rpower], [Rac], [Cac], |* and [Ramp]. However, some models may have only |* a subset these keywords. For example, an input structure |* normally only needs the [Voltage range], [GND_clamp], and |* possibly the [POWER_clamp] keywords. If one or more of |* [Rgnd], [Rpower], [Rac] and [Cac] keywords are used, then |* the Model_type must be Discrete. |* |* BIRD7.2 addition |* Model_types with "open_sink" specify that the output has |* an OPEN side (the [Pullup] keyword is not used or I = 0mA |* for all voltages specified) AND the output SINKS current. |* Model_types with "open_drain" have the identical meaning and |* are retained for backward compatibility. Model_types with |* "open_source" specify that the output has an OPEN side (the |* [Pulldown keyword is not used or I = 0mA for all voltages |* specified) AND the output SOURCES current. Model_types with |* "_ECL" specify that the model represents and ECL type logic |* which follows different conventions for the [Pulldown] keyword. |* | Note that C_comp defines the silicon die capacitance. This | | value should not include the capacitance of the package. | | | |------------------------------------------------------------------------------| [Model] model_name |* |* BIRD7.2 and BIRD9.2 modification Model_type Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, Open_sink, I/O_open_sink, Open_source, I/O_open_source, Input_ECL, Output_ECL, I/O_ECL, Discrete | List one only |* Polarity Non-Inverting, Inverting | List one only, if any Enable Active-High, Active-Low | List one only, if any | Signals RAS, CAS, A(0-64), D(0-128),... | Local list, if desired Vinl = 0.8V | input logic "low" DC voltage, if any Vinh = 2.0V | input logic "high" DC voltage, if any | variable typ min max C_comp 12.0pF 10.0pF 15.0pF |==============================================================================| ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: A set of terminator components is useful to be formatted using IBIS because they are found as packaged components. All of the options can support (typ), (min) and (max) specifications. (1) Parallel Resistor Termination: The additonal elements [Rpower] and [Rgnd] provide terminations to Vcc, Gnd or both. Devices such as the Motorola MCC142233 to MCC142236 Switchable SCSI Passive Bus Terminator series would be modeled with these elements. At least two other techniques could be used in IBIS Version 1.1. The [POWER_clamp] or [GND_clamp] tables could be used (with as few as two data points each) to represent resistors. Another method could be to use R_pkg (or R_pin) with [POWER_clamp] or [GND_clamp] structures configured as a very low impedance. Processing tabular data for these purposes would be less efficient and less obvious than working with resistive elements directly. (2) RC (or AC) Termination: R_pkg (or R_pin) and C_comp can provide RC terminations. This proposal specifies [Rac] connected to [Cac] elements. This will allow packaged RC terminations which include built in clamping diodes to be modeled directly. Diode terminators already can be modeled using IBIS Version 1.1: (3) Diode Termination: Devices such as the TI SN74S1050 thru SN74S1056 Schottky Barrier Diode Bus-Termination Arrays can be modeled using existing [POWER_clamp] and [GND_clamp] structures. The total context model is attached showing the proposed additions. |<-------------DISCRETE Model------------------->| VOLTAGE RANGE or POWER_CLAMP REF o | POWER_ |---o---| CLAMP | | |--o--| \ | | / | VI | \ RPOWER PACKAGE Keyword | | / Parameters |--o--| | |<----------------->| | | | | PIN o-----o-------o-----o-----/\/\/\--UUUUUU---o--o | |GND_ | | R_PKG L_PKG | | |CLAMP | | | | |--o--| | | | | | | \ | | | | VI | /RGND | | | | | \ \ | | |--o--| / / RAC | | | | \ | | |---o---| / | | | | | C_COMP --- o --- CAC C_PKG --- --- GND or --- --- | GND_CLAMP REF | | | | | |-------------------o----------------------| | o GND |<-------->| Proposed Discrete Keywords ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: This BIRD partially addresses the issue related to BIRD2 regarding Termination Resistor Packs and Termination Diode Packs. It does not address Discrete two-port devices. The adoption of this BIRD would require some text changes in BIRD3 to reference the new keywords. ****************************************************************************** From speters@ichips.intel.com Mon Apr 25 09:24:46 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04839; Mon, 25 Apr 94 09:24:46 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Mon, 25 Apr 94 09:22:24 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Mon, 25 Apr 94 09:21:53 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Mon, 25 Apr 94 09:22:07 PDT Message-Id: <9404251622.AA18356@xtg801.intel.com> To: ibis@vhdl.org Subject: BIRD 12, non-linear ramps Date: Mon, 25 Apr 1994 09:22:06 -0700 From: Stephen Peters Hello Fellow IBISans Another egg has hatched........ Regards, Stephen Peters Intel Corp. --------------------------- cut here ----------------------------- Buffer Issue Resolution Document (BIRD) BIRD ID#: 0012 ISSUE TITLE: Non-Linear Driver Waveforms REQUESTER: Stephen Peters, Intel Corp. DATE SUBMITTED: April 25, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: The IBIS specification does not contain enough information to adequately describe the characteristics of a device whose output switching waveform is significantly non-linear. This BIRD proposes a method to describe these non-linear ramp waveforms. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: Two new keywords are added to the specification, [Rising waveform] and [Falling waveform]. These keywords introduce a table of time vs. voltage points that describe the shape of a waveform. | | Keywords: [Rising waveform], [Falling waveform] | Required: No | Description: Used to describe the shape of the rising and falling edge | waveforms of a driver. | Sub-params: R_load, V_load, C_load, L_load | Usage Rules: Each [Rising_waveform] and [Falling-waveform] keyword | introduces a table of time vs. voltage points that | describe the shape of an output waveform. These | time/voltage point are taken under the conditions | specified in the R_load, V_load, C_load and L_load | sub-parameters. The table itself consists of | one column of time points, then three columns of | voltage points in the standard typ, min and max format. | The four entries must be placed on a single line and | must be separated by at least one white space or tab | character. All four columns are required, however, data | is only required in the typical column. If minimum | or maximum data is not available the reserved word "NA" | is used. The first value in the time column does not | have to be '0'. Time values must increase as | one parses down the table. | | A waveform table must include the entire waveform; | i.e., the first entry (or entries) in a voltage column | must be the DC voltage of the output before switching | and the last entry (or entries) of the column must be | the final DC value of the output after switching. | | A [Model] specification can contain more | than one rising edge or falling edge waveform table; | however, each new table must begin with the appropriate | keyword and sub-parameter list as shown below. The | waveform table may contain as many points as needed | to accurately describe the wave. Note that for backwards | compatibility the existing [Ramp] keyword is still | required and the [Ramp] values should be derived as | described in Version 1.1 of the IBIS specification. | | The R_load and V_load sub-parameters are required while | the C_load and L_load sub-parameters are optional. R_load | and V_load are the thevenin equivalent resistance and | voltage the driver is switching into. C_load and | L_load are analogous to the the package parameters C_pkg | and L_pkg and are used if the waveform includes the | effects of pin inductance/capacitance. If they are not | specified they default to zero. The sub-parameters | must appear in the text after the keyword and before | the first row of the waveform table. | [Rising waveform] R_load 50 V_load 1.5 C_load 10p L_load 2n |Time V(typ) V(min) V(max) 0.0ns 0.3 0.5 NA 0.5ns 0.3 0.5 NA 1.0ns 0.6 0.7 NA 1.5ns 0.9 0.9 NA 2.0ns 1.5 1.3 NA 2.5ns 2.1 1.7 NA 3.0ns 3.0 2.7 NA 3.5ns 3.2 3.0 NA | [Falling waveform] R_load 50 V_load 0 |Time V(typ) V(min) V(max) 10.0ns 3.2 3.0 NA 10.5ns 3.0 2.7 NA 11.0ns 2.1 1.7 NA 11.5ns 1.5 1.3 NA 12.0ns 0.9 0.9 NA 12.5ns 0.6 0.7 NA 13.0ns 0.3 0.5 NA 13.5ns 0.0 0.0 NA ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Currently, the IBIS specification assumes that all devices can be described accurately using a single risetime and falltime parameter. In other words, the switching waveform of the device is a relatively linear ramp. However, devices that shape the output waveform (risetime controlled devices) do not have a linear switching ramp. Trying to model devices of this type using a linear ramp model results in mis-predicting both the time to logic threshold and maximum edge rate. As IBIS is a specification that focuses on the behavior of a device rather than it structure or implementation, it would be ideal if there were a simple set of measurements one could take in order to describe the non-linearity. Obviously, the waveform shape itself is a good place to start. The fundamental assumption here is that the shape of the waveform, combined with the loading conditions, give simulator vendors enough additional information to construct accurate models of non-linear waveform drivers. Ideally, an IBIS model will include waveforms taken under several different loading conditions (R_load and V_load). By choosing the appropriate loading conditions a modeler can give the simulator vendors enough information to accurately simulate a device. The most straight forward way to describe a waveform shape is with a table of time vs. voltage points. (Note that one could take this table and enter it into a spreadsheet or graphing program and produce a picture of the waveform -- and that is one of the intents of the format.) One remaining issue is the ability to align the starting points of waveforms taken under different loading conditions (i.e. waveforms in two different tables). Jon Powell (Quad Design) has an action item to produce various waveforms and show this is possible. In addition to providing more complete information to simulator vendors, explicitly describing the waveform allows one to validate a particular simulator's results. By performing a simulation into the specified load(s) and then comparing the results with the waveform(s) as listed in the IBIS file, one can perform anything from a quick sanity check of the data to a detailed analysis between simulators. A 'self-validating' model is a very powerful tool for checking and maintaining model quality. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: ******************************************************************************* From bob@icx.com Mon Apr 25 12:30:49 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06605; Mon, 25 Apr 94 12:30:49 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA13288 for ; Mon, 25 Apr 94 14:55:10 -0400 Date: Mon, 25 Apr 94 11:14:03 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA10795; Mon, 25 Apr 94 11:14:03 PDT Message-Id: <9404251814.AA10795@icx.com> To: ibis@vhdl.org Subject: BIRD12 COMMENTS To Stephen Peters and IBIS Committee Great job, Stephen! Here are some minor comments on format: (1) Typo - The 13.5ns line in the example should be 13.5ns 0.3 0.5 NA (2) Under the keyword [Model] the Vinh and Vinl numerical subparameters are specified as: Vinh = 2.0 Vinl = 0.8 So, for consistency should the _load subparameters be formatted with "=" as: R_load = 50n V_load = 1.5 C_load = 10p L_load = 2n (3) I like the note requiring that the subparameters immediately follow the keywords [Rising waveform] or [Falling waveform] and are before the table. A similar requirement for the [Model] subparameters exists based on IBIS_CHK where the subparameters must appear prior to any keyword associated with [Model]. This does not appear to be documented in IBIS Version 1.1, so I would suggest that the Editing committee add a similar restriction for Version 2.0. Bob Ross, Interconnectix, Inc. From Derrick_Duehren@ccm2.jf.intel.com Tue Apr 26 05:23:36 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15392; Tue, 26 Apr 94 05:23:36 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pvm7h-000MNQC; Tue, 26 Apr 94 05:20 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Tue, 26 Apr 94 05:20:21 PST Date: Tue, 26 Apr 94 05:20:21 PST From: Derrick Duehren Message-Id: <940426052021_1@ccm.hf.intel.com> To: IBIS@vhdl.org Subject: IBIS 4/29 Meeting Agenda Text item: Text_1 IBIS Open Forum Meeting Agenda for 4/29/94 Bridge: Res: (415) 904-8944 721618 ************************************************************************ ****** We will attempt to come to closure on all BIRDs ******* ****** through BIRD 11 at this meeting. PLEASE ATTEND! ******* ************************************************************************ All meetings are 8:00 AM to 10:00 AM PST (15:00 to 17:00 UTC). When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. 8:00 Check-in Intros of new IBIS participants Hobbs Review of previous meeting's minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All New models available All IBIS 2.0 Ratification/DAC/Other 2.0 Issues Hobbs - Birds of a Feather session (6/8) - Rev 2.0 Ratification Summit (6/9) - Levels of support (see 12/3/93 discussion below) IBIS Cookbook Hobbs, Rosenbaum 8:30 BIRD 8, Spec. of V/I data monotonicity Crisafulli CLOSURE EXPECTED BIRD 9.2, Terminator Specification Ross CLOSURE EXPECTED BIRD 10, Coupling effects in package models Bracken CLOSURE EXPECTED 9:00 BIRD 11, Sign of current checking Hobbs, All CLOSURE EXPECTED BIRD 12, Non-Linear Driver Waveforms Peters BIRD 2, VIH, VIL Thresholds for Inputs Powell Egg 3, Simulation temperatures Ward The rest of the nest (Eggs 4, 5...) All 9:55 Wrap-up, Next Meeting Plans Hobbs Levels of Support. From the 12/3/93 IBIS Open Forum Minutes: We discussed how to handle allowing both very complex models and simple models, and that perhaps we should define IBIS model levels; The simplest acceptable IBIS model would be a level 1 model, ones that added some advanced IBIS features such as power and ground structure, would be higher level models, level 2, 3, .... Perhaps we should identify each parameter as participating in a particular level. We agreed to address these levels as we put together IBIS Version 2.0. From bward@dadhb1.ti.com Tue Apr 26 05:46:55 1994 Return-Path: Received: from lobby2b.ti.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15551; Tue, 26 Apr 94 05:46:55 PDT Received: from tilde.csc.ti.com by lobby2b.ti.com with SMTP (8.6.8.1/LAI-3.2) id HAA14239; Tue, 26 Apr 1994 07:42:22 -0500 Received: from isis.dadhb1.ti.com (dadhb1_0.sc.ti.com) by tilde.csc.ti.com id AA17513; Tue, 26 Apr 1994 07:44:11 -0500 Received: from emu.dadhb1.ti.com by isis.dadhb1.ti.com with SMTP (1.37.109.4/IDA1.4.4.1-Domain/OS) id AA15486; Tue, 26 Apr 94 07:43:58 -0500 From: Bob Ward Received: by emu.dadhb1.ti.com id ; Tue, 26 Apr 94 07:44:30 -0500 Date: Tue, 26 Apr 94 07:44:30 -0500 Message-Id: <9404261244.AA03662@emu.dadhb1.ti.com> To: ibis@vhdl.org Subject: Measurement conditions BIRD All - This is a first try at the EGG/BIRD I volunteered for at the last forum meeting. I hope to get this out in time to still discuss it at the next meeting. ++++++++++++++++++++++++++++++++++++ SNIP ++++++++++++++++++++++++++++++++++++++ Buffer Issue Resolution Document (BIRD) BIRD ID#: ISSUE TITLE: Clarify Some Conditions of Measurements REQUESTOR: Bob Ward Texas Instruments DATE SUBMITTED: 22 APR 94 DATE ACCEPTED BY IBIS OPEN FORUM: ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: Certain statements are made in the Version 1.1 standard that need calrification for the sake of newcomers to the Ibis community regarding the conditions under measured data is taken. These changes bring the standard more into line with the discussions on the forum and the cookbook, which is taken to reflect the intention and not just the letter of the specification. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: The majority of the change is to the NOTES TO DATA DERIVATION METHOD section of th spec. In paragraph numbered 1) Old text is: | V/I Curves for CMOS devices: | typ = nominal voltage, 50 degrees C, typical process | min = low voltage tol, 100 degrees C, typical process, minus "X%" | max = hi voltage tol, 0 degrees C, typical process, plus "X%" | | V/I curves for bipolar devices: | typ = nominal voltage, 50 degrees C, typical process | min = low voltage tol, 0 degrees C, typical process, minus "X%" | max = hi voltage tol, 100 degrees C, typical process, plus "X%" Proposed text is: | V/I Curves for CMOS devices: | typ = nominal voltage, nominal temperature deg C, typical process | min = low voltage tol, max temperature deg C, typical process, minus"X%" | max = hi voltage tol, min teperature deg C, typical process, plus "X%" | | V/I curves for bipolar devices: | typ = nominal voltage, nominal temperature deg C, typical process | min = low voltage tol, max temperature deg C, typical process, minus "X%" | max = hi voltage tol, min teperature deg C, typical process, plus "X%" | | where nominal, min, and max temperature are specified by the manufacturer of | the part. The preferred range is 50C nom, 0C min and 100C max temperatures. Add after the end of paragraph numbered 2) and before 3): These voltage ranges apply to simulation derived data. Data derived from lab measurements should be taken as near to this range as equipment will allow ( eg. a curve tracer may limit current to non-destructive values even at these voltage extremes ) or as limited by manufactirer specified absolute maximum voltages. Add in paragraph numbered 3) after step 3 and before step 4 the following note: There may be devices which will not drive a load of only 50 ohms into any useful level of dynamics. In these cases use the manufacturers suggested ( non-reactive ) load and add the load sub parameter to the [Ramp] specification. Under the heading Ramp times fopr CMOS devices, make the same temerature specifications as above. Add a note after step 7. in the same section that during the ramp measurements the driving waveform should be of a rise/fall time typical of the actual circuit in operation. Also the driving waveform should not have sharp breakpoints at the top and bottom of the edges, but should be slightly rounded to avoid artifical high frequency effects. Add specification of the sub parameter 'load' to the [Ramp] keyword. Under Keyword: [Ramp] change Sub-Params: dV/dt_r, dV/dt_f, load Add text to the Usage Rules: The load sub-parameter is optional if the preferred 50 ohm load is used. It is required if a non-standard load is used. Add to the example as follows: [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n load 300ohms Add after the [Volatge range] keyword discussion: |==============================================================================| | Keyword: [Temperature range] | | Required: Yes, if other than the preferred 0, 50, 100 degree C range | | Description: Used to define the temperature range over which the model is | | to operate. | | Usage Rules: Actual temperatures (not percentages) are to be presented in | | the usual typ, min, max format. "NA" is not allowed. | | Other Notes: [Temperature range] also describes the temperature range over | | which the various V/I curves and ramp rates were derived. | |------------------------------------------------------------------------------| | variable typ min max [Temperature range] 27.0C -50C 130.0C ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: {There are many "experts" reviewing this document. Your reasons, analysis, and justifications must be precise and well documented, or your BIRD will be sent back to you. Use this section to show that you've done your homework, and answer all questions that will undoubtedly be asked. If your issue is a change instead of an enhancement, document how backward compatibility is to be addressed.} The spec should have flexibility enough to handle models of parts manufactured to MIL spec and automotive spec as well as parts for special purposes which are perhaps more sensitive than even consumer or commercial spec allows. Thus the relaxation , or tightening as the case may be, of the temperature and voltage range mandates. The added keyword and sub-parameter are to allow the simulator useable specification of the relaxed or tightened ranges for the relevant measurements. The ramp rate is still mandated to be determined between 20 and 80 % of actual swing to promote the linearity of the measured portion of the edge. The load is mandated to be non-reactive so as to preserve the inherent dynamics of the driver, and not introduce false dynamics due to the load. Backward compatibility is addressed by making the new specifications optional if the preferred votage and temperature ranges and load resistance are used. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: N/A ******************************************************************************* ++++++++++++++++++++++++++++++++++++ SNIP ++++++++++++++++++++++++++++++++++++++ ============================================================================= __ / / \ / / Bob Ward /__ / / / / / / / \ _ /_ / / / _ __ _ / INET: bward@dadhb1.ti.com -or- (____ / (_)_ /__) (__(__/ (_(_/ (_(_/ bward@neosoft.com 713+274-4146 Voice 713+274-3911 Fax ============================================================================= ___ (o o) -------------------------------ooO-(_)-Ooo----------------------------------- Here I sit in endless joy, 'cause I was here before Kilroy!!! From bward@dadhb1.ti.com Tue Apr 26 06:31:34 1994 Return-Path: Received: from lobby2b.ti.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15815; Tue, 26 Apr 94 06:31:34 PDT Received: from tilde.csc.ti.com by lobby2b.ti.com with SMTP (8.6.8.1/LAI-3.2) id IAA16152; Tue, 26 Apr 1994 08:27:01 -0500 Received: from isis.dadhb1.ti.com (dadhb1_0.sc.ti.com) by tilde.csc.ti.com id AA19848; Tue, 26 Apr 1994 08:28:51 -0500 Received: from emu.dadhb1.ti.com by isis.dadhb1.ti.com with SMTP (1.37.109.4/IDA1.4.4.1-Domain/OS) id AA15556; Tue, 26 Apr 94 08:28:39 -0500 From: Bob Ward Received: by emu.dadhb1.ti.com id ; Tue, 26 Apr 94 08:29:11 -0500 Date: Tue, 26 Apr 94 08:29:11 -0500 Message-Id: <9404261329.AA03720@emu.dadhb1.ti.com> To: ibis@vhdl.org Subject: Clarification, please, on monotonicity All - We have had several discussions of monotonic and non-monotonic behaviour of drivers, but there is a point which remains ambiguous in my mind. When we speak of monotonicity, do we mean strictly rising ( or falling ) waveforms, or do we accept non-decreasing ( non-increasing ) waveforms as monotonic? That is would a waveform be considered monotonic if it rose for a while, flattened out to a number of equal values and then rose again? The question really is does the derivative have to be always of the same sign, or is a derivative that has a zero region acceptable as a definition of monotonic? According to the strict mathematical definition, the derivative must be of the same sign and non- zero over the interval of interest. But it seems to me that we are more interested here in allowing the zero region of the derivative and so talking about non_decreassing ( or non-increasing ). Either can make a valid working definition, but it makes a difference as I code a test for the condition as to which we mean. Clarification? Comments? Thanks, Bob bward@dadhb1.ti.com or bward@neosoft.com From jonp@qdt.com Tue Apr 26 08:46:14 1994 Return-Path: Received: from relay1.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16628; Tue, 26 Apr 94 08:46:14 PDT Received: from uucp1.uu.net by relay1.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwnhu03528; Tue, 26 Apr 94 11:43:51 -0400 Received: from qdt.UUCP by uucp1.uu.net with UUCP/RMAIL ; Tue, 26 Apr 1994 11:43:51 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00589; Tue, 26 Apr 94 08:32:39 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA06092; Tue, 26 Apr 94 08:32:39 PDT Date: Tue, 26 Apr 94 08:32:39 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404261532.AA06092@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA01455; Tue, 26 Apr 94 08:32:47 PDT To: uunet!dadhb1.ti.com!bward@uunet.UU.NET Cc: ibis@vhdl.org In-Reply-To: Bob Ward's message of Tue, 26 Apr 94 08:29:11 -0500 <9404261329.AA03720@emu.dadhb1.ti.com> Subject: Clarification, please, on monotonicity Non-monotonic I always intened monotonic to mean no sign change or no value change. What I am trying to avoid is un-stable configurations caused by load lines that can intersect an IV curve at more than one stable point. I think this can only happen with a complete sign change. (Now I have to go get some graph paper.) jonp From Arpad_Muranyi@ccm.fm.intel.com Tue Apr 26 09:32:30 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16900; Tue, 26 Apr 94 09:32:30 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pvq0Z-000MNYC; Tue, 26 Apr 94 09:29 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Tue, 26 Apr 94 09:29:15 PST Date: Tue, 26 Apr 94 09:29:15 PST From: Arpad Muranyi Message-Id: <940426092915_4@ccm.hf.intel.com> To: ibis@vhdl.org Subject: Response to the Quad article from Arpad Text item: Text_1 Hi IBIS folk, This is my response to the article "Measuring Pull-down Currents in CMOS devices" by Jon Powell and Chris Myles (JP&CM) at Quad Design. 1) Generally speaking, I must say that I couldn't agree more with the theory presented in the article. I am fully aware of the fact that the bulk currents are different in an ON and an OFF transistor, as shown in Figures 2 and 3. I also agree with the equations on page 2 which state that the difference between the ON and OFF transistor's drain current is equal to the ON transistor's source current if and only if the bulk currents are equal and the OFF transistor's source current is assumed to be zero. Id1-Id2 = -Is1, iff Ib1 = Ib2 and Is2 = 0 2) I also agree that the difference between the ON and OFF transistor's bulk current can be plotted as shown in Figure 5 and if combined with the curve shown in Figure 4, we arrive to the curve shown in Figure 6. 3) The difference in our opinion came from the interpretation of the IBIS specifications. I must admit that the specifications do not clearly spell out how to deal with this issue. We must address this problem so that the rev2 specification would be clear and unambiguous. Here is how I approached the problem: It was not my goal to provide transistor-theory correct Is curves in the pulldown and pullup tables. I assumed that a simulator tool would use the clamping curves as constantly present I-V curves, and it would add the appropriate pullup or pulldown curve to it when the buffer was turned on. This is the key assumption, which I believe nearly all of us have made, that should be clearly documented in the IBIS specifications. With lab measurements we can only obtain I-V curves for 3-stated or enabled buffers. A 3-stated buffer can be used to obtain the I-V curves needed for the clamping tables, but an enabled buffer gives the sum of the clamp and the transistor. This sum curve cannot be added to the clamp, as stated above, because it already includes the clamp currents. This is how I arrived at the "subtract method". In order to be able to add the I-V curves in the clamp sections to the I-V curves in the pullup and pulldown sections for an enabled buffer, I had to provide the difference of the two for those tables. This is what the JP&CM article calls Id1-Id2. I did not have an easy way to subtract these curves from each other in the early days. Knowing from theory that the source current of a MOSFET transistor is fairly symmetric around the origin (just like figure 6 shows it in the JP&CM article), first I generated models based on the approximation that the difference of the two is the positive part of the I-V curve flipped over. Therefore, in the early models, I generated symmetric curves for the pulldown and pullup tables, and used the 3-stated I-V curves as measured for the clamp tables. I used this method until I made myself a tool with which I could subtract the 3-stated buffer's curve from the enabled buffer's curve. I was very surprised by the non-monotonic curve I saw. First I thought I had a bad silicon model; however, after investigating the issue further, I came to the conclusion that the curves were correct the way they looked. In the spirit of continuous improvements, I started to make models with the "subtract method", which were non-monotonic but were more accurate (assuming the curves are later summed) than the previously described models generated with the "symmetry method". In the case of the non 3-statable buffers there is no way to measure the clamping curves alone. Since a buffer always appears as the sum of the transistor and the clamp, I decided to put all zeroes in the clamp sections (i.e. omitted the clamp keywords) and lumped everything into the pulldown and pullup I-V tables. Based on the summing assumption (that must be documented) for the simulation tools, I did not see anything wrong with this method. You might wonder why it is necessary to subtract, when the tool adds the curves up again. I could have provided the measured curves just as they are. For one thing, I wanted to avoid the "double counting" of the clamp curves. Another important reason was the Vcc relativness of the pullups and the power clamps. However, it is beyond the purpose of this writing to explain these issues in detail. I believe that the method described above presented correct models and I do not see any mathematical errors in the process. I was simply using the available keywords to allow the most accurate simulations possible. 4) For the sake of completeness, I need to point out that something must be wrong (perhaps due to an typing error) with the equations on page 3 of the JP&CM article, since the left hand side is equal to 0 as shown. Also, on page 5, it is stated that SPICE models assume a zero bulk resistance and it would be more realistic to use bulk resistances in the range of 100 Ohms. First of all, the two SPICE flavors I have used so far do NOT assume that. There are three parameters which can be used in the .MODEL section: Rd for drain, Rs for source, and Rb for bulk resistances. (It is another story that sometimes these are not defined in a model, in which case they default to zero). Second, 100 Ohms seems to be quite large, however if expressed in terms of sheet resistance, 100 Ohms/square is certainly possible. Consider a 100 Ohm series (bulk) resistance with a clamping diode: at -5 V it would allow about 50 mA only. Most devices draw a lot more than that (if they survive the -5 V or their curve is extrapolated to -5 V). Still referring to page 5, in my experience, we are not trying to detect a 5 mA difference between two 1.0E+20 mA (1.0E+17 Amp) numbers. Such currents occur usually when the drain, source and bulk resistances are not defined in a transistor level SPICE model. If a buffer is modeled correctly in SPICE (or if lab measurements are used), these large currents are in the range of 5 to 15 Amps at -5 volts, but they can be as low as 7 mA at -3.5 Volts (in the case of some DRAM modules I tested). A 30 to 40 mA difference WILL NOT cause mathematical floating point errors between two 15 Amp numbers. Also, we might neglect a 30 to 40 mA difference in the case of two 15 Amp clamping currents, but we certainly cannot do that if the clamps are weak, as in the case of DRAMs. 5) Regarding the suggestion that using realistic bulk currents will result in monotonic curves, I found the followings from simulations: The shape of the curve depends on the proportions between the drain/source/channel resistance and the bulk resistance (and possibly the channel resistance as well). When the bulk resistance is small, most of the current goes through the bulk, resulting in a non-monotonic curve for Id1 - Id2. When the bulk resistance is relatively large, most of the current goes through the channel, and the Id1 - Id2 curve becomes monotonic in shape. However, a lab measurement on a 74HCT245 buffer showed that the difference between a 3-stated buffer curve and an enabled buffer curve (Id1 - Id2) was indeed non-monotonic. This indicated to me that the bulk resistance must have been relatively small with respect to the drain and source resistances. I hope this has provided some good background information. I will be working in the future to enusre that the proper set of assumptions are documented in the IBIS specifications. (Watch for a bird fly by). I welcome your comments as we all labor together to make IBIS as clear as possible. Sincerely Arpad Muranyi Intel Corporation, Folsom, CA (916) 356-2558 From Arpad_Muranyi@ccm.fm.intel.com Tue Apr 26 09:56:55 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17034; Tue, 26 Apr 94 09:56:55 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pvqOA-000MNUC; Tue, 26 Apr 94 09:53 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Tue, 26 Apr 94 09:53:38 PST Date: Tue, 26 Apr 94 09:53:38 PST From: Arpad Muranyi Message-Id: <940426095338_3@ccm.hf.intel.com> To: ibis@vhdl.org Subject: Re: BIRD 12, non-linear ramps Steven, Great job. However, I am still missing the capability of defining separate turn-on and turn-off waveforms (for both rising and falling). We migh want to define a sub-paramteter, or sub-keyword to allow for that. Arpad Hello Fellow IBISans Another egg has hatched........ Regards, Stephen Peters Intel Corp. --------------------------- cut here ----------------------------- Buffer Issue Resolution Document (BIRD) BIRD ID#: 0012 ISSUE TITLE: Non-Linear Driver Waveforms REQUESTER: Stephen Peters, Intel Corp. DATE SUBMITTED: April 25, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** * ****************************************************************************** * STATEMENT OF THE ISSUE: The IBIS specification does not contain enough information to adequately describe the characteristics of a device whose output switching waveform is significantly non-linear. This BIRD proposes a method to describe these non-linear ramp waveforms. ****************************************************************************** * STATEMENT OF THE RESOLVED SPECIFICATIONS: Two new keywords are added to the specification, [Rising waveform] and [Falling waveform]. These keywords introduce a table of time vs. voltage points that describe the shape of a waveform. | | Keywords: [Rising waveform], [Falling waveform] | Required: No | Description: Used to describe the shape of the rising and falling edge | waveforms of a driver. | Sub-params: R_load, V_load, C_load, L_load | Usage Rules: Each [Rising_waveform] and [Falling-waveform] keyword | introduces a table of time vs. voltage points that | describe the shape of an output waveform. These | time/voltage point are taken under the conditions | specified in the R_load, V_load, C_load and L_load | sub-parameters. The table itself consists of | one column of time points, then three columns of | voltage points in the standard typ, min and max format. | The four entries must be placed on a single line and | must be separated by at least one white space or tab | character. All four columns are required, however, data | is only required in the typical column. If minimum | or maximum data is not available the reserved word "NA" | is used. The first value in the time column does not | have to be '0'. Time values must increase as | one parses down the table. | | A waveform table must include the entire waveform; | i.e., the first entry (or entries) in a voltage column | must be the DC voltage of the output before switching | and the last entry (or entries) of the column must be | the final DC value of the output after switching. | | A [Model] specification can contain more | than one rising edge or falling edge waveform table; | however, each new table must begin with the appropriate | keyword and sub-parameter list as shown below. The | waveform table may contain as many points as needed | to accurately describe the wave. Note that for backwards | compatibility the existing [Ramp] keyword is still | required and the [Ramp] values should be derived as | described in Version 1.1 of the IBIS specification. | | The R_load and V_load sub-parameters are required while | the C_load and L_load sub-parameters are optional. R_load | and V_load are the thevenin equivalent resistance and | voltage the driver is switching into. C_load and | L_load are analogous to the the package parameters C_pkg | and L_pkg and are used if the waveform includes the | effects of pin inductance/capacitance. If they are not | specified they default to zero. The sub-parameters | must appear in the text after the keyword and before | the first row of the waveform table. | [Rising waveform] R_load 50 V_load 1.5 C_load 10p L_load 2n |Time V(typ) V(min) V(max) 0.0ns 0.3 0.5 NA 0.5ns 0.3 0.5 NA 1.0ns 0.6 0.7 NA 1.5ns 0.9 0.9 NA 2.0ns 1.5 1.3 NA 2.5ns 2.1 1.7 NA 3.0ns 3.0 2.7 NA 3.5ns 3.2 3.0 NA | [Falling waveform] R_load 50 V_load 0 |Time V(typ) V(min) V(max) 10.0ns 3.2 3.0 NA 10.5ns 3.0 2.7 NA 11.0ns 2.1 1.7 NA 11.5ns 1.5 1.3 NA 12.0ns 0.9 0.9 NA 12.5ns 0.6 0.7 NA 13.0ns 0.3 0.5 NA 13.5ns 0.0 0.0 NA ****************************************************************************** * ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Currently, the IBIS specification assumes that all devices can be described accurately using a single risetime and falltime parameter. In other words, the switching waveform of the device is a relatively linear ramp. However, devices that shape the output waveform (risetime controlled devices) do not have a linear switching ramp. Trying to model devices of this type using a linear ramp model results in mis-predicting both the time to logic threshold and maximum edge rate. As IBIS is a specification that focuses on the behavior of a device rather than it structure or implementation, it would be ideal if there were a simple set of measurements one could take in order to describe the non-linearity. Obviously, the waveform shape itself is a good place to start. The fundamental assumption here is that the shape of the waveform, combined with the loading conditions, give simulator vendors enough additional information to construct accurate models of non-linear waveform drivers. Ideally, an IBIS model will include waveforms taken under several different loading conditions (R_load and V_load). By choosing the appropriate loading conditions a modeler can give the simulator vendors enough information to accurately simulate a device. The most straight forward way to describe a waveform shape is with a table of time vs. voltage points. (Note that one could take this table and enter it into a spreadsheet or graphing program and produce a picture of the waveform -- and that is one of the intents of the format.) One remaining issue is the ability to align the starting points of waveforms taken under different loading conditions (i.e. waveforms in two different tables). Jon Powell (Quad Design) has an action item to produce various waveforms and show this is possible. In addition to providing more complete information to simulator vendors, explicitly describing the waveform allows one to validate a particular simulator's results. By performing a simulation into the specified load(s) and then comparing the results with the waveform(s) as listed in the IBIS file, one can perform anything from a quick sanity check of the data to a detailed analysis between simulators. A 'self-validating' model is a very powerful tool for checking and maintaining model quality. ****************************************************************************** * ANY OTHER BACKGROUND INFORMATION: ****************************************************************************** * From bward@dadhb1.ti.com Tue Apr 26 12:00:08 1994 Return-Path: Received: from lobby2b.ti.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17859; Tue, 26 Apr 94 12:00:08 PDT Received: from tilde.csc.ti.com by lobby2b.ti.com with SMTP (8.6.8.1/LAI-3.2) id NAA14576; Tue, 26 Apr 1994 13:55:35 -0500 Received: from isis.dadhb1.ti.com (dadhb1_0.sc.ti.com) by tilde.csc.ti.com id AA07575; Tue, 26 Apr 1994 13:57:22 -0500 Received: from emu.dadhb1.ti.com by isis.dadhb1.ti.com with SMTP (1.37.109.4/IDA1.4.4.1-Domain/OS) id AA18637; Tue, 26 Apr 94 13:57:10 -0500 From: Bob Ward Received: by emu.dadhb1.ti.com id ; Tue, 26 Apr 94 13:57:41 -0500 Date: Tue, 26 Apr 94 13:57:41 -0500 Message-Id: <9404261857.AA04127@emu.dadhb1.ti.com> To: ibis@vhdl.org Subject: Re: Clarification on monotonicity Jon, and the rest of the ibis community - I can agree with the definition of monotonicity including the equal condition, but I am not sure it is a strong enough condition to absolutely gaurantee no multiple operating points. If R be the load resistance so that it represents the slope of a load line, and if it be large enough, but not too large, you can get something like : I * | .* | * | *. | * . | * . | * . | * .| * . * |. * | . *| . ---------------+---.--------------- V | * . | * . | *. | * | . | *. | * . | * . | * . | * . | * Which yields two possible operating points, or maybe up to 4 depending on just where the load line falls and the exact shape of the IV curve. And it seems that either the pull up or the pull down curve will have a shape somewhat like this. There may be other considerations that say that load lines in real life do not attain such slopes, and that may even be fair. The same example holds if the curve be rotated. Then the load line slope, thus load R need only be small enough to make the same example hold. Again, that might take an unrealistically small load resistance. But then again it might not, too. So I wonder if this is a strong enough condition. I fully agree it is necessary, but I am not sure it is sufficient. In fact, a truly non monotonic IV curve would almost guarantee multiple solution points for realistic load lines, I would guess. So I agree that the monotonicity check is good, but should we strengthen the condition we are testing for? I have not convinced myself either way yet. Less yet do I see just _how_ to strengthen the condition. Further comment invited! ============================================================================= __ / / \ / / Bob Ward /__ / / / / / / MSG: SQU / \ _ /_ / / / _ __ _ / INET: bward@dadhb1.ti.com (____ / (_)_ /__) (__(__/ (_(_/ (_(_/ 713+274-4146 Voice 713+274-3911 Fax ============================================================================= ,,, (o o) -------------------------------ooO-(_)-Ooo----------------------------------- Here I sit in endless joy, 'cause I was here before Kilroy!!! From bward@dadhb1.ti.com Tue Apr 26 13:47:49 1994 Return-Path: Received: from lobby2b.ti.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18661; Tue, 26 Apr 94 13:47:49 PDT Received: from tilde.csc.ti.com by lobby2b.ti.com with SMTP (8.6.8.1/LAI-3.2) id PAA23600; Tue, 26 Apr 1994 15:43:14 -0500 Received: from isis.dadhb1.ti.com (dadhb1_0.sc.ti.com) by tilde.csc.ti.com id AA12403; Tue, 26 Apr 1994 15:44:59 -0500 Received: from emu.dadhb1.ti.com by isis.dadhb1.ti.com with SMTP (1.37.109.4/IDA1.4.4.1-Domain/OS) id AA19817; Tue, 26 Apr 94 15:44:40 -0500 From: Bob Ward Received: by emu.dadhb1.ti.com id ; Tue, 26 Apr 94 15:45:12 -0500 Date: Tue, 26 Apr 94 15:45:12 -0500 Message-Id: <9404262045.AA04270@emu.dadhb1.ti.com> To: ibis@vhdl.org Subject: A little more to add to Arpad's response to Quad article. At this time I will comment only on the size of bulk resistances. Reading Arpad's response makes me want to go back and reread the article for the math's sake, but I have not done so yet. But, interestly enough, I have just gotten the result of some lab work to measure several bulk resistances for several transistors of several constructions. Realistic values ran in the range 4 ohms to 30 ohms depending on the nature of the well in which the transistor is formed and on whether it was from an epitaxial or non epitaxial process. It was surpringly constant WRT n-type p-type with the main variation being epi or non-epi. As a matter of fact two clusters were formed, one from about 4 to 8.5 ohms and one from about 19 to 30 ohms. ============================================================================= __ / / \ / / Bob Ward /__ / / / / / / MSG: SQU / \ _ /_ / / / _ __ _ / INET: bward@dadhb1.ti.com (____ / (_)_ /__) (__(__/ (_(_/ (_(_/ 713+274-4146 Voice 713+274-3911 Fax ============================================================================= ___ (o o) -------------------------------ooO-(_)-Ooo----------------------------------- Here I sit in endless joy, 'cause I was here before Kilroy!!! From jonp@qdt.com Tue Apr 26 14:18:44 1994 Return-Path: Received: from relay1.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA19023; Tue, 26 Apr 94 14:18:44 PDT Received: from uucp4.uu.net by relay1.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwnir01351; Tue, 26 Apr 94 17:16:20 -0400 Received: from qdt.UUCP by uucp4.uu.net with UUCP/RMAIL ; Tue, 26 Apr 1994 17:16:22 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00707; Tue, 26 Apr 94 10:06:38 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA06308; Tue, 26 Apr 94 10:06:36 PDT Date: Tue, 26 Apr 94 10:06:36 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404261706.AA06308@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA01465; Tue, 26 Apr 94 10:06:43 PDT To: ibis@vhdl.org Subject: bird 2.2 I read the 1.1x unofficial spec. I sure hope I pass. JNP Buffer Issue Resolution Document (BIRD) BIRD ID#: 2.2 ISSUE TITLE: Requiring VIH VIL thresholds for input devices REQUESTOR: Jon Powell, Quad Desgin DATE SUBMITTED: 4/26/94 DATE ACCEPTED BY IBIS OPEN FORUM: {will be filled in when accepted} ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: The V1.1 IBIS specification does not require the presence of input thresholds on input devices. This allows data-generators to omit thresholds and still create "IBIS LEGAL" models. Input devices with no stated digital logic input thresholds do not allow for the calculation of digital pin-to-pin delays which is a very important quantity to many potential IBIS customers. Requiring a low and high threshold for all digital input devices is therefor a reasonable requirement that adds information without creating undo restrictions. A secondary issue in Differential Input Thresholds is also addressed. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: intent: modify the definition of Vinl and Vinh to require threshold definition for certain [Model] types. method: 1) Add the following model type: Load 2) Add the following description of "Load": A "Load" is an input only device that can have analog loading effects on the circuit being simulated but has no digital logic thresholds. Examples of "Loads" are: Capacitors, Termination Diodes, Pullup resistors etc. NOTE TO IBIS COMITTEE: I believe that all of the above "Loads" can be defined inside of the current IBIS specification JNP. I understand that there are other efforts in effect to expand this definition but those definitions should be able to supercede "Load" with no significant effect on this bird. 3) Add the following requirements to [Model]: The model types Input, I/O, I/O_open_drain, I/O_open_sink, I/O_open_soure must have Vinl and Vinh defined. If they are not defined, the parser will issue a warning and the default values of Vinl=.8V and Vinh=2.0V will be assumed. The model types Input_ECL and I/O_ECL must have Vinl and Vinh defined. If they are not defined, the parser will issue a warning and the default values of Vinl=-1.475V and Vinh=-1.165V will be assumed. NOTE TO IBIS COMITTEE: ECL defaults derived from FAIRCHILD F100K ECL data book specification of Guaranteed input HIGH and LOW. 4) The following is added to the differential specification to clarify Differential input threshold: If a pin is a differential input pin the differential input threshold (vdiff) overrides and supercedes the need for Vinh and Vinl. If vdiff is not defined for a pin that is defined as requiring a Vinh by its [Model] type, the parser will issue a warning and vdiff will be set to the default value of 200mV. 5) The golden parser must be modified to allow (1) and (4) and check for (3) and (4). ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Although it makes sense to require input thresholds for all of the [Model] types currently in the IBIS specification, it also makes sense for there to be devices that have no digital logic threshold. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: The section on DIFFERENTIAL can be struck if there is argument, but note that we currently have overlapping defintions of input Thresholds on differential input pins. ******************************************************************************* From Arpad_Muranyi@ccm.fm.intel.com Tue Apr 26 14:51:43 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA19235; Tue, 26 Apr 94 14:51:43 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pvuzU-000MNXC; Tue, 26 Apr 94 14:48 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Tue, 26 Apr 94 14:48:27 PST Date: Tue, 26 Apr 94 14:48:27 PST From: Arpad Muranyi Message-Id: <940426144827_3@ccm.hf.intel.com> To: ibis@vhdl.org Subject: A little more to add to Arpad's response to Quad article. ---------------------------- Forwarded with Changes --------------------------- From: bward@dadhb1.ti.com at Internet_Gateway Date: 4/26/94 1:55PM *To: ibis@vhdl.org at Internet_Gateway Subject: A little more to add to Arpad's response to Quad article. ------------------------------------------------------------------------------- Bob, I am curious how these measurements were done. Can you give a short description on it? Do your bulk resistances include the drain or source resistances (in series with the bulk) or are they strictly bulk? Arpad At this time I will comment only on the size of bulk resistances. Reading Arpad's response makes me want to go back and reread the article for the math's sake, but I have not done so yet. But, interestly enough, I have just gotten the result of some lab work to measure several bulk resistances for several transistors of several constructions. Realistic values ran in the range 4 ohms to 30 ohms depending on the nature of the well in which the transistor is formed and on whether it was from an epitaxial or non epitaxial process. It was surpringly constant WRT n-type p-type with the main variation being epi or non-epi. As a matter of fact two clusters were formed, one from about 4 to 8.5 ohms and one from about 19 to 30 ohms. ============================================================================= __ / / \ / / Bob Ward /__ / / / / / / MSG: SQU / \ _ /_ / / / _ __ _ / INET: bward@dadhb1.ti.com (____ / (_)_ /__) (__(__/ (_(_/ (_(_/ 713+274-4146 Voice 713+274-3911 Fax ============================================================================= ___ (o o) -------------------------------ooO-(_)-Ooo----------------------------------- Here I sit in endless joy, 'cause I was here before Kilroy!!! From jonp@qdt.com Tue Apr 26 16:02:39 1994 Return-Path: Received: from relay1.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA19695; Tue, 26 Apr 94 16:02:39 PDT Received: from uucp2.uu.net by relay1.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwniy03866; Tue, 26 Apr 94 19:00:11 -0400 Received: from qdt.UUCP by uucp2.uu.net with UUCP/RMAIL ; Tue, 26 Apr 1994 19:00:11 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA01066; Tue, 26 Apr 94 14:42:00 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA07268; Tue, 26 Apr 94 14:42:00 PDT Date: Tue, 26 Apr 94 14:42:00 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404262142.AA07268@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA01581; Tue, 26 Apr 94 14:42:08 PDT To: bward@dadhb1.ti.com Cc: ibis@vhdl.org In-Reply-To: Bob Ward's message of Tue, 26 Apr 94 13:57:41 -0500 <9404261857.AA04127@emu.dadhb1.ti.com> Subject: Clarification on monotonicity BOb, you are the sly dog with the ascii waveforms. Look, when you draw load lines on an IV curve, don't they run the other way? Like if I were to draw a 50 ohm to 5 volt wouldn't it look like: I * | * | * | * | * | * | * | * | * | * | * | *| ---------------+------.------------- V | * . | *. | . * | . * | . * |. * | * | * | * | * | * now I really have to get out my graph paper. jonp From 71436.1314@CompuServe.COM Wed Apr 27 09:53:30 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from arl-img-2.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00385; Wed, 27 Apr 94 09:53:30 PDT Received: from localhost by arl-img-2.compuserve.com (8.6.4/5.930129sam) id MAA21456; Wed, 27 Apr 1994 12:51:08 -0400 Date: 27 Apr 94 12:47:08 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Re: BIRD 12, non-linear ramps Message-Id: <940427164707_71436.1314_HHB63-3@CompuServe.COM> From: Kellee Crisafulli, HyperLynx I really like the concept you are working on with bird 12. However I am concerned about how various simulators will use the data. I don't believe the proposed specification goes far enough in explaining what the simualtor should model. This a really nice specification from the stand point of the expected output at a single load point. If we don't specify in more detail what the simulators are suppose to do I am concerned that they will not produce the same results. Is there a way to define this information in terms of the original SPICE model created by INTEL. I could guess at what might be done, however if you have already played with this it might be very useful. A postscript file like Jon sent might be a good way to communicate this. Also how are the load components connect? I have a pretty good guess, but I would like to see this in the specification also. R_load 50 V_load 1.5 C_load 10p L_load 2n This is a great start on the BIRD... Kellee From 71436.1314@CompuServe.COM Wed Apr 27 09:54:02 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from arl-img-2.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00392; Wed, 27 Apr 94 09:54:02 PDT Received: from localhost by arl-img-2.compuserve.com (8.6.4/5.930129sam) id MAA21521; Wed, 27 Apr 1994 12:51:40 -0400 Date: 27 Apr 94 12:47:09 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Clarification, please, on monotonicity Message-Id: <940427164709_71436.1314_HHB63-4@CompuServe.COM> From: Kellee Crisafulli, HyperLynx RE: your question about monotonic behavior. I agree with Jon. I believe we are concerned about not having the simulators go into an unrealistic oscillation. I believe most simulators will be stable with a constant sign or 0. I.E. it would be OK to have flat spots. Have a great day... Kellee From 71436.1314@CompuServe.COM Wed Apr 27 09:54:07 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from arl-img-2.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00398; Wed, 27 Apr 94 09:54:07 PDT Received: from localhost by arl-img-2.compuserve.com (8.6.4/5.930129sam) id MAA21529; Wed, 27 Apr 1994 12:51:42 -0400 Date: 27 Apr 94 12:47:11 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Measurement conditions BIRD, bird on Temperature Message-Id: <940427164710_71436.1314_HHB63-5@CompuServe.COM> From Kellee: Bob, your proposed Bird on operating temperature looks good, it needs some formating clean however. I don't see any problems with the concepts. Good ideas... From bob@icx.com Wed Apr 27 10:36:05 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01064; Wed, 27 Apr 94 10:36:05 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA21877 for ; Wed, 27 Apr 94 13:06:14 -0400 Date: Wed, 27 Apr 94 09:49:31 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA17493; Wed, 27 Apr 94 09:49:31 PDT Message-Id: <9404271649.AA17493@icx.com> To: ibis@vhdl.org Subject: LEVELS OF SUPPORT To IBIS Committee: IBIS Version 2.0 will represent a substantial increase in functionality over Version 1.1. All of the proposed advances really do relate to the real modeling challenges we are facing. IBIS Version 2.0 will be very valuable for specifying the format for the advances. I am glad to see "levels of support" on the agenda. I expect that most simulators are not structured to handle ALL of the planned extensions. For guidance, I would proposed that all Version 2.0 compliant parsers be able to read files with ANY of the FINALIZED Version 2.0 extensions. They MUST be able to work with LEVEL 1 extensions. They MAY work with ANY of the LEVEL 2 extensions or take some alternative action including doing nothing, issuing a warning message, or substituting a Version 1.1 compliant action (e.g., use [Ramp] instead of using non-linear waveforms). Here are my thoughts at classifying the approved and pending BIRDS and EGGS into level 1 and 2 categories. Category of Functionality Status Level 1. IBIS VERSION 1.1 APPROVED 1 2. FUNDAMENTAL FUNCTIONALITY ADDITIONS BIRD 3 - MULTIPLE POWER SUPPLY LEVELS APPROVED 1 BIRD 4 - ECL EXTENSIONS APPROVED 1 BIRD 7.2 - OPEN SPECIFICATION COMPLETION APPROVED 1 BIRD 9.2 - TERMINATOR SPECIFICATION PENDING 2 3. MULTIPLE PIN RELATIONSHIPS BIRD 5.2 - PIN_MAPPING FOR GROUND BOUNCE APPROVED 2 SIMULATION BIRD 6.2 - DIFFERENTIAL PIN SPECIFICATION APPROVED 2 BIRD 10.1 - DESCRIBING COUPLING EFFECTS PENDING 2 IN PACKAGE MODELS 5. SPECIFICATION REFINEMENTS BIRD 2.2 - REQUIRING VIH VIL THRESHOLDS PENDING 1 FOR INPUT DEVICES BIRD 8 - SPECIFICATION OF V/I DATA PENDING 1 MONOTONICITY BIRD 11.2 - IMPROVING COMMON ERROR DETECTION PENDING 1 IN IBIS_CHK PROGRAM 6. DATA DETAIL EXTENSIONS BIRD 12 - NON-LINEAR DRIVER WAVEFORMS PENDING 2 EGG 3 - CLARIFY SOME CONDITIONS OF PENDING 2 MEASUREMENT Bob Ross, Interconnectix, Inc. From cpk@Cadence.COM Wed Apr 27 10:38:34 1994 Return-Path: Received: from mailgate.cadence.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01072; Wed, 27 Apr 94 10:38:34 PDT Received: from localhost (smap@localhost) by mailgate.cadence.com (8.6.4/8.6.4) id KAA21347 for ; Wed, 27 Apr 1994 10:36:12 -0700 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma021304; Wed Apr 27 10:35:48 1994 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA18476; Wed, 27 Apr 94 10:26:10 -0700 Received: by hot (5.65+/1.5) id AA12594; Wed, 27 Apr 94 13:35:24 -0400 Date: Wed, 27 Apr 94 13:35:24 -0400 From: cpk@cadence.com (C. Kumar) Message-Id: <9404271735.AA12594@hot> To: ibis@vhdl.org Subject: Re: BIRD 12, non-linear ramps >Kellee Crisafulli, HyperLynx writes Also how are the load components connect? I have a pretty good guess, but I would like to see this in the specification also. R_load 50 V_load 1.5 C_load 10p L_load 2 I woul also like the connection to be clarified. I also think it is unnecessary to put the word non-linear in the non-linear ramp. Non-linear has other connotations. A linear ramp can be produced by highly non-linear drivers for example. My point is that the non-linea rnon-linear ramp does not necessarily indicate a more complex model for the output. - kumar From speters@ichips.intel.com Wed Apr 27 10:58:31 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01238; Wed, 27 Apr 94 10:58:31 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 27 Apr 94 10:56:09 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Wed, 27 Apr 94 10:55:47 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Wed, 27 Apr 94 10:56:02 PDT Message-Id: <9404271756.AA25107@xtg801.intel.com> To: ibis@vhdl.org Subject: RE[1]: bird 12, non-linear waveforms Date: Wed, 27 Apr 1994 10:56:01 -0700 From: Stephen Peters Hello Kellee and Kumar and Fellow IBISians -- Thanks for your comments. To clarify the R_load, V_load, etc. connections, they are as follows: __________________ | | | | L_load R_load | OUTPUT MODEL |-----@@@@@------------/\/\/\----- V_load | | | | | | ------------------ ---- C_load ---- | | gnd The L_load and R_load parameters are the same as the L_pkg and C_pkg parameters in the pin spec. As far as Kellee's comments (as I understand them) about telling the simulator what to do with the data: I keep thinking back to what Bob Ross said at the last open forum about IBIS being a 'data transfer standard'. The purpose of Bird 12 is to allow IBIS to include another specific piece of information that more fully describes a device's characteristics. How a simulator vendor uses the information is up to them; I don't think IBIS can dictate that. See (hear) you all friday... Best Regards, Stephen Peters Intel Corp. From jonp@qdt.com Wed Apr 27 11:21:42 1994 Return-Path: Received: from relay1.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01390; Wed, 27 Apr 94 11:21:42 PDT Received: from uucp6.UU.NET by relay1.UU.NET with SMTP (5.61/UUNET-internet-primary) id AAwnlx12892; Wed, 27 Apr 94 14:18:59 -0400 Received: from qdt.UUCP by uucp6.UU.NET with UUCP/RMAIL ; Wed, 27 Apr 1994 14:19:13 -0400 Received: from sal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00802; Wed, 27 Apr 94 11:12:55 PDT Received: from f14.qdt.com by sal.qdt.com (4.1/SMI-4.1) id AA10672; Wed, 27 Apr 94 11:12:54 PDT Date: Wed, 27 Apr 94 11:12:54 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9404271812.AA10672@sal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA00718; Wed, 27 Apr 94 11:12:53 PDT Cc: ibis@vhdl.org In-Reply-To: Kellee Crisafulli's message of 27 Apr 94 12:47:08 EDT <940427164707_71436.1314_HHB63-3@CompuServe.COM> Subject: BIRD 12, non-linear ramps As far as different simulators getting different results. The correct answer is the input data itself (which is the cool thing about this approach). If you don't get that you are wrong. Getting close to that is the old competition game. And once again, someone might use this data for doing a simulation that produces no waveforms (just delay etc.). jonp From Arpad_Muranyi@ccm.fm.intel.com Wed Apr 27 12:41:50 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02060; Wed, 27 Apr 94 12:41:50 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pwFRI-000MNNC; Wed, 27 Apr 94 12:38 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Wed, 27 Apr 94 12:38:32 PST Date: Wed, 27 Apr 94 12:38:32 PST From: Arpad Muranyi Message-Id: <940427123832_2@ccm.hf.intel.com> To: ibis@vhdl.org Subject: New bird flying by, see if you can catch it... Text item: Text_1 Buffer Issue Resolution Document (BIRD) BIRD ID#: ISSUE TITLE: Adding a new section for [Model] sub-parameters REQUESTER: John Keifer at Intel DATE SUBMITTED: April 26, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: ************************************************************************* ************************************************************************* STATEMENT OF THE ISSUE: It is desirable to have two new sub-parameters added to a [Model] in order to fully represent the characteristics of a given component's I/O cells. These sub-parameters are desirable for the user of the IBIS [Models] who wishes to perform board level simulations. It is also desirable to have a new optional keyword added to the top of an .IBS file in order to parameterize the sub-parameters of a [Model] so that each time a [Model] is used with a different sub-parameter a new [Model] would not have to be made. ************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: A new keyword, [SPECS], is added to the .IBS file. The keyword [SPECS] and all of its sub-parameters are optional. The sub-parameters under this keyword override the sub-parameters of a [Model]. Only those pins should be listed in the [SPECS] section which need to override the default sub-parameters of a [Model]. All sub-parameters must be filled in on a line either with NA or a value. Two new sub-parameters, Cref (a reference specload) and Vt (a test voltage), are added to a [Model]. These sub-parameters are also optional. |************************************************************************* | | Keyword: [SPECS] | Required: No |Description: Used to list pin-level specifications that differ from | the more global sub-params listed under [Model] below. | Sub-Params: Vinl, Vinh, Vt, Cref, C_comp |Usage Rules: Only pins that have values different from the default | values specified in [Model] sub-parameters should be | listed. Sub-parameters not used on a line must be | filled in with NA. | The [SPECS] section consists of five characters for a | pin number, six for Vinl, six for Vinh, five for Vt, | five for Cref, and six for each of the three | sub-parameters in C_comp. These three sub-parameters | represent the following: typ, min, and max. All | sub-parameters must be separated by at least one | blank space. This comes to a total of fifty-two | characters. | |************************************************************************* Example: Pin1 = I/O, Pin4 = Output/3-state, Pin9 = Input [SPECS] | C_comp Pin Vinl Vinh Vt Cref typ min max 1 0.8V 2.0V 1.5V 50pF 4.5pF 3.0pF 6.0pF 4 NA NA 2.5V 30pF NA NA NA 9 1.5V 3.5V NA NA NA NA NA This section will be placed directly underneath the pin list (the [Pin] keyword section). The [Model] section should be changed as shown below, only changes are listed. |************************************************************************* | | Keyword: [Model] | . | . | Sub-Params: ..., Vt, Cref | | Other Notes: ... Component timings are usually specified into a | reference capacitance that can be listed as Cref. Vt is | the test voltage at a driver that timings are specified | to. (This is usually around the 50% level of the voltage | thresholds. For example, TTL=1.5V, CMOS=2.5V.) | |************************************************************************* Example: [Model] IB080812 Model_type I/O Polarity Non-Inverting Enable Active-High | Signals A[2-17] Vinl = 0.8V Vinh = 2.0V Vt=1.5V |Test voltage timings are specified to Cref=50pF |Reference capacitance timings are specified into The Cref and Vt sub-parameters would be placed inside each [Model] file, after Vinh. ************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Presently if a particular [Model] needs to be used for a couple of buffers in which the only differences are in the Vinl, Vinh, or C_comp sub-parameters, separate [Model]s have to be made. With the [SPECS] keyword, only one [Model] has to be made with the sub-parameters being passed down from the [SPECS] section. This feature will reduce the size of the .IBS file. The [SPECS] section allows separating the details from the core of a [Model], and at the same time, gives the user the sub-parameters he needs. The [SPECS] keyword is also optional and hence fully backward compatible. The keywords Cref and Vt and all other sub-parameters of a [Model] are to be used as default values only. All sub-parameters in a [Model] are overriden by any values listed in the [SPECS] section. All of the data in the [SPECS] section, Cref, and Vt is standard data available in data books. Allowing the specification of Cref and Vt enhances the usability of an IBIS model by providing key parameters for simulation. ************************************************************************* ANY OTHER BACKGROUND INFORMATION: ************************************************************************* From Will_Hobbs@ccm2.jf.intel.com Wed Apr 27 13:31:50 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02398; Wed, 27 Apr 94 13:31:50 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 27 Apr 94 13:28:18 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 27 Apr 94 13:27:58 -0700 Received: from ccMail by jfsmt2.intel.com id AA767478500 Wed, 27 Apr 94 13:28:20 PDT Date: Wed, 27 Apr 94 13:28:20 PDT From: "Hobbs, Will" Message-Id: <9403277674.AA767478500@jfsmt2.intel.com> To: ibis@vhdl.org, bob@icx.com ( Bob Ross) Subject: Re: LEVELS OF SUPPORT Bob, Thanks for posting this to prime a discussion. You picked up on what the agenda item is about. For anyone that didn't pick up on the gist of the subject, in our December 3 meeting, we dicussed dividing new IBIS features into levels so we wouldn't raise the entry bar too high for new simulators. This is an appropriate time to re-open that discussion. Will Hobbs To IBIS Committee: IBIS Version 2.0 will represent a substantial increase in functionality over Version 1.1. All of the proposed advances really do relate to the real modeling challenges we are facing. IBIS Version 2.0 will be very valuable for specifying the format for the advances. I am glad to see "levels of support" on the agenda. I expect that most simulators are not structured to handle ALL of the planned extensions. For guidance, I would proposed that all Version 2.0 compliant parsers be able to read files with ANY of the FINALIZED Version 2.0 extensions. They MUST be able to work with LEVEL 1 extensions. They MAY work with ANY of the LEVEL 2 extensions or take some alternative action including doing nothing, issuing a warning message, or substituting a Version 1.1 compliant action (e.g., use [Ramp] instead of using non-linear waveforms). Here are my thoughts at classifying the approved and pending BIRDS and EGGS into level 1 and 2 categories. Category of Functionality Status Level 1. IBIS VERSION 1.1 APPROVED 1 2. FUNDAMENTAL FUNCTIONALITY ADDITIONS BIRD 3 - MULTIPLE POWER SUPPLY LEVELS APPROVED 1 BIRD 4 - ECL EXTENSIONS APPROVED 1 BIRD 7.2 - OPEN SPECIFICATION COMPLETION APPROVED 1 BIRD 9.2 - TERMINATOR SPECIFICATION PENDING 2 3. MULTIPLE PIN RELATIONSHIPS BIRD 5.2 - PIN_MAPPING FOR GROUND BOUNCE APPROVED 2 SIMULATION BIRD 6.2 - DIFFERENTIAL PIN SPECIFICATION APPROVED 2 BIRD 10.1 - DESCRIBING COUPLING EFFECTS PENDING 2 IN PACKAGE MODELS 5. SPECIFICATION REFINEMENTS BIRD 2.2 - REQUIRING VIH VIL THRESHOLDS PENDING 1 FOR INPUT DEVICES BIRD 8 - SPECIFICATION OF V/I DATA PENDING 1 MONOTONICITY BIRD 11.2 - IMPROVING COMMON ERROR DETECTION PENDING 1 IN IBIS_CHK PROGRAM 6. DATA DETAIL EXTENSIONS BIRD 12 - NON-LINEAR DRIVER WAVEFORMS PENDING 2 EGG 3 - CLARIFY SOME CONDITIONS OF PENDING 2 MEASUREMENT Bob Ross, Interconnectix, Inc. From Will_Hobbs@ccm2.jf.intel.com Wed Apr 27 17:42:19 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04219; Wed, 27 Apr 94 17:42:19 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 27 Apr 94 17:39:57 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 27 Apr 94 17:38:50 -0700 Received: from ccMail by jfsmt2.intel.com id AA767493528 Wed, 27 Apr 94 17:38:48 PDT Date: Wed, 27 Apr 94 17:38:48 PDT From: "Hobbs, Will" Message-Id: <9403277674.AA767493528@jfsmt2.intel.com> To: ibis@vhdl.org, Derrick_Duehren@ccm2.jf.intel.com Subject: Bird 13, Measurement condition clarification ****************************************************************************** ****************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 13.0 ISSUE TITLE: Clarify Some Conditions of Measurements REQUESTOR: Bob Ward, Texas Instruments DATE SUBMITTED: April 22, 1994 DATE REVISED: DATE ACCEPTED BY IBIS OPEN FORUM: pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Certain statements are made in the Version 1.1 standard that need clarification for the sake of newcomers to the Ibis community regarding the conditions under measured data is taken. These changes bring the standard more into line with the discussions on the forum and the cookbook, which is taken to reflect the intention and not just the letter of the specification. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The majority of the change is to the NOTES TO DATA DERIVATION METHOD section of the spec. In paragraph numbered 1) Old text is: | V/I Curves for CMOS devices: | typ = nominal voltage, 50 degrees C, typical process | min = low voltage tol, 100 degrees C, typical process, minus "X%" | max = hi voltage tol, 0 degrees C, typical process, plus "X%" | | V/I curves for bipolar devices: | typ = nominal voltage, 50 degrees C, typical process | min = low voltage tol, 0 degrees C, typical process, minus "X%" | max = hi voltage tol, 100 degrees C, typical process, plus "X%" Proposed text is: | V/I Curves for CMOS devices: | typ = nominal voltage, nominal temperature deg C, typical process | min = low voltage tol, max temperature deg C, typical process, minus"X%" | max = hi voltage tol, min temperature deg C, typical process, plus "X%" | | V/I curves for bipolar devices: | typ = nominal voltage, nominal temperature deg C, typical process | min = low voltage tol, max temperature deg C, typical process, minus "X%" | max = hi voltage tol, min temperature deg C, typical process, plus "X%" | | where nominal, min, and max temperature are specified by the manufacturer | of the part. The preferred range is 50C nom, 0C min and 100C max | temperatures. Add after the end of paragraph numbered 2) and before 3): These voltage ranges apply to simulation derived data. Data derived from lab measurements should be taken as near to this range as equipment will allow ( e.g. a curve tracer may limit current to nondestructive values even at these voltage extremes ) or as limited by manufacturer specified absolute maximum voltages. Add in paragraph numbered 3) after step 3 and before step 4 the following note: There may be devices which will not drive a load of only 50 ohms into any useful level of dynamics. In these cases use the manufacturers suggested ( non-reactive ) load and add the load sub parameter to the [Ramp] specification. Under the heading Ramp times for CMOS devices, make the same temperature specifications as above. Add a note after step 7. in the same section that during the ramp measurements the driving waveform should be of a rise/fall time typical of the actual circuit in operation. Also the driving waveform should not have sharp breakpoints at the top and bottom of the edges, but should be slightly rounded to avoid artificial high frequency effects. Add specification of the sub parameter 'load' to the [Ramp] keyword. Under Keyword: [Ramp] change Sub-Params: dV/dt_r, dV/dt_f, load Add text to the Usage Rules: The load sub-parameter is optional if the preferred 50 ohm load is used. It is required if a non-standard load is used. Add to the example as follows: [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n load 300ohms Add after the [Voltage range] keyword discussion: |============================================================================== | | Keyword: [Temperature range] | | Required: Yes, if other than the preferred 0, 50, 100 degree C range | | Description: Used to define the temperature range over which the model is | to operate. | | Usage Rules: Actual temperatures (not percentages) are to be presented in | the usual typ, min, max format. "NA" is not allowed. | | Other Notes: [Temperature range] also describes the temperature range over | which the various V/I curves and ramp rates were derived. |------------------------------------------------------------------------------ | variable typ min max [Temperature range] 27.0C -50C 130.0C ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: {There are many "experts" reviewing this document. Your reasons, analysis, and justifications must be precise and well documented, or your BIRD will be sent back to you. Use this section to show that you've done your homework, and answer all questions that will undoubtedly be asked. If your issue is a change instead of an enhancement, document how backward compatibility is to be addressed.} The spec should have flexibility enough to handle models of parts manufactured to MIL spec and automotive spec as well as parts for special purposes which are perhaps more sensitive than even consumer or commercial spec allows. Thus the relaxation , or tightening as the case may be, of the temperature and voltage range mandates. The added keyword and sub-parameter are to allow the simulator usable specification of the relaxed or tightened ranges for the relevant measurements. The ramp rate is still mandated to be determined between 20 and 80 % of actual swing to promote the linearity of the measured portion of the edge. The load is mandated to be non-reactive so as to preserve the inherent dynamics of the driver, and not introduce false dynamics due to the load. Backward compatibility is addressed by making the new specifications optional if the preferred voltage and temperature ranges and load resistance are used. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: N/A ****************************************************************************** From Will_Hobbs@ccm2.jf.intel.com Wed Apr 27 17:42:22 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04220; Wed, 27 Apr 94 17:42:22 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 27 Apr 94 17:39:59 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 27 Apr 94 17:38:52 -0700 Received: from ccMail by jfsmt2.intel.com id AA767493538 Wed, 27 Apr 94 17:38:58 PDT Date: Wed, 27 Apr 94 17:38:58 PDT From: "Hobbs, Will" Message-Id: <9403277674.AA767493538@jfsmt2.intel.com> To: ibis@vhdl.org Cc: Arpad_Muranyi@ccm.fm.intel.com Subject: Bird 14, [Model] sub-parameters section ************************************************************************* ************************************************************************* Buffer Issue Resolution Document (BIRD) BIRD ID#: 14 ISSUE TITLE: Adding a new section for [Model] sub-parameters REQUESTER: John Keifer at Intel DATE SUBMITTED: April 26, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ************************************************************************* ************************************************************************* STATEMENT OF THE ISSUE: It is desirable to have two new sub-parameters added to a [Model] in order to fully represent the characteristics of a given component's I/O cells. These sub-parameters are desirable for the user of the IBIS [Models] who wishes to perform board level simulations. It is also desirable to have a new optional keyword added to the top of an .IBS file in order to parameterize the sub-parameters of a [Model] so that each time a [Model] is used with a different sub-parameter a new [Model] would not have to be made. ************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: A new keyword, [SPECS], is added to the .IBS file. The keyword [SPECS] and all of its sub-parameters are optional. The sub-parameters under this keyword override the sub-parameters of a [Model]. Only those pins should be listed in the [SPECS] section which need to override the default sub-parameters of a [Model]. All sub-parameters must be filled in on a line either with NA or a value. Two new sub-parameters, Cref (a reference specload) and Vt (a test voltage), are added to a [Model]. These sub-parameters are also optional. |************************************************************************* | | Keyword: [SPECS] | Required: No |Description: Used to list pin-level specifications that differ from | the more global sub-params listed under [Model] below. | Sub-Params: Vinl, Vinh, Vt, Cref, C_comp |Usage Rules: Only pins that have values different from the default | values specified in [Model] sub-parameters should be | listed. Sub-parameters not used on a line must be | filled in with NA. | The [SPECS] section consists of five characters for a | pin number, six for Vinl, six for Vinh, five for Vt, | five for Cref, and six for each of the three | sub-parameters in C_comp. These three sub-parameters | represent the following: typ, min, and max. All | sub-parameters must be separated by at least one | blank space. This comes to a total of fifty-two | characters. | |************************************************************************* Example: Pin1 = I/O, Pin4 = Output/3-state, Pin9 = Input [SPECS] | C_comp Pin Vinl Vinh Vt Cref typ min max 1 0.8V 2.0V 1.5V 50pF 4.5pF 3.0pF 6.0pF 4 NA NA 2.5V 30pF NA NA NA 9 1.5V 3.5V NA NA NA NA NA This section will be placed directly underneath the pin list (the [Pin] keyword section). The [Model] section should be changed as shown below, only changes are listed. |************************************************************************* | | Keyword: [Model] | . | . | Sub-Params: ..., Vt, Cref | | Other Notes: ... Component timings are usually specified into a | reference capacitance that can be listed as Cref. Vt is | the test voltage at a driver that timings are specified | to. (This is usually around the 50% level of the voltage | thresholds. For example, TTL=1.5V, CMOS=2.5V.) | |************************************************************************* Example: [Model] IB080812 Model_type I/O Polarity Non-Inverting Enable Active-High | Signals A[2-17] Vinl = 0.8V Vinh = 2.0V Vt=1.5V |Test voltage timings are specified to Cref=50pF |Reference capacitance timings are specified into The Cref and Vt sub-parameters would be placed inside each [Model] file, after Vinh. ************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Presently if a particular [Model] needs to be used for a couple of buffers in which the only differences are in the Vinl, Vinh, or C_comp sub-parameters, separate [Model]s have to be made. With the [SPECS] keyword, only one [Model] has to be made with the sub-parameters being passed down from the [SPECS] section. This feature will reduce the size of the .IBS file. The [SPECS] section allows separating the details from the core of a [Model], and at the same time, gives the user the sub-parameters he needs. The [SPECS] keyword is also optional and hence fully backward compatible. The keywords Cref and Vt and all other sub-parameters of a [Model] are to be used as default values only. All sub-parameters in a [Model] are overriden by any values listed in the [SPECS] section. All of the data in the [SPECS] section, Cref, and Vt is standard data available in data books. Allowing the specification of Cref and Vt enhances the usability of an IBIS model by providing key parameters for simulation. ************************************************************************* ANY OTHER BACKGROUND INFORMATION: ************************************************************************* From 71436.1314@CompuServe.COM Wed Apr 27 21:38:52 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from dub-img-1.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05666; Wed, 27 Apr 94 21:38:52 PDT Received: from localhost by dub-img-1.compuserve.com (8.6.4/5.930129sam) id AAA07799; Thu, 28 Apr 1994 00:36:30 -0400 Date: 28 Apr 94 00:33:19 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: Response to Bob's, 'LEVELS OF SUPPORT' Message-Id: <940428043319_71436.1314_HHB21-2@CompuServe.COM> From: Kellee Crisafulli Bob, I fully 'support' all your choices for levels of support for revision 2.0 of the IBIS specification. Keep up the good work... From 71436.1314@CompuServe.COM Wed Apr 27 21:39:06 1994 Return-Path: <71436.1314@CompuServe.COM> Received: from dub-img-1.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05671; Wed, 27 Apr 94 21:39:06 PDT Received: from localhost by dub-img-1.compuserve.com (8.6.4/5.930129sam) id AAA07817; Thu, 28 Apr 1994 00:36:45 -0400 Date: 28 Apr 94 00:33:18 EDT From: Kellee Crisafulli <71436.1314@CompuServe.COM> To: IBIS ALL Subject: BIRD 12, non-linear ramps, response to Jon from Kellee Message-Id: <940428043317_71436.1314_HHB21-1@CompuServe.COM> From: Kellee Crisafulli To: Jon and IBISians From: Jon As far as different simulators getting different results. The correct answer is the input data itself (which is the cool thing about this approach). If you don't get that you are wrong. Getting close to that is the old competition game. jonp I think I didn't present my point well enough. I understand that the data would be used to validate the model for a given load. I was hoping that the data would also be used to produce simulation results. It then becomes modeling information not just validation information. And the question is does the model work for other load conditions! Is the intent to use this data only to validate models? Have a great day... Kellee From Will_Hobbs@ccm2.jf.intel.com Wed Apr 27 23:27:02 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06240; Wed, 27 Apr 94 23:27:02 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 27 Apr 94 23:24:41 -0700 Received: from jfsmt2 by ichips.intel.com (5.64+/10.0i); Wed, 27 Apr 94 23:24:21 -0700 Received: from ccMail by jfsmt2.intel.com id AA767514291 Wed, 27 Apr 94 23:24:51 PDT Date: Wed, 27 Apr 94 23:24:51 PDT From: "Hobbs, Will" Message-Id: <9403277675.AA767514291@jfsmt2.intel.com> To: Kellee Crisafulli <71436.1314@CompuServe.COM>, ibis@vhdl.org Subject: BIRD 12, non-linear ramps, response to Jon from Kellee Kellee and others, The intent of the Bird is to present ramps that deviate significantly from the straight line currently supported in V1.1, such as those exhibited by controlled slew rate devices. The bonus that Jon pointed out is that the ramp curve itself provides a way of verifying the simulation, simply by simulating the model into the load used to derive the ramp curve in the first place. Additional ramps could be added to provide golden waveforms into other loads, which can be specified using the other elements in the Bird. By the way, I strongly hope to get this Bird, as modified by Forum discussion, into V2.0, since it overcomes the one glaring artificial linear element in the original spec. The strength of IBIS is that it allows second order effects to be simulated, but the single-value ramp rate limits its ability to work with a whole class of devices we are currently struggling to model. Will From: Kellee Crisafulli To: Jon and IBISians From: Jon As far as different simulators getting different results. The correct answer is the input data itself (which is the cool thing about this approach). If you don't get that you are wrong. Getting close to that is the old competition game. jonp I think I didn't present my point well enough. I understand that the data would be used to validate the model for a given load. I was hoping that the data would also be used to produce simulation results. It then becomes modeling information not just validation information. And the question is does the model work for other load conditions! Is the intent to use this data only to validate models? Have a great day... Kellee From Derrick_Duehren@ccm2.jf.intel.com Thu Apr 28 13:08:53 1994 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15382; Thu, 28 Apr 94 13:08:53 PDT Received: from ccm.hf.intel.com by ormail.intel.com (Smail3.1.28.1 #2) id m0pwcKy-000MNuC; Thu, 28 Apr 94 13:05 PDT Received: by ccm.hf.intel.com (ccmgate 3.0) Thu, 28 Apr 94 13:05:32 PST Date: Thu, 28 Apr 94 13:05:32 PST From: Derrick Duehren Message-Id: <940428130532_3@ccm.hf.intel.com> To: IBIS@vhdl.org Subject: IBIS Minutes 4/15/94 Text item: Text_1 My apologies I thought I had sent out the minutes, but looking back at my mail log, it appears that I didn't. Here they are. - Derrick ---------------------------------------------------------------------------- Date: April 20, 1994 From: Will Hobbs (503) 696-4369, fax (503) 696-4210 Will_Hobbs@ccm2.jf.intel.com XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum Intel Corporation 5200 NE Elam Young Pkwy, Hillsboro, Oregon 97124 USA and Derrick Duehren (503) 696-4299, fax (503) 696-4904 Derrick_Duehren@ccm.jf.intel.com Intel Program Manager Subject: Minutes from IBIS Open Forum 4/15/94 To: Anacad Steffen Rochel Ansoft Henri Maramis Atmel Corporation Dan Terry Cadence Design Sandeep Khanna, Chris Reed, Kumar* Contec Maah Sango, Clark Cochran Digital Equipment Corp. Barry Katz* High Design Technology Michael Smith HyperLynx Steve Kaufer, Kellee Crisafulli IBM Jay Diepenbrock IBM-Motorola alliance Lynn Warriner, Hoa Quoc, John Burnett Integrity Engineering Greg Doyle, Wayne Olhoft Intel Corporation Stephen Peters*, Don Telian, Will Hobbs* Arpad Muranyi*, D. Duehren*, Lisa Huang Interconnectix, Inc. Bob Ross* Intergraph Ian Dodd, David Wiens IntuSoft Charles Hymowitz Logic Modeling Corp. Randy Harr Mentor Graphics Greg Seltzer, Ravender Goyal Meta-Software Mei Wong, Mei-Ling Wei MicroSim Arthur Wong, Jerry Brown, Graham Bell National Semiconductor Syed Huq* North Carolina State U. Paul Franzon, Michael Steer, Steve Lipa Performance Signal Integrity Vivek Raghawan, Eric Bracken* Quad Design Jon Powell* Quantic Labs Mike Ventham, Zhen Mu Racal-Redac John Berrie Siemens Nixdorf Werner Rissiek*, Olaf Rethmeier Texas Instruments Bob Ward* Thomson-CSF/SCTF Jean Lebrun Zeelan Technology Hiro Moriyasu, George Opsahl* CC: Intel Corporation Randy Wilhelm, Jerry Budelman, Intel IBIS team In the list above, attendees at the 4/15/94 meeting are indicated by * Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences are listed below: Date Bridge Number Reservation # 4/29/94 (415) 904-8944, 721618 5/13/94 (415) 904-8944, 721619 5/20/94 Face-to-face, editing committee All meetings are 8:00 AM to 10:00 AM PST (15:00 to 17:00 UTC). We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum and give the bridge operator the reservation number. If you know of someone new who wants to join the e-mail reflector (ibis@vhdl.org) send e-mail to ibis-request@vhdl.org. NOTE: "AR" = Action Required. ************************************************************************ ****** General Announcement ******* ****** We will attempt to come to closure on all BIRDs ******* ****** through BIRD 11 at the 4/29/94 meeting. ******* ************************************************************************ ------------------------------------------------------------------------ 4/15/94 Meeting Agenda ---------------------- Check-in Intros of new IBIS participants Hobbs Review of previous meeting's minutes Hobbs Miscellany/Announcements Hobbs Opens for new issues All New models available All IBIS 2.0 Ratification/DAC Hobbs, Ward - Rev 2.0 Ratification Summit (6/9) - Birds of a Feather session (6/8) IBIS Cookbook Hobbs BIRD 8, Spec. of V/I data monotonicity Crisafulli BIRD 9, Other model types Ross BIRD 10, Coupling effects in package models Bracken BIRD 11, Sign of current checking Hobbs, All Egg 2, Variable ramp Peters BIRD 2, VIH, VIL Thresholds for Inputs Powell Simulation temperatures (new BIRD?) Warriner Ramp measurement Reid, Ross, et. al. Wrap-up, Next Meeting Plans Hobbs From this point on, we propose tabling until after 2.0: Formal BNF notation (BIRD?) Reed, Harr High freq. and EMI Goyal, et. al. Phased turn-on/off of multiple devices Powell 1. Intros of new IBIS participants New participants: None. 2. Review of Pervious Meeting's Minutes There were no corrections made to last month's minutes. 3. Miscellany/Announcements We have been experiencing problems on the reflector/internet (messages bouncing, 3 attempts to get agenda out with delayed acknowledge to sender but everyone got it 3 times, etc. AR Derrick: See if anything can be done to improve the internet/reflector performance. Derrick suggested eliminating non-active people from this document's to: list as participants are also listed in the roster document. Consensus was to leave the list as it is. 4. Opens for new issues Add to the agenda, Non-monotonic data (Muranyi/Powell) Derrick is converting the IBIS Overview document into an EDN article. An abstract has been sent to EDN, which has acknowledged, but no activity. 5. New models available 6. IBIS 2.0 Ratification/DAC - May 20 Editing Committee AR Derrick: Get room, time, hotel info out to May 20 participants within next week. AR Will: Engage Paul Munsey after 5/20 for parsability study of the proposed version 2.0 to minimize a need for a version 2.1 soon after 2.0. - Rev 2.0 Ratification Summit (6/9/94) AR Kumar: Arrange a room for 2.0 ratification session, all day, preferably at the conference, though possibly at the Cadence office in San Diego. - Birds of a Feather session (6/8/94) 11 RSVPs so far, meeting 10 minimum, DAC will assign room at the Marriot, overhead, etc. Will will give quick (5-7 minutes) icebreaker intro to the group at 5:30 p.m., then open the discussion to everyone. Bob Ward is also getting posters made by a graphic artist using IBIS logos from an Intel artist. Any additional people planning to attend should sign up when they register for DAC. 9. IBIS Cookbook The cookbook is in the second round of internal review. It may be ready for limited review by participants as early as the next (4/29) meeting. Those who would like to participate in the review should send email requests to Derrick. 11. BIRD 8, Spec. of V/I data monotonicity Kellee was not present -- no discussion. 12. BIRD 9, Other model types Bob Ross recapped the additional components added to the BIRD (series, ac terminators). Stephen is concerned about the fact we have no way to tell how series resistors connect in a package. Arpad: Does this address terminators in buffers or separately? Bob R: this is a problem; it is intended to represent terminations, but it is stated as if it is part of a buffer. Bob W: is this a simple, pure resistor, or a saturable resistor? Bob R: simple resistor. Other discussion addressed series diodes, saturable r-packs (do such things exist?), etc. Arpad: "IBIS was intended to be a buffer description, and BIRD 9 looks like we are trying to extend it to include more general components. This may be valid, but that wasn't the original intent." Jon sees it as just a way to get data from vendors to simulators. Kumar and others feel we should not make IBIS too general yet. Bob is willing to withdraw the BIRD as it is at this time, since it appears we can't reach consensus and defer it to post-2.0 discussions. Bob W. will consider generating BIRD 9.2 for 2.0 consideration, focusing solely on termination packages, without series resistors being addressed. 13. BIRD 10, Coupling effects in package models Eric will update the BIRD to include alphanumeric pin names for PGA-type packages. Eric posed the question of whether we want to include package data in same file rather than in a separate file, which generated a lengthy discussion discussing the pros and cons of each approach. Single-file approach: + Keeps everything together - Libraries of devices that share package types will require much more storage space if package info is duplicated in each file. Multiple-file approach: + Enables mix and match buffer descriptions with various packages (multiple models, 1 package description; multiple packages, 1 model) + Enables easy updates to packages that affect a library of parts. - Potential for filename overlaps, esp. with 8/3 character DOS filename limitation. (File name inside file could be required to include creation date, etc. to ensure it is unique. Company codes?) = Package and model-description files should be kept in the same directory. We need a model moderator for vhdl.org to pass files through the Golden Parser and to avoid same-name different models. We will talk about this at DAC. Consensus was reached that we will allow separate package models. We need to make clear that we are not excluding nor mandating sparse versus banded versus full matrix representation. AR Eric: Create BIRD 10.1 with alphanumeric pin names, and make it explicit that the package model can be either in the file or in a separate .pkg file. We will vote on which takes priority if both exist at the next meeting. 14. BIRD 11, Sign of current checking Kellee was not present. Bob R. questions whether a table of zeros would pass or not? He thinks a slight clarification might be a good idea. The editing committee could clean it up, if needed. Discussion tabled until the next meeting. The Golden Parser is the standard; all rules must be checked by the GP. AR Bob R: Address your concerns with Kellee. 15. Egg 2, Variable ramp Stephen pointed out that this Egg could be used to put out "Golden Waveforms" and "Golden Load Topologies". Jon also suggests that we could avoid the ramp specification altogether if we specified the output waveform into a pull-up load and a pull-down load and let the simulator vendors decide what the ramp times were. We'd still need pull-up and pull-down V/I tables, the rise-time data can still be there, but the golden waveform could supplant the ramp table if the simulator vendor believes it can do better with the waveform. The data should be in raw form, not percent voltage/percent time. We still have to decide or specify whether the package is included in the waveform. We would also need the complete environment for creating the waveform, but this would enable the models to contain sanity- check/verification within the models. Consensus was that this is a step in the right direction. We will attempt to get this into Version 2.0. AR Stephen (With Jon, Bob R, and Arpad): Collaborate on turning this into a BIRD. Stephen to set up a bridge number for discussion. AR Jon: Share some experimental data with Stephen et. al. to discuss prior to the conference call. 16. BIRD 2, VIH, VIL Thresholds for Inputs Jon needs a compendium of past BIRDs. AR Bob R: Send Jon your rollup of V1.1x so he can check existing passed syntax and repost the BIRD for discussion next meeting. 17. Simulation temperatures (new BIRD?) We need a new BIRD to change the spec. to be explicit that simulation temperatures are only guidelines. Jon suggests a temperature keyword to specify min/max. AR Bob W: Submit an Egg 3.0 to the reflector regarding this issue. 18. Ramp measurement Covered in Egg 2. 19. New Issue: Non-monotonic data Jon and Arpad agreed that the data was a measurement artifact, but given that, it is OK. Simulator vendors can back out the anomaly. It is an artifact that comes from one measurement being derived from on versus tri-stated transistors. When you subtract the curves, there is a small error that results. After discussion, Jon and Arpad were not in agreement. AR Jon: Publish a discussion of this issue. DONE. 20. Wrap-up, Next Meeting Plans Next meeting is 4/29/94. We will concentrate on approving/rejecting all pending BIRDs through BIRD 11. From bob@icx.com Fri Apr 29 11:42:53 1994 Return-Path: Received: from uu4.psi.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26932; Fri, 29 Apr 94 11:42:53 PDT Received: by uu4.psi.com (5.65b/4.0.071791-PSI/PSINet) via UUCP; id AA04641 for ; Fri, 29 Apr 94 14:15:29 -0400 Date: Fri, 29 Apr 94 11:01:37 PDT From: bob@icx.com ( Bob Ross) Received: by icx.com (4.1/3.2.083191-Interconnectix Inc.) id AA24885; Fri, 29 Apr 94 11:01:37 PDT Message-Id: <9404291801.AA24885@icx.com> To: ibis@vhdl.org Subject: BIRD9.3 ("Terminator" change) Hello IBIS members: BIRD9.2 was approved at the April 29, 1994 meeting, but with the change the Model_type "Discrete" be changed to "Terminator". This is done below, and the number is rolled to BIRD9.3 Bob Ross, Interconnectix, Inc. ***************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 9.3 ISSUE TITLE: Terminator Specification REQUESTOR: Bob Ross, Interconnectix, Inc. DATE SUBMITTED: 2 February 1994 DATE REVISED: 21 February 1994, 22 April 1994, 29 April 1994 DATE ACCEPTED BY IBIS OPEN FORUM: 29 April 1994 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Terminators are used in design and can exist as packaged parts. Therefore they are candidates for IBIS modeling. **************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The additional keywords, [Rpower] and [Rgnd], are proposed to represent resistors connected to power (VCC) and ground (GND) or to the voltages based on the voltage reference rules in BIRD3 as they apply to [POWER_clamp] and [GND_clamp]. An AC terminator requiring both [Rac] and [Cac] to GND is proposed. For new keyword usage, a new Model_type parameter within [Model] called "Terminator" is proposed. |============================================================================== | Keywords: [Rgnd], [Rpower], [Rac], [Cac] | Required: Yes, if they exist in the device | Description: The data for these keywords define the resistance values of | Rgnd and Rpower connected to GND and the POWER pins, | respectively. | Usage Rules: For each of these sections the three columns hold the | typical, minimum, and maximum resistance values. The three | entries for R(typ), R(min), and R(max) or C(typ), C(min), | and C(max) must be placed on a single line and must be | separated by at least one white space or tab character. | All three columns are required under these keywords, however | data is only required in the typical column. If minimum | and/or maximum values are not available, the reserved word | "NA" must be used indicating the R(typ) or C(typ) value by | default. | Other Notes: It should be noted that [Rpower] is connected to 'Vcc' and | [Rgnd] is connected to 'GND'. However, [GND_clamp reference] | voltages, if defined, apply to [Rgnd]. [POWER_clamp reference] | voltages, if defined, apply to [Rpower]. | Either or both [Rgnd] and [Rpower] may be defined and may | co-exist with [GND_clamp] and [POWER_clamp] structures. | If an AC terminator is specified, then both [Rac] and [Cac] | are required. | When [Rgnd], [Rpower], or [Rac] and [Cac] are specified, the | Model_type must be Terminator. |------------------------------------------------------------------------------ | variable R(typ) R(min) R(max) | [Rgnd] 330Ohm 300Ohm 360Ohm | Parallel Terminator [Rpower] 220Ohm 200Ohm NA | | [Rac] 30Ohm NA NA | | | | variable C(typ) C(min) C(max) | AC terminator | | [Cac] 50pF NA NA | |============================================================================== The [Model] keyword text has "Terminator" added to the list of Model_types. A modification to the Other Notes section refers to the the new keywords. |==============================================================================| | Keyword: [Model] | | Required: Yes | | Description: Used to define a model, and its attributes. | | Sub-Params: Model_type, Polarity, Enable, Vinl, Vinh, C_comp | |* |* BIRD7.2 and 9.3 modifications |* Usage Rules: Each Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, |* Open_sink, I/O_open_sink, Open_source, I/O_open_source, |* Input_ECL, Output_ECL, I/O_ECL and Terminator model must |* | begin with the keyword [Model]. The model_name must match | | the one that is listed under the [Pin] keyword and must not | | contain more than 20 characters. An .ibs file must contain | | enough [Model] keywords to cover all of the model_names | | specified under the [Pin] keyword, except for those | | model_names which use reserved words (POWER, GND and NC). | | Model_names with reserved words are an exception and | | they do not have to have a corresponding [Model] keyword. | | C_comp is allowed to use "NA" for the min and max values only. | |* |* BIRD9.3 change |* Other Notes: A complete [Model] description normally contains the following |* keywords: [Voltage range], [Pullup], [Pulldown], [GND_clamp], |* [POWER_clamp], [Rgnd], [Rpower], [Rac], [Cac], |* and [Ramp]. However, some models may have only |* a subset these keywords. For example, an input structure |* normally only needs the [Voltage range], [GND_clamp], and |* possibly the [POWER_clamp] keywords. If one or more of |* [Rgnd], [Rpower], [Rac] and [Cac] keywords are used, then |* the Model_type must be Terminator. |* |* BIRD7.2 addition |* Model_types with "open_sink" specify that the output has |* an OPEN side (the [Pullup] keyword is not used or I = 0mA |* for all voltages specified) AND the output SINKS current. |* Model_types with "open_drain" have the identical meaning and |* are retained for backward compatibility. Model_types with |* "open_source" specify that the output has an OPEN side (the |* [Pulldown keyword is not used or I = 0mA for all voltages |* specified) AND the output SOURCES current. Model_types with |* "_ECL" specify that the model represents and ECL type logic |* which follows different conventions for the [Pulldown] keyword. |* | Note that C_comp defines the silicon die capacitance. This | | value should not include the capacitance of the package. | | | |------------------------------------------------------------------------------| [Model] model_name |* |* BIRD7.2 and BIRD9.3 modification Model_type Input, Output, I/O, 3-state, Open_drain, I/O_open_drain, Open_sink, I/O_open_sink, Open_source, I/O_open_source, Input_ECL, Output_ECL, I/O_ECL, Terminator | List one only |* Polarity Non-Inverting, Inverting | List one only, if any Enable Active-High, Active-Low | List one only, if any | Signals RAS, CAS, A(0-64), D(0-128),... | Local list, if desired Vinl = 0.8V | input logic "low" DC voltage, if any Vinh = 2.0V | input logic "high" DC voltage, if any | variable typ min max C_comp 12.0pF 10.0pF 15.0pF |==============================================================================| ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: A set of terminator components is useful to be formatted using IBIS because they are found as packaged components. All of the options can support (typ), (min) and (max) specifications. (1) Parallel Resistor Termination: The additonal elements [Rpower] and [Rgnd] provide terminations to Vcc, Gnd or both. Devices such as the Motorola MCC142233 to MCC142236 Switchable SCSI Passive Bus Terminator series would be modeled with these elements. At least two other techniques could be used in IBIS Version 1.1. The [POWER_clamp] or [GND_clamp] tables could be used (with as few as two data points each) to represent resistors. Another method could be to use R_pkg (or R_pin) with [POWER_clamp] or [GND_clamp] structures configured as a very low impedance. Processing tabular data for these purposes would be less efficient and less obvious than working with resistive elements directly. (2) RC (or AC) Termination: R_pkg (or R_pin) and C_comp can provide RC terminations. This proposal specifies [Rac] connected to [Cac] elements. This will allow packaged RC terminations which include built in clamping diodes to be modeled directly. Diode terminators already can be modeled using IBIS Version 1.1: (3) Diode Termination: Devices such as the TI SN74S1050 thru SN74S1056 Schottky Barrier Diode Bus-Termination Arrays can be modeled using existing [POWER_clamp] and [GND_clamp] structures. The total context model is attached showing the proposed additions. |<-------------TERMINATOR Model--------------->| VOLTAGE RANGE or POWER_CLAMP REF o | POWER_ |---o---| CLAMP | | |--o--| \ | | / | VI | \ RPOWER PACKAGE Keyword | | / Parameters |--o--| | |<----------------->| | | | | PIN o-----o-------o-----o-----/\/\/\--UUUUUU---o--o | |GND_ | | R_PKG L_PKG | | |CLAMP | | | | |--o--| | | | | | | \ | | | | VI | /RGND | | | | | \ \ | | |--o--| / / RAC | | | | \ | | |---o---| / | | | | | C_COMP --- o --- CAC C_PKG --- --- GND or --- --- | GND_CLAMP REF | | | | | |-------------------o----------------------| | o GND |<-------->| Proposed Terminator Keywords ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: This BIRD partially addresses the issue related to BIRD2 regarding Termination Resistor Packs and Termination Diode Packs. It does not address Terminator two-port devices. The adoption of this BIRD would require some text changes in BIRD3 to reference the new keywords. ****************************************************************************** From speters@ichips.intel.com Fri Apr 29 15:15:01 1994 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA28811; Fri, 29 Apr 94 15:15:01 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Fri, 29 Apr 94 15:12:36 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Fri, 29 Apr 94 15:12:17 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Fri, 29 Apr 94 15:12:32 PDT Message-Id: <9404292212.AA01014@xtg801.intel.com> To: ibis@vhdl.org Subject: BIRD 12.1 Date: Fri, 29 Apr 1994 15:12:31 -0700 From: Stephen Peters Hello Fellow IBISians -- Based on the conversation today I've updated Bird 12 to 12.1. The details of the change are listed in the ANALYSIS PATH/DATA section of the bird. I hope I captured everything. Thanks again for everyones input. Best Regards, Stephen Peters Intel Corp. ----------------------- CUT HERE ------------------------------ Buffer Issue Resolution Document (BIRD) BIRD ID#: 12.1 ISSUE TITLE: Non-Linear Driver Waveforms REQUESTER: Stephen Peters, Intel Corp. DATE SUBMITTED: April 25, 1994, Revised April 29, 1994 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ******************************************************************************* ******************************************************************************* STATEMENT OF THE ISSUE: The IBIS specification does not contain enough information to adequately describe the characteristics of a device whose output switching waveform is significantly non-linear. This BIRD proposes a method to describe these non-linear ramp waveforms. ******************************************************************************* STATEMENT OF THE RESOLVED SPECIFICATIONS: Two new keywords are added to the specification, [Rising waveform] and [Falling waveform]. These keywords introduce a table of time vs. voltage points that describe the shape of a waveform. | | Keywords: [Rising waveform], [Falling waveform] | Required: No | Description: Used to describe the shape of the rising and falling edge | waveforms of a driver. | Sub-params: R_fixture, V_fixture, C_fixture, L_fixture, | R_dut, L_dut, C_dut | Usage Rules: Each [Rising waveform] and [Falling waveform] keyword | introduces a table of time vs. voltage points that | describe the shape of an output waveform. These | time/voltage points are taken under the conditions | specified in the R/L/C/V_fixture and R/L/C_dut | sub-parameters. The table itself consists of | one column of time points, then three columns of | voltage points in the standard typ, min and max format. | The four entries must be placed on a single line and | must be separated by at least one white space or tab | character. All four columns are required, however, data | is only required in the typical column. If minimum | or maximum data is not available the reserved word "NA" | is used. The first value in the time column does not | have to be '0'. Time values must increase as | one parses down the table. The waveform table may | contain a maximum of 100 data points. Note that for | backwards compatibility the existing [Ramp] keyword | is still required. | | A waveform table must include the entire waveform; | i.e., the first entry (or entries) in a voltage column | must be the DC voltage of the output before switching | and the last entry (or entries) of the column must be | the final DC value of the output after switching. | | A [Model] specification can contain more than one | rising edge or falling edge waveform table; | however, each new table must begin with the appropriate | keyword and sub-parameter list as shown below. If more | than one rising or falling edge waveform table is | present, then the data in each of the respective tables | must be time correlated. In other words, the rising | (falling) edge data in each of the rising (falling) edge | waveform tables must be entered with respect to a | common reference point on the input stimulus waveform. | | The 'fixture' sub-parameters specifies the loading | conditions under which the waveform is taken. | The R_dut, C_dut, and L_dut are analogous to the the | package parameters R_pkg, C_pkg and L_pkg and are used | if the waveform includes the effects of pin | inductance/capacitance. The diagram below shows the | interconnection of these elements. | | | | | | PACKAGE | TEST FIXTURE | _________ | | | DUT | L_dut R_dut | L_fixture R_fixture | | die |__@@@@@__/\ /\______|__@@@@_______/\ /\_____ V_fixture | | | \/ | | | \/ | |_________| | | | | | | | | C_dut === | === C_fixture | | | | | | | | | gnd | gnd | | Only the R_fixture and C_fixture sub-parameters are | required, the rest of the sub-parameters are optional. | If a sub-parameter is not used its value defaults to | zero. The sub-parameters must appear in the text after | the keyword and before the first row of the waveform | table. | [Rising waveform] R_fixture = 500 V_fixture = 5.0 C_fixture = 50p L_fixture = 2n C_dut = 7p R_dut = 1m L_dut = 1n |Time V(typ) V(min) V(max) 0.0ns 0.3 0.5 NA 0.5ns 0.3 0.5 NA 1.0ns 0.6 0.7 NA 1.5ns 0.9 0.9 NA 2.0ns 1.5 1.3 NA 2.5ns 2.1 1.7 NA 3.0ns 3.0 2.7 NA 3.5ns 3.2 3.0 NA | [Falling waveform] R_fixture = 50 V_fixture = 0 |Time V(typ) V(min) V(max) 10.0ns 3.2 3.0 NA 10.5ns 3.0 2.7 NA 11.0ns 2.1 1.7 NA 11.5ns 1.5 1.3 NA 12.0ns 0.9 0.9 NA 12.5ns 0.6 0.7 NA 13.0ns 0.3 0.5 NA 13.5ns 0.3 0.5 NA ******************************************************************************* ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Currently, the IBIS specification assumes that all devices can be described accurately using a single risetime and falltime parameter. In other words, the switching waveform of the device is a relatively linear ramp. However, devices that shape the output waveform (risetime controlled devices) do not have a linear switching ramp. Trying to model devices of this type using a linear ramp model results in mis-predicting both the time to logic threshold and maximum edge rate. As IBIS is a specification that focuses on the behavior of a device rather than it structure or implementation, it would be ideal if there were a simple set of measurements one could take in order to describe the non-linearity. Obviously, the waveform shape itself is a good place to start. The fundamental assumption here is that the shape of the waveform, combined with the loading conditions, give simulator vendors enough additional information to construct accurate models of non-linear waveform drivers. Ideally, an IBIS model will include waveforms taken under several different loading conditions (R_fixture and V_fixture). By choosing the appropriate loading conditions a modeler can give the simulator vendors enough information to accurately simulate a device. The most straight forward way to describe a waveform shape is with a table of time vs. voltage points. (Note that one could take this table and enter it into a spreadsheet or graphing program and produce a picture of the waveform -- and that is one of the intents of the format.) One remaining issue is the ability to align the starting points of waveforms taken under different loading conditions (i.e. waveforms in two different tables). Jon Powell (Quad Design) has an action item to produce various waveforms and show this is possible. (PLEASE SEE THE NOTE BELOW ON VERSION 12.0 TO 12.1 CHANGES) In addition to providing more complete information to simulator vendors, explicitly describing the waveform allows one to validate a particular simulator's results. By performing a simulation into the specified load(s) and then comparing the results with the waveform(s) as listed in the IBIS file, one can perform anything from a quick sanity check of the data to a detailed analysis between simulators. A 'self-validating' model is a very powerful tool for checking and maintaining model quality. VERSION 12.0 TO 12.1 CHANGES: Based on e-mail suggestions and conversions in the April 29th IBIS open forum the following changes were made: 1. The sub-parameters now have an '=' between the sub-parameter name and value. 2. The maximum number of data points in a waveform table has been specified (100 max). 3. A statement was added that requires that all rising/falling edge data be time correlated. To make this perfectly clear: the data in one rising edge table must be time correlated to the data in any other RISING edge waveform table. Likewise for falling edge data. There is no requirement for time correlation between the data in rising and falling waveform tables. Note also the requirement that the correlation be to a reference point on the input stimulus waveform. This is to prevent a user from time correlating the waveforms to a point on an output waveform -- this defeats the purpose of time correlation. 4. The sub_parameters were expanded and changed from 'load' to 'dut' and 'fixture' to better indicate there proper use. A connection diagram was also added. 5. Cleaned up a few typos in the original version. ******************************************************************************* ANY OTHER BACKGROUND INFORMATION: *******************************************************************************