From Will_Hobbs@ccm2.jf.intel.com  Fri Sep  2 09:54:44 1994
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Date: Fri, 2 Sep 94 09:50:41 PST
From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940902095041_1@ccm.jf.intel.com>
To: ibis@vhdl.org
Subject: IBIS Affiliation with EIA


Text item: Text_1


Fellow IBIS conspirators,

We have taken two straw polls at the last two IBIS Open Forum phone conferences 
and have unanimously agreed to affiliate with the EIA.  The timing of this move 
still needs refinement;  I propose we begin the formal affiliation process 
immediately following IBIS V2.1 ratification in November.

This message is intended to solicit any comments, dissenting opinions or 
reservations, or your aagreement with this move.  If you have an opinion that 
hasn't been expressed, or questions you feel need to be addressed, please reply 
to the reflector.  Thank you.

Regards,

Will Hobbs
Intel Corp.

From bob@icx.com  Fri Sep  2 14:19:34 1994
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Date: Fri, 2 Sep 94 13:48:38 PDT
From: bob@icx.com ( Bob Ross)
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To: ibis@vhdl.org
Subject: Re: DAC session

Paul Franzon and IBIS Committee

Regarding DAC95 participation, I would encourage anyone who wants to 
submit a signal integrity paper to do so.  I cannot because of
time limitations and a 2 week vacation.  One consideration is that if the
session and/or papers are not accepted, perhaps you or someone could
have a similar session at ICCAD95 in November.

While this has not been scheduled yet, I presume that the next IBIS face-
to-face meeting will be in November during the week of ICCAD94, as it was
last year.  This could be an opportunity for individuals to test out ideas
and presentations that could be developed into papers, including those that
have been submitted to DAC95.  A lot of good material was presented in
the Nov93 meeting which eventually found it way into IBIS Version 2.0.  Some
of this could be developed into papers, as well.

Bob Ross
Interconnectix, Inc. 

From 73053.721@compuserve.com  Sat Sep  3 21:53:17 1994
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Date: 04 Sep 94 00:46:57 EDT
From: Paul Munsey <73053.721@compuserve.com>
To: IBIS Reflector <ibis@vhdl.org>
Cc: Ron Neville <75123.3477@compuserve.com>
Subject: Golden Parse data structures
Message-Id: <940904044657_73053.721_GHB35-1@CompuServe.COM>

IBIS Members,

    Included is the data structures that Ron Neville and I are using for building
the 2.0 version of the Golden Parser.  You may notice that the package model
data structure is not included in this.  Ron and I still had not fully decided
exactly how we wanted to represent the matrix's (matrices?), plus I figured that
the following structures will be fun enough to read through all by themselves.

   Note: The following structures are just a cutting and pasting from the various
C header files that we're using.

    Enjoy!

Paul Munsey

---------------------------------------------------------------------------------------------------------------
/**********************************************************************
name:   ibis_chk.h
**********************************************************************/
#define UL unsigned long
#define IBIS_LINE_MAX 80
#define IBIS_PATH_MAX 256 /* debug/todo is not this defined someplace */
/**********************************************************************
   typdefs
**********************************************************************/
typedef enum bool {FALSE, TRUE} BOOL;
typedef enum numstat {NOT_SET, SET, NA} NUMSTAT;
typedef enum ibis_ver {UNKNOWN, VER_1, VER_2} IBIS_VER;



/**********************************************************************
name: ibis.h
desc: Defines the structure for the ibis struct.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct ibis {
   HDR      *pHdr;
               /* this structure holds all the header info */
   CMPNT    *pCmpnts;
               /* this is a ptr to a linked list of structures that 
               hold all the components */
   MDL      *pMdls;
               /* this is a ptr to a linked list of structures that 
               hold all the models */
   PKGMDL   *pPkgmdls;
               /* this is a ptr to a linked list of structures that 
               hold all the package models */
} IBIS;



/**********************************************************************
name:   hdr.h
desc:   Defines the structure for the "header" information in a .ibs 
         file.
**********************************************************************/
#define HDR_VER_LEN      70
#define HDR_REV_LEN      70
#define HDR_DATE_LEN     40 
#define HDR_FILENAME_LEN 12  /* MSDOS max 8 + 1 + 3 */
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct hdr {
   char   sIBIS_Ver[HDR_VER_LEN + 1]; 
   char   sFile_name[HDR_FILENAME_LEN + 1];  
   char   sFile_Rev[HDR_REV_LEN + 1];
   char   sDate[HDR_DATE_LEN + 1];
   char   *sSource; /* ptr to a dynamically maintained array of text.  */
   char   *sNotes;  /* ptr to a dynamically maintained array of text.  */
   char   *sDisclaimer; /* ptr to a dynamically maintained array of text.  */
   char   *sCopyright;  /* ptr to a dynamically maintained array of text.  */
} HDR;



/**********************************************************************
name:   cmpnt.h
desc:   Defines the structure for a single component within a .ibs file.
**********************************************************************/
#define CMPNT_CMPNT_LEN    40
#define CMPNT_MNFCTR_LEN   40
#define CMPNT_PKGMDL_LEN   40
/**********************************************************************
   structure definition
**********************************************************************/
typedef struct cmpnt {
   struct cmpnt *pNext;    /* link list */
   char         sComponent[CMPNT_CMPNT_LEN + 1];
   char         sManufacturer[CMPNT_MNFCTR_LEN + 1];
   PKG          *pPackage;
   PIN          *pPin;           /* linked list of pins */
   char         sPackage_Model[CMPNT_PKGMDL_LEN + 1];
   PINMPG       *pPin_Mapping;   /* linked list of pinmappings */
   DIFPIN       *pDiff_Pin;      /* linked list of diffpins */
} CMPNT; 



/**********************************************************************
name:   mdl.h
desc:   Defines the structure for a single model within a .ibs file.
**********************************************************************/
#define MDL_NAME_LEN     20
/**********************************************************************
   model types
**********************************************************************/
typedef enum model_type {
   NO_TYPE,
   INPUT,
   OUTPUT,
   IO,
   THREE_STATE,
   OPEN_DRAIN,
   IO_OPEN_DRAIN,
   OPEN_SINK,
   IO_OPEN_SINK,
   OPEN_SOURCE,
   IO_OPEN_SOURCE,
   INPUT_ECL,
   OUTPUT_ECL,
   IO_ECL,
   TERMINATOR
} MODEL_TYPE;

/**********************************************************************
   model polarity
**********************************************************************/
typedef enum model_polarity {
   NON_INVERTING,
   INVERTING
} MODEL_POLARITY;

/**********************************************************************
   model enable
**********************************************************************/
typedef enum model_enable {
   ACTIVE_HIGH,
   ACTIVE_LOW
} MODEL_ENABLE;

/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct mdl {
   struct mdl   *pNext;
   char         sModel[MDL_NAME_LEN + 1];
   MODEL_TYPE   *pType;
   MODEL_POLARITY *pPolarity;
   MODEL_ENABLE *pEnable;
   double       *pdVinl;
   double       *pdVinh;
   RNG          *pC_comp;
   double       *pdVmeas;
   double       *pdCref;
   double       *pdRref;
   double       *pdVref;
   RNG          *pTemp_Range;
   RNG          *pVoltage_Range;
   RNG          *pPullup_Ref;
   RNG          *pPulldown_Ref;
   RNG          *pPOWER_Clamp_Ref;
   RNG          *pGND_Clamp_Ref;
   VRNG         *pPulldown;
   VRNG         *pPullup;
   VRNG         *pGND_Clamp;
   VRNG         *pPOWER_Clamp;
   RNG          *pRgnd;
   RNG          *pRpower;
   RNG          *pRac;
   RNG          *pCac;
   RAMP         *pDVDT_r;
   RAMP         *pDVDT_f;
   double       *pdR_load;
   WVFRM        *pRising_Waveform;
   WVFRM        *pFalling_Waveform;
} MDL;



/**********************************************************************
name:   pkg.h
desc:   Defines the structure for the Package.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct pkg {
   RNG   *pR_pkg;
   RNG   *pL_pkg;
   RNG   *pC_pkg;
} PKG;



/**********************************************************************
name:   pin.h
desc:   Defines the structure for the Pin data.
**********************************************************************/
#define PIN_NAME_LEN      5
#define PIN_SIGNAL_LEN   20
#define PIN_MODEL_LEN    20
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct pin {
   struct pin   *pNext;    /* linked list of pins... */
   int          iColumnCount;   /* must be 3 or 6 */
   char         sPin[PIN_NAME_LEN + 1];
   char         sSignal_name[PIN_SIGNAL_LEN + 1];
   char         sModel_name[PIN_MODEL_LEN + 1];
   double       dR_pin;
   BOOL         bR_pinNA;
   double       dL_pin;
   BOOL         bL_pinNA;
   double       dC_pin;
   BOOL         bC_pinNA;
} PIN;



/**********************************************************************
name:   pinmpg.h
desc:   Defines the structure for the pin mapping.
**********************************************************************/
#define PINMPG_NAME_LEN   5
#define PINMPG_REF_LEN   15
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct pinmpg {
   struct pinmpg   *pNext;     /* link list */
   int              iColumnCount;
   char             sPin_Mapping[PINMPG_NAME_LEN + 1];
   char             sPulldown_ref[PINMPG_REF_LEN + 1];
   char             sPullup_ref[PINMPG_REF_LEN + 1];
   char             sGnd_clamp_ref[PINMPG_REF_LEN + 1];
   char             sPower_clamp_ref[PINMPG_REF_LEN + 1];
} PINMPG;



/**********************************************************************
name:   difpin.h
desc:   Defines the structure for the Diff Pin data.
**********************************************************************/
#define DIFPIN_NAME_LEN     5
#define DIFPIN_INVPIN_LEN   5
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct difpin {
   struct difpin   *pNext;     /* linked list of difpins... */
   int             iColumnCount;
   char            sDiff_Pin[DIFPIN_NAME_LEN + 1];
   char            sInv_pin[DIFPIN_INVPIN_LEN + 1];
   VRNG            pVrng;
} DIFPIN;



/**********************************************************************
name:   rng.h
desc:   Defines the structure for the range values.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct rng {
   double   dTyp;
   NUMSTAT  eTypStat;
   double   dMin;
   NUMSTAT  eMinStat;
   double   dMax;
   NUMSTAT  eMaxStat;
} RNG;


/**********************************************************************
name:   vrng.h
desc:   Defines the structure for the v range values.
        Also contains function prototypes for the access methods for 
        that structure.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct vrng {
   double   dVolt;
   BOOL     bVoltNA;
   RNG      *pTdelay;
} VRNG;


/**********************************************************************
name:   ramp.h
desc:   Defines the structure for the ramp.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct ramp {
   double   dTyp_dV;
   double   dTyp_dt;
   double   dMin_dV;
   double   dMin_dt;
   BOOL     bMinNA;
   double   dMax_dV;
   double   dMax_dt;
   BOOL     bMaxNA;
} RAMP;



/**********************************************************************
name:   wvfrm.h
desc:   Defines the structure for the wavefrom values.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct wvfrm {
   struct wvfrm *pNext;       /* link list */
   double       R_fixture;
   double       V_fixture;
   double       C_fixture;
   double       L_fixture;
   double       R_dut;
   double       L_dut;
   double       C_dut;
   TRNG         *pTrng;
} WVFRM;



/**********************************************************************
name:   trng.h
desc:   Defines the structure for the time range values.
**********************************************************************/
/**********************************************************************
   structure definitions
**********************************************************************/
typedef struct trng {
   struct trng *pNext;     /* link list */
   double      time;
   RNG         range;         
} TRNG;


From Derrick_Duehren@ccm2.jf.intel.com  Tue Sep  6 11:48:26 1994
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Date: Tue, 6 Sep 94 09:48:20 PST
From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940906094820_1@ccm.hf.intel.com>
To: IBIS@vhdl.org
Subject: 8/26/94 IBIS Open Forum Meeting Minutes 


Text item: Text_1


Date:    Sep. 6, 1994

From:    Will Hobbs (503) 696-4369, fax (503) 696-4210
         Will_Hobbs@ccm2.jf.intel.com
         XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum
         Intel Corporation
         5200 NE Elam Young Pkwy, Hillsboro, Oregon 97124 USA
         and
         Derrick Duehren (503) 696-4299, fax (503) 696-4904
         Derrick_Duehren@ccm.jf.intel.com
         Intel Program Manager

Subject: Minutes from IBIS Open Forum Meeting 8/26/94

To:
AT&T Global Info Systems      Dave Moxley*
Anacad                        Steffen Rochel
Ansoft                        Henri Maramis
Atmel Corporation             Dan Terry
Cadence Design                Sandeep Khanna, C. Kumar*
Cadlab                        Ralf Bruning
Contec                        Maah Sango
Digital Equipment Corp.       Barry Katz
EIA                           Patty Rusher
High Design Technology        Michael Smith, Dr. Ing. Cosso
HyperLynx                     Kellee Crisafulli
IBM                           Jay Diepenbrock, Joseph Flanigan
IBM-Motorola alliance         Lynn Warriner, Hoa Quoc, John Burnett
Integrated Silicon Systems    Eric Bracken
Integrity Engineering         Greg Doyle
Intel Corporation             Stephen Peters*, Don Telian, Will Hobbs*
                              Arpad Muranyi*, Derrick Duehren*,
Interconnectix, Inc.          Bob Ross*, Scott Bloom*
Intergraph                    Ian Dodd, David Wiens
IntuSoft                      Charles Hymowitz
Mentor Graphics               Ravender Goyal
Meta-Software                 Mei Wong, You-Pang Wei, John Sliney
NEC                           Hiroshi Matsumoto
MicroSim                      Arthur Wong
National Semiconductor        Syed Huq*
North Carolina State U.       Steve Lipa, Michael Steer
OptEM Engineering, Inc.       Benny Leveille, Ken Ehn
PC Ware                       Paul Munsey
Quad Design                   Jon Powell*
Quantic Labs                  Mike Ventham
Racal-Redac                   John Berrie
Siemens Nixdorf               Werner Rissiek*, Olaf Rethmeier
Symmetry                      Martin Walker
Synopsys, Logic Modeling G.   Randy Harr
Texas Instruments             Bob Ward*
Thomson-CSF/SCTF              Jean Lebrun
UniCAD Canada Ltd.            Stephen Lum
Zeelan Technology             George Opsahl, Hiro Moriyasu

CC:
Intel Corporation             Randy Wilhelm, Jerry Budelman,
                              Intel IBIS team

In the list above, attendees at the meeting are indicated by *.

Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences 
are listed below:
     Date       Bridge Number    Reservation #
     9/16/94    (415) 904-8944   #809164
     10/7/94    (415) 904-8944   #809164

All meetings are 8:00 AM to 10:00 AM PDT (15:00 to 17:00 UTC).  We try to have 
agendas out 7 days before each open forum and meeting minutes out within 7 
days after.  When you call into the meeting, ask for the IBIS Open Forum 
hosted by Will Hobbs and give the reservation number.

NOTE: "AR" = Action Required.

------------------------------------------------------------------------


Check-in, Intros, Announcements
Bill denBeste introduced himself and reported that he has taken over as 
administrator for the vhdl.org machine (IBIS and DIE), as a contractor in 
place of Randy Harr, who has accepted a position at Stanford U.  Bill can be 
reached at (503) 649-7477, billd@reprise.com 

There were no corrections made to last month's minutes.

Will paid Paul Munsey for his evaluation of the 2.0 changes ($250).

There were no new agenda items.

There is an IBIS mention in the current ASIC and EDA System Design, Pg. 34.


Progress toward enlisting new IC vendors
There was no new public model availability announced.  Jon is working with 
VLSI, they have a program in place to create IBIS models.  Will reported that 
one of Intel's customers reported that a DRAM supplier provided IBIS models 
with their components.  This supplier is not one of the regular forum members.
Bob Ward reported that he has nearly succeeded in working through TI politics, 
IBIS consensus is converging.  Syed reported that he presented IBIS to 
National Semiconductor.  They are now moving toward incorporation of IBIS into 
their release process.

AR Will: Track down the DRAM IBIS vendor, see if they will post the models.


Golden Parser, 2.1
Paul was not present in the meeting, but sent the following update:

  Ron Neville and I are moving forward.  We have most of the data 
  structure figured out, but are still ironing out a few wrinkles.  I, for the 
  most part, just need to package it all together into one file so I can mail 
  it out for those who are interested in looking at it.  At the same time we 
  are also progressing with the coding in the areas that we have well defined. 

  It is proving very beneficial to have 2 people working on this project, 
  sharing ideas, and coming to an understanding of the best methods and design 
  for the parser.  I do think we're behind where we would like to be at this 
  time, but we are still targeting the end of September.  The internal design 
  is changing some from V1.1 to accommodate the requirements and better fit 
  the V2.0 and future enhancements.  - Paul Munsey


Timing the release of 2.1 models
Kumar, Jon, and Bob Ross confirmed that they, as simulator vendors, will be 
ready to support 2.1 models when the 2.1 Golden Parser is ready (November).  
To do so, however, they will need 2.1 models earlier.  They would like early 
copies from model suppliers.

Jon proposed that IC vendors post perturbed 2.1 models as examples to vhdl.org 
/models directory by the end of September.  Intel and National committed to 
provide the examples; TI thinks they can do so, also.

We recognized/acknowledged that 2.1 models can contain lots of data that can 
be used in many creative ways.

The most important version 2.1 features to semiconductor vendors follow:

Intel: multiple rails (various voltage rails), non-linear ramp tables
National: multiple rails, differential I/O
TI: multiple rails, differential I/O, multiple and non-linear ramp tables.


IBIS Librarian
Michael Steer of NCSU can't make Friday meetings during the academic year.  He 
had been unavailable for a few weeks, but is back now.

Old AR Michael: Post procedures for companies to post IBIS files.

Old AR Michael: Propose a longer, more thorough disclaimer statement and send 
it to Derrick Duehren for legal review.


Standards Body Affiliation
Will summarized previous discussions: affiliation is good, it legitimizes IBIS 
(IBM comments), provides legal standing and international exposure.

Bob Ward and Jon Powell added their votes for affiliation with EIA.  

AR Will: Post notice to the reflector of our intent to affiliate  so if anyone 
has a problem with it they can react.

Bill denBeste recommended having an IBIS participant in the DIE meetings.  DIE 
wants to go out for vote on the spec. in October.  We would like to tag along, 
but we will not be ready until probably November.  Bill reported that the DIE 
meeting on 9/13, 9/14 will cover schedule and EIA affiliation.  DIE ARPA 
funding will conclude in Dec. or Jan.  

AR Bill: Post DIE 9/13/14 meeting agenda to the reflector.  [DONE]


Spice-to-IBIS Converter
Bob Ross reported that the V1.1 converter is available on vhdl.org.  It works 
very well if the Spice models work under IBIS ranges.  There are a few 
undocumented glitches.  Some Spice models aren't built to sweep over the IBIS 
range, causing glitches.  S2ibis works well if the Spice model is built to 
handle the extreme ranges.  When the Spice run doesn't converge, S2ibis tells 
the user when and where the non-convergence occurred.  There is a man page, a 
spec., and a readme file with the program, but they don't cover the gotchas.  
There is also a try.me file to use with the S2ibis program.  Will suggested a 
public comments file for people to contribute to.  The forum decided to post 
experiences to the reflector and copy Michael Steer at NCSU 
(mbs@eos.ncsu.edu).

AR All:  Try out the converter and post comments to the reflector.  If nothing 
else, please send email to Michael.  He can use it when seeking additional 
ARPA funding.


2.0 BNF
Bob Ross would appreciate any comments on the BNF.  Bob Ward will post a 
response as soon as he has reviewed it.  Bob Ross believes that we should have 
a very robust 2.0 BNF available.


1995 Design Automation Conference
Kumar talked to Paul about DAC'95.  We should submit as many papers as 
possible.  It should describe the design process and how IBIS is used.  Kumar 
and Werner are planning to submit papers.  We may need to submit 20 papers to 
have 5 accepted to qualify for a slot.   

AR Jon: Start a discussion on the reflector on this subject.  [DONE.  We only 
need 3 or 4 well-written papers]


BIRD 17, Number of Data Points
The hundred-point limit debate continues.  Arpad put the 100 point limit in 
originally somewhat arbitrarily.  Will is inclined to kill the BIRD,  Jon 
wants no limit due to customer input, though he thinks 50 is enough.  Arpad 
feels that 151 would be a better choice than 101 to cover -5 to +10 in .1 volt 
increments.  Consensus was reached to kill the BIRD.

Vote taken:  BIRD 17 unanimously NOT approved.


BIRD 19, V_fixture sub-keyword
Concern over rising and falling waveform timing with a shifting power supply.  
Bob proposes this BIRD for inclusion in the 2.1 IBIS spec.

Vote taken:  BIRD 19.1 unanimously approved for inclusion in 2.1.


Voltage range "span"
"Span" in the spec. is inclusive and allows voltages to go beyond the range.  
Arpad can send a test case to Jon if he would like his code tested.


Wrap-up, Next Meeting Plans
Our next meeting is 9/16/94.

==============================================================================
                                      NOTES
If you know of someone new who wants to join the e-mail reflector 
(ibis@vhdl.org), send e-mail to ibis-request@vhdl.org.

Check the pub/ibis directory on vhdl.org for more information on previous 
discussions and results.  You can get on via ftp anonymous, "guest" login from 
telnet or dial-in (408-945-4170), or send an email request to the automatic 
archive server, archive@vhdl.org.
==============================================================================




From bob@icx.com  Tue Sep  6 22:29:21 1994
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Date: Tue, 6 Sep 94 22:03:02 PDT
From: bob@icx.com ( Bob Ross)
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To: ibis@vhdl.org
Subject: Update on Version 2.0 BNF

Steffen Rochel and Ibis Committee

Thanks for doing a major extension on the IBIS BNF for Version 2.0.  It takes
a lot of detailed effort to work on this.  One open question is, does there
exist an ISO or ANSI preferred BNF style?

I have attempted a thorough pass through the BNF.  Probably more review is needed
for better accuracy.  My changes are indicated by a comment above using
specific comment format:

     "//***  .....  "

Some minor spelling corrections are not noted.

Several overall comments:

(1) For certain groups of keywords, the order of occurance is not fixed.
I did not make any changes or notes where I detected such situations.
However, I did provide the sub-parameter ordering combinations for the sub-
parameters r_pin, l_pin, and c_pin since this is the only exception to a fixed
keyword-line sub-parameter ordering.

(2) At this time the sub-parameters are case sensitive.  I did not attempt
to make changes in this area.  This could be a IBIS issue to relax Version
2.1 over Version 1.1.  Reserved words 'power', 'gnd', 'na', 'nc' are not
case sensitive.  Units, e.g, 'm' are case sensitive.  So some portions of
the BNF may have to be changed for clarity.  Without any case sensitivity
restrictions, the BNF here will except IBIS_CHK compliant syntax along with
non-compliant case change variations.  Other than units and file name
conventions, no portion of IBIS really needs the case restriction.

(3) The 80 character line length limit is assumed using strings of limited
length and reals.  However, a sequence of reals may extend over several lines
in the "full_matrix" package model.  Stings of unlimited length may extend to
subsequent lines, and their termination is demarked by any subsequent keyword.


Bob Ross
Interconnectix, Inc.

//*** Changes in "keywords ... and added next line:

// Remarks
// comments starts with "//"
// keywords are enclosed by '[' '...' ']'.  An underbar "_" may be substituted
//     for any internal single space and a single space may be substituted for
//     an internal underbar.  No space may exist between the '[' or ']' and
//     the internal keyword.
// defined characters and verbatium strings are enclosed by '...'
// a set is specified by { }, options are enclosed by [ ... ]
// "|" defines an alternative


ibisfile ::= ibisfileheader sections '[' 'end' ']'

packagefile ::= packagefileheader packagedefinitionsections '[' 'end' ']'

ibisfileheader ::= ibisversion ibisfilename fileversion fileheaderitems

packagefileheader ::= ibisversion packagefilename fileversion fileheaderitems

fileheaderitems ::= [ commentchar ] [ date ] [ source ] [ notes ] [ disclaimer ]
		    [ copyright ]

ibisversion ::= '[' 'ibis ver' ']' string

commentchar ::= '[' 'comment char' ']' commentstring

commentstring ::= comment_character '_char'

//*** Some comment characters used "\" so I changed the list and
//*** put the permitted characters in ASCII order within ' '.

comment_character ::= '!' | '"' | '#' | '$' | '%' | '&' | ''' | '(' |
		      ')' | '*' | ',' | ':' | ';' | '<' | '>' | '?' |
		      '@' | '\' | '^' | '`' | '{' | '|' | '}' | '~' 

ibisfilename ::= '[' 'file name' ']' ibisfilenamestring

ibisfilenamestring ::= string8 '.ibs'

packagefilename ::= '[' 'file name' ']' packagefilenamestring

packagefilenamestring ::= string8 '.pkg'

fileversion ::= '[' 'file rev' ']' string

date ::= '[' 'date' ']' string40                             

//*** The following four keywords do not have a string length limitation.
//*** Even copyright can extend to several lines.

source ::= '[' 'source' ']' string                        

notes ::= '[' 'notes' ']' string                        

disclaimer ::= '[' 'disclaimer' ']'  string

copyright ::= '[' 'copyright' ']' string

sections ::= componentdefinitionsection [ modeldefinitionsections ]
	     [ packagedefinitionsection ]

modeldefinitionsections ::= { modeldefinitionsection }

packagedefinitionsections ::= { packagedefinitionsection }

componentdefinitionsection ::= component manufacturer package pin 
                               [ package_model ] [ pin_mapping ] 
                               [ diff_pin ]

component ::= '[' 'component' ']' string40

manufacturer ::= '[' 'manufacturer' ']' string40

package ::= '[' 'package' ']' package_rlc

package_rlc ::=  'r_pkg' typ_min_max 
		 'l_pkg' typ_min_max 
		 'c_pkg' typ_min_max

typ_min_max ::= real real_na real_na

real_na ::=  real | 'na' 

real_na9 ::= real9 | 'na'

//*** This was unclear, so I made a change here

 //pin_with_package_info
pin ::=   pin_wpi	
	| pin_data

//*** Sub-parameter order choices added

pin_wpi ::= pin_header rlc_pin_heading pin_entry_set_wpi

rlc_pin_heading ::= 'r_pin' 'l_pin' 'c_pin' |
                    'r_pin' 'c_pin' 'l_pin' |
                    'l_pin' 'c_pin' 'r_pin' |
                    'l_pin' 'r_pin' 'c_pin' |
                    'c_pin' 'r_pin' 'l_pin' |
                    'c_pin' 'l_pin' 'r_pin' 

pin_data ::= pin_header pin_entry_set

pin_header ::= '[' 'pin' ']' 'signal_name' 'model_name' 

pin_entry_set_wpi ::= pin_entry_wpi { pin_entry_wpi }

pin_entry_set ::= pin_entry { pin_entry }

//*** Even with package information heading, the last 3 columns are
//*** optional for any line.  Thus the "[" and "]".

pin_entry_wpi ::= pin_entry [ real_na9 real_na9 real_na9 ]

//*** model_identifier is required, so I removed the "[" and "]"

pin_entry ::= pin_identifier signal_identifier model_identifier

pin_identifier ::= string5

signal_identifier ::= string20

model_identifier ::= string20 | 'power' | 'gnd' | 'nc'

package_model ::= '[' 'package model' ']' string40

//*** Last two subparameters are optional and pin_mapping follows similar
//*** syntax to diff_pin.  This whole section has been modified.

pin_mapping ::=   pin_mapping_wr
                | pin_mapping_data

pin_mapping_wr ::= pin_mapping_header clamp_ref_name pin_mapping_data_set_wr

pin_mapping_data ::= pin_mapping_header pin_mapping_value_set

pin_mapping_header ::= '[' 'pin mapping' ']' 'pulldown_ref' 'pullup_ref' 

clamp_ref_name ::= 'gnd_clamp_ref' 'power_clamp_ref'

pin_mapping_value_set ::= pin_mapping_values { pin_mapping_values }

pin_mapping_value_set_wr ::= pin_mapping_values_wr { pin_mapping_values_wr }

pin_mapping_values_wr ::= string5 string15 string15 [ string15 string15 ]

pin_mapping_values ::= string5 string15 string15

diff_pin ::=   diff_pin_wr
	     | diff_pin_data

diff_pin_wr ::= diff_pin_header delay_range_name diff_pin_value_set_wr

diff_pin_data ::= diff_pin_header diff_pin_value_set

diff_pin_header ::= '[' 'diff_pin' ']' 'inv_pin' 'vdiff' 'tdelay_typ' 

delay_range_name ::= 'tdelay_min' 'tdelay_max'

diff_pin_value_set ::= diff_pin_values { diff_pin_values }

diff_pin_value_set_wr ::= diff_pin_values_wr { diff_pin_values_wr }

//*** Last two entries can be optional

diff_pin_values_wr ::= diff_pin_values [ real_na9 real_na9 ]

diff_pin_values ::= string5 string5 real9 real_na9

modeldefinitionsection ::= '[' 'model' ']' model_name model 

model_name ::= string20

model ::= model_of_type_one | model_of_type_two | model_of_type_terminator

model_of_type_one ::= modeltype_one modelentry_one

model_of_type_two ::= modeltype_two modelentry_two

model_of_type_terminator ::= modeltype_terminator modelentry_terminator

modeltype_one ::= 'model_type' modeltype_one_identifier

modeltype_one_identifier ::= 'input' | 'i/o' | 'i/o_open_drain' |
                             'i/o_open_sink' | 'i/o_open_source' |
                             'input_ecl' | 'i/o_ecl'

modeltype_two ::= 'model_type' modeltype_two_identifier

modeltype_two_identifier ::= '3-state' | 'open_sink' | 'open_drain' |
                             'open_source' | 'output' | 'output_ecl' 

modeltype_terminator ::= 'model_type' 'terminator'

modelentry_one ::= c_comp vinl vinh modelentry

modelentry_two ::= c_comp modelentry

modelentry_terminator ::= c_comp modelentry

modelentry ::=  [ polarity ] [ enable ] [ vmeas ] [ cref ] [ rref ] [ vref ]
		[ temperature_range ] [ model_range ] [ pulldown ] [ pullup ]
		[ gndclamp ] [ powerclamp ] [ rpower ] [ rgnd ] [ ramp ] 
		[ rac ] [ cac ] [ waveformtable ]

//*** Model_refs and voltage_range requirement clarification below:

model_range ::= voltage_range | 
                all_model_refs |
                voltage_range model_refs

all_model_refs ::= pullup_reference pulldown_reference gnd_clamp_reference
              	   power_clamp_reference

model_refs ::= [ pullup_reference ] [ pulldown_reference ] [ gnd_clamp_reference ]
	       [ power_clamp_reference ]

c_comp ::= 'c_comp' typ_min_max

polarity ::= 'polarity' [ 'non-inverting' | 'inverting' ]

enable ::= 'enable'  [ 'active-high' | 'active-low' ]

vinl ::= 'vinl' '=' voltage_spec

vinh ::= 'vinh' '=' voltage_spec

vmeas ::= 'vmeas' '=' voltage_spec

cref ::= 'cref' '=' capacitance_spec

rref ::= 'rref' '=' resistance_spec

vref ::= 'vref' '=' voltage_spec

voltage_spec ::= real

capacitance_spec ::= real

resistance_spec ::= real 

temperature_range ::= '[' 'temperature range' ']' typ_min_max

voltage_range ::= '[' 'voltage range' ']' typ_min_max

pullup_reference ::= '[' 'pullup reference' ']' typ_min_max

pulldown_reference ::= '[' 'pulldown reference' ']' typ_min_max

power_clamp_reference ::= '[' 'power clamp reference' ']' typ_min_max

gnd_clamp_reference ::= '[' 'gnd clamp reference' ']' typ_min_max

pulldown ::= '[' 'pulldown' ']' videfinitions

pullup ::= '[' 'pullup' ']' videfinitions

gndclamp ::= '[' 'gnd_clamp' ']' videfinitions

powerclamp ::= '[' 'power_clamp' ']' videfinitions

rpower ::= '[' 'rpower' ']' typ_min_max

rgnd ::= '[' 'rgnd' ']' typ_min_max

videfinitions ::= videfinition { videfinition }

videfinition ::=  real typ_min_max 

//*** Both dvdtr and dvdtf are required

ramp ::= '[' 'ramp' ']'  dvdtr dvdtf  [ r_load ]

dvdtr ::= 'dv/dt_r' typ_min_max_rate

dvdtf ::= 'dv/dt_r' typ_min_max_rate

r_load ::= 'r_load' '=' real 

typ_min_max_rate ::= rate [ rate | 'na' ] [ rate | 'na' ]

rac ::= '[' 'rac' ']' typ_min_max

cac ::= '[' 'cac' ']' typ_min_max

waveformtable ::= { waveform_data }

waveform_data ::= '[' 'rising waveform' | 'falling waveform' ']' 
		  waveform_header waveform_table

waveform_header ::= r_fixture v_fixture [ c_fixture ] [ l_fixture ] [ r_dut ] 
                    [ l_dut ] [ c_dut ]

r_fixture ::= 'r_fixture' '=' real

v_fixture ::= 'v_fixture' '=' real

c_fixture ::= 'c_fixture' '=' real

l_fixture ::= 'l_fixture' '=' real

r_dut ::= 'r_dut' '=' real

l_dut ::= 'l_dut' '=' real

c_dut ::= 'c_dut' '=' real

waveform_table ::= { waveform_point }

waveform_point ::= time_point typ_min_max

time_point ::= real

rate ::= real '/' real

packagedefinitionsection ::= definepackage package_header package_description 
			     endpackage

definepackage ::= '[' 'define package model' ']' string40

//*** Insert "number_pins" and "pin_numbers" definition corrected"

package_header ::= manufacturer oem description number_pins pin_numbers pin_names 

oem ::= '[' 'oem' ']' string40

description ::= '[' 'description' ']' string60

//*** Correction here and define "pin_numbers"

number_pins ::= '[' 'number of pins' ']' pos_integer

pin_numbers ::= '[' 'pin numbers' ']' pin_names

pin_names ::= pin_name { pin_name }

pin_name ::= string5

package_description ::= '[' 'model data' ']' model_body '[' 'end model data' ']'

model_body ::= inductance_matrix capacitance_matrix [ resistance_matrix ]

inductance_matrix ::= '[' 'inductance matrix' ']' matrix

capacitance_matrix ::= '[' 'capacitance matrix' ']' matrix

resistance_matrix ::= '[' 'resistance matrix' ']' matrix

matrix ::= full_matrix | banded_matrix | sparse_matrix

full_matrix ::= 'full matrix' matrix_line { matrix_line }

//*** Refinded matrix_line definitions for banded and sparce matricies and 
//*** broke out "row".  Corrected bandwidth spelling.

banded_matrix ::= 'banded matrix' bandwidth banded_matrix_line 
                  { banded_matrix_line }

sparse_matrix ::= 'sparse matrix' sparce_matrix_line 
                  { sparce_matrix_line }

bandwidth ::= '[' 'bandwidth' ']' pos_integer

matrix_line ::= row real { real }

banded_matrix_line ::= row real

sparce_matrix_line ::= row string5 real { string5 real }

row ::= '[' 'row' ']'  string5

endpackage ::= '[' 'end package model' ']'

//*** Made explicit that characters can follow real, certain FIRST characters are
//*** Units

real ::= <real_number> [ anychar { anychar } ]

real9 ::= <real_with_max_9_characters>

//*** Put in extended unit definition using ' '

anychar ::= unit | char

unit ::=  'f' | 'p' | 'n' | 'u' | 'm' | 'k' | 'M" | 'G' | 'T' 

string5 ::= <character_string_with_max_5_characters>

string8 ::= <character_string_with_max_8_characters>

string15 ::= <character_string_with_max_15_characters>

string20 ::= <character_string_with_max_20_characters>

string40 ::= <character_string_with_max_40_characters>

string60 ::= <character_string_with_max_60_characters>

string  ::= <unlimited_character_string>

char ::= <valid_character>

pos_integer ::= <positive_decimal_integer>




From Derrick_Duehren@ccm2.jf.intel.com  Thu Sep  8 00:03:55 1994
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Date: Thu, 8 Sep 94 00:00:03 PST
From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940908000003_1@ccm.hf.intel.com>
To: IBIS@vhdl.org
Subject: IBIS Roster as of 8/94


Text item: Text_1

============================================================================
                  IBIS Open Forum Participation Roster
                  As of 08/02/94 (updated periodically)

                      Submit changes/updates to:
                   Derrick_Duehren@ccm.jf.intel.com
                  (503) 696-4299, Fax (503) 696-4904
============================================================================

Anacad
  Contact:  Steffen Rochel
  Email:    sr@anacad.de
  Phone:    +49 (731) 9545414, FAX: +49 (731) 9545450
  Address:  Helmholtzstr.20
            89081 Ulm
            Germany
  Support:  Anacad can translate IBIS descriptions into models using their
            analog behavioral modeling language HDL-A.  Together with Eldo
            and a VHDL simulator, highly accurate investigations of mixed
            signal designs are then possible.
  Tag-line:

Ansoft Corporation
  Contact:  Henri Maramis
  Email:    maramis@ansoft.com
  Phone:    (412) 261-3200, Fax: (412) 471-9427
  Address:  4 Station Square, Suite 660
            Pittsburgh, PA. 15219
  Support:  The Ansoft Maxwell SI product will support IBIS models/library
            in native format.
  Tag-line: Ansoft is a dedicated provider of electromagnetic field
            simulation software and integrated solutions for signal
            integrity and EMC/EMI.

Atmel Corporation
  Contact:  Dan Terry
  Email:    No internet address -- Pls Fax notices
  Phone:    (408) 436-4346, Fax: (408) 436-4200
  Address:

  Support:
  Tag-line:

Cadence Design Systems, Inc.
  Contact:  C. Kumar
  Email:    cpk@cadence.com
  Phone:    (508) 262-6488, Fax: 508-262-6600
  Address:  270 Billerica Rd,
            Chelmsford,  MA 01824
  Support:  Cadence fully supports IBIS behavior models at the I/O cell and
            package levels.  Cadence's DF/SigNoise product family offers a
            vendor-specific, IBIS compatible signal integrity library of
            over 7000 components.  Cadence also provides a translator
            program enabling the conversion of IBIS 1.1 files to Cadence
            library format.
  Tag-line: Cadence, one of the world's 10 largest software companies, is
            the leading supplier of design automation software/services that
            accelerate and advance the process of designing electronic
            systems.

Contec Microelectronics USA, Inc.
  Contact:  Maah Sango, Clark Cochran
  Email:    maah@contec.com
  Phone:    (408) 434-6767, Fax: (408) 434-6884
  Address:  2188 Bering Drive
            San Jose, CA 95131
  Support:  A Contec product will support IBIS models in native mode.
  Tag-line:

Digital Equipment Corp.
  Contact:  Barry Katz
  Email:    katz@decsim.enet.dec.com
  Phone:    (508) 568-6016, Fax:
  Address:  77 Reed Road, HLO2-2/H13
            Hudson, MA 01749
  Support:  Digital will generate IBIS models for its own chip products,
            including the line of ALPHA AXP microprocessors, as needed, and
             support IBIS models in in-house simulation tools.
  Tag-line: Digital, maker of the world's fastest microprocessor, is also a
            leading developer of computer systems, and networking and
            communication products, including PCI.

Hewlett-Packard/HP EEsof Division
  Contact:  Karl Kachigan
  Email:    karlk@sr.hp.com
  Phone:    (707) 577-3949,  Fax: (707) 577-5260
  Address:  1400 Fountaingrove Parkway
            Santa Rosa, CA 94503
  Support:  none at this time
  Tag-line:
Derrick, you asked about my division within HP.  Here is a short summary for 
the both of you.  HP EEsof Division was formed in May 1994 as a byproduct of 
the merging of two high frequency analog design companies -- HP's High 
Frequency Design Software group based in Santa Rosa, Calif., and EEsof High 
Frequency Design Software based in Westlake Village, Calif. HP acquired EEsof 
in Oct. 1993, and we are consolidating our products, etc., to have a unifed 
high frequency analog CAE product line.  HP EEsof division is physically 
located in the two sites today and will be for the future.
Our strengths are high frequency models and analog simulators that truly 
account for physical effects in layout.  Traditionally used by RF and 
microwave designers, many doing high speed digital design have used our tools 
to simulate the analog performance of interconnects, packages, etc.

Our interest is in tracking industry standards groups like IBIS, to see how 
our products may use this technology in the future.

High Design Technology
  Contact:  Michael Smith
  Email:
  Phone:
  Address:

  Support:
  Tag-line:

HyperLynx
  Contact:  Kellee Crisafulli
  Email:    71436.1314@compuserve.com
  Phone:    (206) 869-2320, Fax: (206) 881-1008
  Address:  P.O. Box 3578
            Redmond, WA 98073-3578
  Support:  The LineSim simulator, an interactive analysis tool, reads IBIS
            files as part of its native library support.  The BoardSim
            simulator (available in July 1994) is an analysis tool that
            reads geometric data directly from PCB layout databases; it also
            natively supports IBIS files.

            LineSim and BoardSim both ship with a set of IBIS libraries;
            additional model libraries are available free of charge to
            customers on HyperLynx's BBS.
  Tag line: HyperLynx, Inc. is the industry's leading supplier of
            affordable, accurate, PC-based signal-integrity software.

IBM Corp. (unofficially)
  Contact:  Joseph C. (Jay) Diepenbrock
  Email:    jayd@ralvm29.vnet.ibm.com
  Phone:    (919) 543-8804
  Address:  IBM Network Hdwe. Div.
            Transceiver Technology Dev't, D63/061
            P. O. Box 12195
            Research Triangle Park, NC 27709
  Support:  No formal declaration of support.
  Tag-line:

IBM-Motorola (PowerPC)
  Contact:  Lynn Warriner, Hoa Quoc
  Email:
  Phone:
  Address:

  Support:
  Tag-line:

Integrity Engineering, Inc.
  Contact:  Greg Doyle
  Email:    gdoyle@intgrty.mn.org
  Phone:    (612) 636-6913, Fax: (612) 631-2241
  Address:  1306 W. Country Rd. F, Suite 100
            St. Paul, MN 55112
  Support:  The Integrity Simulators and Parasitic Extractor tools, SImnet,
            SImnet X, and Autospice are shipped with an IBIS2IEI translation
            program that enables any IBIS file to be directly converted for
            use with the simulator or SPICE extractor.

            The next revisions of IEI programs, slated for delivery 2Q '94,
            will support IBIS models in native mode.  A utility will be
            provided to read, edit, and view IBIS files directly.
  Tag-line:

Intel Corporation
  Contact:  Will Hobbs
  Email:    Will_Hobbs@ccm2.jf.intel.com
  Phone:    (503) 696-4369, Fax: (503) 696-4210
  Address:  5200 NE Elam Young Pkwy, JF1-57
            Hillsboro, OR 97124
  Support:  Intel provides IBIS models for some of its components.  For a
            list of supported components, send the following message to
            archive@vhdl.org:
            path <your return email path>
            send pub/ibis/models/intel readme   index /pub/ibis/models/intel
  Tag-line: Intel, the world's largest chip maker, is also a leading
            manufacturer of personal computer networking and communications
            products.

Interconnectix, Inc.
  Contact:  Bob Ross
  Email:    bob@icx.com
  Phone:    (503) 684-6641, Fax: (503) 639-3469
  Address:  10220 S.W. Nimbus Ave., K4
            Portland, Oregon 97223
  Support:  Interconnectix product will be able to read IBIS Version 1.1
            models directly (NATIVE MODE).  The product will be able to read
            a text file composed of a library of IBIS models.
  Tag-line:


Intergraph Corp.
Feel free to include our name in the EDN article.  Rob Kelley
  Contact:  Ian Dodd, David Wiens
  Email:    idodd@ingr.com, dwiens@ingr.com
  Phone:    (303) 581-2300
  Address:  6101 Lookout Road, Suite A
            Boulder, CO 80301
  Support:  Intergraph Electronics fully supports the activities of the IBIS
            open forum and as such, is ensuring that all signal integrity
            development is aligned so that our customers will be able to
            take advantage of IBIS as the standard stabilizes.
  Tag-line: Intergraph Corporation, a Fortune 500 company, is the world's
            largest independent NT development site and the world's largest
            company dedicated to supplying interactive computer graphics
            systems.

IntuSoft
  Contact:  Charles Hymowitz
  Email:
  Phone:    (303) 833-0710
  Address:

  Support:  IntuSoft takes a customer's netlist or model and translates it
            into a Spice model, free of charge.  IntuSoft has the Golden
            Parser source but hasn't, as of yet, automated the process.
            IntuSoft is waiting until there are more IBIS models available.
  Tag-line:

Mentor Graphics Corp.
  Contact:  Ravender Goyal
  Email:    Ravender_Goyal@mentororg.com
  Phone:
  Address:  8005 SW Boeckman Rd.
            Wilsonville, OR 97070-7777
  Support:  Mentor supports IBIS by using Quad Design and Intel IBIS models.
  Tag-line:

Meta-Software
  Contact:  John Sliney,       Mei Wong
  Email:    johns@metasw.com,  mei@metasw.com
  Phone:    (408) 369-5446,    (408) 371-5100
  Address:  1300 White Oaks Rd.
            Campbell, CA 95008
  Support:
  Tag-line:

MicroSim Corp.
  Contact:  Arthur Wong
  Email:
  Phone:    (714) 770-3022, FAX: (714) 455-0554
  Address:  20 Fairbanks
            Irvine, CA 92718
  Support:  MicroSim can automatically generate PSpice models for vendors
            who provide data in a file format conforming to the IBIS Ver 1.1
            specification.  The models can then be simulated with PSpice.
            MicroSim has made IBIS models for Intel's Pentium processor
            82430 PCIset available to customers.
  Tag-line: MicroSim Corp. - The Desktop EDA Company - provides technically
            sophisticated software for schematic entry, simulation,
            programmable logic synthesis, and signal integrity analysis.

National Semiconductor Corp.
  Contact:  Syed Huq
  Email:    huq@rockie.nsc.com
  Phone:    (408) 721-4874, Fax:(408)721-4785
  Address:  2900 Semiconductor Drive
            M/S E-200
            Santa Clara, CA 95052
Support:    The Advanced Systems & Interface Product Group(ASIP) of National
            Semiconductor is willing to create differential IBIS model files
            and provide IBIS model support to customers.
  Tag-line: National Semiconductor provides technologies for moving and
            shaping information.  The company focuses on communications,
            analog, and personal systems markets, and is the fourth largest
            U.S semiconductor merchant.

NEC Corporation
Contact:  Hiroshi Matsumoto
Email:    mat@lsi.tmg.nec.co.jp
Phone:    +81 -44-435-1501(DIR), Fax: +81 -44-435-1887
Address:  Design Sys. Dept., System ASIC Div., NEC Corp.
          1753 Shimonumabe, Nakahara-ku
          Kawasaki Japan 211
Support:  NEC is willing to write some IBIS models and a model generator
          for some of its LSI components.
Tag-line:

North Carolina State University
  Contact:  Michael Steer, Paul Franzon,   Steve Lipa
  Email:    mbs@ncsu.edu   paulf@ncsu.edu  slipa@eos.ncsu.edu
  Phone:    919-515-5191   919-515-7351    919-515-3947
            FAX for all three: 919-515-5523
  Address:  ECE Dept. Box 7911
            NC State Univ.
            Raleigh, NC  27695-7911
  Support:  (as of 2/94) A Spice to IBIS converter is being developed.  A
            measurement based procedure is being developed for extracting
            IBIS models.  A yacc/lex parser for IBIS models is being
            develped.  All software and techniques will be put in the public
            domain.
  Tag-line:

Performance Signal Integrity, Inc.
  Contact:  Eric Bracken
  Email:    bracken@performance.com
  Phone:    (412) 682-7101, Fax: (412) 682-7178
  Address:  4618 Henry St.
            Pittsburgh, PA 15213
  Support:  PSIBoards will accept IBIS V1.1 (ibis_chk compatible) model
            files directly.  The IBIS files can contain any number of
            models or components.  Instances of these models can be declared
            in the input deck, along with interconnections, to describe a
            complete design.
  Tag-line:


Quad Design Technology, Inc.
  Contact:  Jon Powell
  Email:    jonp@qdt.com
  Phone:    (805) 988-8250, Fax: (805) 988-8259
  Address:  1385 Del Norte Rd.
            Camarillo, CA 93010
  Support:  Quad Design has a translation program that translates from IBIS
            format to Quad Design .mod format.  This translator uses the
            Golden Parser code with enhancements to warn of malformed (yet
            legal) models.  The translator supports user input to be able to
            select from the min-typ-max range of IBIS data.  This program
            (IBIS2XTK) is available now and will be generally distributed
            with the XTK 5.2 release (available in Feb. 1994).
  Tag-line: Quad Desgin is a leading supplier of Signal Integrity and Timing
            tools for high speed digital designs.

Quantic Laboratories, Inc.
  Contact:  Mike Ventham, Zhen Mu
  Email:    ventham@quantic.mb.ca, mu@quantic.mb.ca
  Phone:    (204) 942-4000, Fax: (204) 957-1158
  Address:  12th Floor, 191 Lombard Ave
            Winnipeg, Manitoba, R3B 0X1
            Canada
  Support:  Quantic will be providing an IBIS reader (based on the Golden
            Parser) that will read IBIS models and automatically generate
            data files for Phidias (our graphical VI curve device modellor)
            and database files that associate the component definitions with
            the pin models.

            From Phidias, both SPICE models for Greenfield Phyllis (our
            PHYsical Load and Line Simulator) and models for BoardScan,
            (our PC board scanner for signal integrity and crosstalk) can
            be created.

            The release date has not been set yet.  An application note is
            available regarding using IBIS models with Phidias.
  Tag-line:

Racal-Redac Systems Ltd.
  Contact:  John Berrie
  Email:    johnb@redact.co.uk
  Phone:    +44 684 294161, Fax: +44 684 299754
  Address:  Tewkesbury
            Gloucestershire GL20 8QL,
            England
  Support:  Work is in progress to enable use of IBIS models in native
            format for Redac High-Performance Engineering and EMC Adviser
            products.  In addition, integration with Quad Design and Quantic
            products provides the stated level of support provided by these
            companies.
  Tag-line: Racal-Redac is a world leader in design automation, providing
            open, leading technology, standards-based CADCAM solutions.


Siemens Nixdorf
  Contact:  Werner Rissiek, Olaf Rethmeier
  Email:    wr@cadlab.cadlab.de, olaf@cadlab.cadlab.de
  Phone:    ++49-5251-284-155, ++49-5251-284-222, Fax: ++49-5251-284-105
  Address:  Siemens Nixdorf Informationssysteme AG
            Cadlab / Analog System Engineering
            Bahnhofstrasse 32
            D-33102 Paderborn, Germany
  Support:  Siemens Nixdorf uses the simulation program FREACS (Fast
            REflection And Crosstalk Simulator) for signal integrity
            analysis within the EMC-Workbench. Siemens Nixdorf can read IBIS
            Version 1.1 files and translate the IBIS models into FREACS
            models.  Siemens Nixdorf uses an IBIS parser, developed by
            Siemens Nixdorf, and a semi-automatic process for the
            parametrization of the FREACS macromodels.  The translation of
            IBIS to FREACS is available as a service for customers.

            A fully automated process will be developed when there are more
            IBIS models available.

            Additionally, so called 'reference lists' are set-up that are
            used by the interface (XLIN) between the EMC-Workbench and the
            FREACS macromodel library.  These reference lists consist of
            circuit informations in a special language named HINAC
            (Hierachical Naming Convention), where macromodel data is
            assigned to pins of a component using IBIS-informations, as
            well.

            In this way a controlled set-up of a library is possible using
            IBIS-files as basis.

            Detailed information will be available on request.
  Tag-line: Siemens Nixdorf (SNI) is the leading European company for
            information technology.  Based on self experiences of hardware
            and software development, SNI provides the EMC-workbench for
            advanced analysis of EMC and signal integrity.

Symmetry Design Systems, Inc.
  Contact:  Andy Hughes
  Email:    andy@symmetry.com
  Phone:    (415) 949-9600, Fax: (415)-949-0831
  Address:  477 S. San Antonio Rd. #200
            Los Altos, Ca. 94022

  Support:  Symmetry provides IBIS modeling tools and services. Symmetry's
            modeling tool MODPEX can create IBIS models based on measured
            device characteristics or data sheet information. MODPEX can
            translate IBIS models to SPICE descriptions for testing and
            documentation or translate SPICE models to IBIS.

  Tag-line: Symmetry is a dedicated supplier of tools and services for
            creating, testing, and documenting SPICE and IBIS component
            models for electronic system design.


Synopsys Inc. (Logic Modeling Group)
  Contact:  Randy Harr
  Email:    randyh@synopsys.com
  Phone:    (415) 694-1835, Fax (415) 965-8637
  Address:  700 East Middlefield Road
            Mountain View, CA 94043-4033
  Support:  None at this time
  Tag-line:

Texas Instruments
  Contact:  Bob Ward
  Email:    bward@neosoft.com
  Phone:    (713) 274-4146, Fax (713) 274-3911
  Address:  P.O. Box 1443, M/S 631
            Houston, TX 77251
  Support:  TI has a three-pronged attack on IBIS support.  TI is working on
            a scheme to automatically generate IBIS models from TI Spice
            simulations (TI's proprietary Spice dialect), on an automatic
            means to generate C code to be linked in to TI Spice as a User
            Defined Element from an IBIS model, and an automatic means to
            create the Spice equivalent of the IBIS model from the IBIS
            model specification.

            The latter method differs from the second in that it uses
            skeletonized Spice primitive elements in the form of a
            subcircuit, while the second actually generates C code and
            compiles it for dynamic linking.
  Tag-line:

Thomson-CSF/SCTF
  Contact:  Jean Lebrun
  Email:
  Phone:
  Address:

  Support:
  Tag-line:

UniCAD Canada Ltd.
  Contact:  Stephen Lum
  Email:    lum@unicad.com
  Phone:    (613) 596-9091 Ext. 321
  Address:  2745 Iris Street
            Pinecrest Office Park
            Ottawa, Ontario K2C 3V5
  Support:  UniSolve, a concurrent engineering workbench will support
            IBIS v1.1 model files in native mode for signal integrity
            analysis.
Tag-line:

Zeelan Technology, Inc.
  Contact:  Hiro Moriyasu, George Opsahl
  Email:    zeelan@netcom.com
  Phone:    (503) 520-1000
  Address:  10550 SW Allen Blvd.
            Beaverton, OR 97005
  Support:  Zeelan Tech. provides a modeling service that characterize and
            creates models conforming to the IBIS format.  Zeelan Tech.
            MasterModel(TM) models are created from measurements of physical
            devices using a tightly controlled high-frequency fixture and
            modeling system.  These models closely represent actual device
            behaviour when used in simulation.
  Tag-line:

IBIS Roster    Page 1    06/27/94


From steffen@anacad.de  Fri Sep  9 02:55:08 1994
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	by anacad.de (4.1/SMC-5.11)
Date: Fri, 9 Sep 94 11:41:20 +0200
From: *** Steffen Rochel ***  <steffen@anacad.de>
Message-Id: <9409090941.AA13279@anacad.de>
To: ibis@vhdl.org
Subject: BNF for IBIS

Hi Bob,
thanks for checking and correcting the BNF. As far I know, there
exists no standard for the BNF, I used a format which understandable
by one of our internal tools.  Using this, I detected a small mistake, 
pin_mapping_data_set_wr wasused instead of pin_mapping_value_set_wr.
Also I think, some iterations are necessary until we will have a final
BNF and further work is necessary for the solution of the case sensitivity.

Unfortunatly, I'm not able to meet you in Frankfurt at September the 29th,
but I hope I can attend on some meetings in the future.


Regards
Steffen Rochel
Anacad EES


//(1) For certain groups of keywords, the order of occurance is not fixed.
//I did not make any changes or notes where I detected such situations.
//However, I did provide the sub-parameter ordering combinations for the sub-
//parameters r_pin, l_pin, and c_pin since this is the only exception to a fixed
//keyword-line sub-parameter ordering.

//(2) At this time the sub-parameters are case sensitive.  I did not attempt
//to make changes in this area.  This could be a IBIS issue to relax Version
//2.1 over Version 1.1.  Reserved words 'power', 'gnd', 'na', 'nc' are not
//case sensitive.  Units, e.g, 'm' are case sensitive.  So some portions of
//the BNF may have to be changed for clarity.  Without any case sensitivity
//restrictions, the BNF here will except IBIS_CHK compliant syntax along with
//non-compliant case change variations.  Other than units and file name
//conventions, no portion of IBIS really needs the case restriction.

//(3) The 80 character line length limit is assumed using strings of limited
//length and reals.  However, a sequence of reals may extend over several lines
//in the "full_matrix" package model.  Stings of unlimited length may extend to
//subsequent lines, and their termination is demarked by any subsequent keyword.


//*** Changes in "keywords ... and added next line:

// Remarks
// comments starts with "//"
// keywords are enclosed by '[' '...' ']'.  An underbar "_" may be substituted
//     for any internal single space and a single space may be substituted for
//     an internal underbar.  No space may exist between the '[' or ']' and
//     the internal keyword.
// defined characters and verbatium strings are enclosed by '...'
// a set is specified by { }, options are enclosed by [ ... ]
// "|" defines an alternative


ibisfile ::= ibisfileheader sections '[' 'end' ']'

packagefile ::= packagefileheader packagedefinitionsections '[' 'end' ']'

ibisfileheader ::= ibisversion ibisfilename fileversion fileheaderitems

packagefileheader ::= ibisversion packagefilename fileversion fileheaderitems

fileheaderitems ::= [ commentchar ] [ date ] [ source ] [ notes ] [ disclaimer ]
		    [ copyright ]

ibisversion ::= '[' 'ibis ver' ']' string

commentchar ::= '[' 'comment char' ']' commentstring

commentstring ::= comment_character '_char'

//*** Some comment characters used "\" so I changed the list and
//*** put the permitted characters in ASCII order within ' '.

comment_character ::= '!' | '"' | '#' | '$' | '%' | '&' | ''' | '(' |
		      ')' | '*' | ',' | ':' | ';' | '<' | '>' | '?' |
		      '@' | '\' | '^' | '`' | '{' | '|' | '}' | '~' 

ibisfilename ::= '[' 'file name' ']' ibisfilenamestring

ibisfilenamestring ::= string8 '.ibs'

packagefilename ::= '[' 'file name' ']' packagefilenamestring

packagefilenamestring ::= string8 '.pkg'

fileversion ::= '[' 'file rev' ']' string

date ::= '[' 'date' ']' string40                             

//*** The following four keywords do not have a string length limitation.
//*** Even copyright can extend to several lines.

source ::= '[' 'source' ']' string                        

notes ::= '[' 'notes' ']' string                        

disclaimer ::= '[' 'disclaimer' ']'  string

copyright ::= '[' 'copyright' ']' string

sections ::= componentdefinitionsection [ modeldefinitionsections ]
	     [ packagedefinitionsection ]

modeldefinitionsections ::= { modeldefinitionsection }

packagedefinitionsections ::= { packagedefinitionsection }

componentdefinitionsection ::= component manufacturer package pin 
                               [ package_model ] [ pin_mapping ] 
                               [ diff_pin ]

component ::= '[' 'component' ']' string40

manufacturer ::= '[' 'manufacturer' ']' string40

package ::= '[' 'package' ']' package_rlc

package_rlc ::=  'r_pkg' typ_min_max 
		 'l_pkg' typ_min_max 
		 'c_pkg' typ_min_max

typ_min_max ::= real real_na real_na

real_na ::=  real | 'na' 

real_na9 ::= real9 | 'na'

//*** This was unclear, so I made a change here

 //pin_with_package_info
pin ::=   pin_wpi	
	| pin_data

//*** Sub-parameter order choices added

pin_wpi ::= pin_header rlc_pin_heading pin_entry_set_wpi

rlc_pin_heading ::= 'r_pin' 'l_pin' 'c_pin' |
                    'r_pin' 'c_pin' 'l_pin' |
                    'l_pin' 'c_pin' 'r_pin' |
                    'l_pin' 'r_pin' 'c_pin' |
                    'c_pin' 'r_pin' 'l_pin' |
                    'c_pin' 'l_pin' 'r_pin' 

pin_data ::= pin_header pin_entry_set

pin_header ::= '[' 'pin' ']' 'signal_name' 'model_name' 

pin_entry_set_wpi ::= pin_entry_wpi { pin_entry_wpi }

pin_entry_set ::= pin_entry { pin_entry }

//*** Even with package information heading, the last 3 columns are
//*** optional for any line.  Thus the "[" and "]".

pin_entry_wpi ::= pin_entry [ real_na9 real_na9 real_na9 ]

//*** model_identifier is required, so I removed the "[" and "]"

pin_entry ::= pin_identifier signal_identifier model_identifier

pin_identifier ::= string5

signal_identifier ::= string20

model_identifier ::= string20 | 'power' | 'gnd' | 'nc'

package_model ::= '[' 'package model' ']' string40

//*** Last two subparameters are optional and pin_mapping follows similar
//*** syntax to diff_pin.  This whole section has been modified.

pin_mapping ::=   pin_mapping_wr
                | pin_mapping_data

pin_mapping_wr ::= pin_mapping_header clamp_ref_name pin_mapping_value_set_wr

pin_mapping_data ::= pin_mapping_header pin_mapping_value_set

pin_mapping_header ::= '[' 'pin mapping' ']' 'pulldown_ref' 'pullup_ref' 

clamp_ref_name ::= 'gnd_clamp_ref' 'power_clamp_ref'

pin_mapping_value_set ::= pin_mapping_values { pin_mapping_values }

pin_mapping_value_set_wr ::= pin_mapping_values_wr { pin_mapping_values_wr }

pin_mapping_values_wr ::= string5 string15 string15 [ string15 string15 ]

pin_mapping_values ::= string5 string15 string15

diff_pin ::=   diff_pin_wr
	     | diff_pin_data

diff_pin_wr ::= diff_pin_header delay_range_name diff_pin_value_set_wr

diff_pin_data ::= diff_pin_header diff_pin_value_set

diff_pin_header ::= '[' 'diff_pin' ']' 'inv_pin' 'vdiff' 'tdelay_typ' 

delay_range_name ::= 'tdelay_min' 'tdelay_max'

diff_pin_value_set ::= diff_pin_values { diff_pin_values }

diff_pin_value_set_wr ::= diff_pin_values_wr { diff_pin_values_wr }

//*** Last two entries can be optional

diff_pin_values_wr ::= diff_pin_values [ real_na9 real_na9 ]

diff_pin_values ::= string5 string5 real9 real_na9

modeldefinitionsection ::= '[' 'model' ']' model_name model 

model_name ::= string20

model ::= model_of_type_one | model_of_type_two | model_of_type_terminator

model_of_type_one ::= modeltype_one modelentry_one

model_of_type_two ::= modeltype_two modelentry_two

model_of_type_terminator ::= modeltype_terminator modelentry_terminator

modeltype_one ::= 'model_type' modeltype_one_identifier

modeltype_one_identifier ::= 'input' | 'i/o' | 'i/o_open_drain' |
                             'i/o_open_sink' | 'i/o_open_source' |
                             'input_ecl' | 'i/o_ecl'

modeltype_two ::= 'model_type' modeltype_two_identifier

modeltype_two_identifier ::= '3-state' | 'open_sink' | 'open_drain' |
                             'open_source' | 'output' | 'output_ecl' 

modeltype_terminator ::= 'model_type' 'terminator'

modelentry_one ::= c_comp vinl vinh modelentry

modelentry_two ::= c_comp modelentry

modelentry_terminator ::= c_comp modelentry

modelentry ::=  [ polarity ] [ enable ] [ vmeas ] [ cref ] [ rref ] [ vref ]
		[ temperature_range ] [ model_range ] [ pulldown ] [ pullup ]
		[ gndclamp ] [ powerclamp ] [ rpower ] [ rgnd ] [ ramp ] 
		[ rac ] [ cac ] [ waveformtable ]

//*** Model_refs and voltage_range requirement clarification below:

model_range ::= voltage_range | 
                all_model_refs |
                voltage_range model_refs

all_model_refs ::= pullup_reference pulldown_reference gnd_clamp_reference
              	   power_clamp_reference

model_refs ::= [ pullup_reference ] [ pulldown_reference ] [ gnd_clamp_reference ]
	       [ power_clamp_reference ]

c_comp ::= 'c_comp' typ_min_max

polarity ::= 'polarity' [ 'non-inverting' | 'inverting' ]

enable ::= 'enable'  [ 'active-high' | 'active-low' ]

vinl ::= 'vinl' '=' voltage_spec

vinh ::= 'vinh' '=' voltage_spec

vmeas ::= 'vmeas' '=' voltage_spec

cref ::= 'cref' '=' capacitance_spec

rref ::= 'rref' '=' resistance_spec

vref ::= 'vref' '=' voltage_spec

voltage_spec ::= real

capacitance_spec ::= real

resistance_spec ::= real 

temperature_range ::= '[' 'temperature range' ']' typ_min_max

voltage_range ::= '[' 'voltage range' ']' typ_min_max

pullup_reference ::= '[' 'pullup reference' ']' typ_min_max

pulldown_reference ::= '[' 'pulldown reference' ']' typ_min_max

power_clamp_reference ::= '[' 'power clamp reference' ']' typ_min_max

gnd_clamp_reference ::= '[' 'gnd clamp reference' ']' typ_min_max

pulldown ::= '[' 'pulldown' ']' videfinitions

pullup ::= '[' 'pullup' ']' videfinitions

gndclamp ::= '[' 'gnd_clamp' ']' videfinitions

powerclamp ::= '[' 'power_clamp' ']' videfinitions

rpower ::= '[' 'rpower' ']' typ_min_max

rgnd ::= '[' 'rgnd' ']' typ_min_max

videfinitions ::= videfinition { videfinition }

videfinition ::=  real typ_min_max 

//*** Both dvdtr and dvdtf are required

ramp ::= '[' 'ramp' ']'  dvdtr dvdtf  [ r_load ]

dvdtr ::= 'dv/dt_r' typ_min_max_rate

dvdtf ::= 'dv/dt_r' typ_min_max_rate

r_load ::= 'r_load' '=' real 

typ_min_max_rate ::= rate [ rate | 'na' ] [ rate | 'na' ]

rac ::= '[' 'rac' ']' typ_min_max

cac ::= '[' 'cac' ']' typ_min_max

waveformtable ::= { waveform_data }

waveform_data ::= '[' 'rising waveform' | 'falling waveform' ']' 
		  waveform_header waveform_table

waveform_header ::= r_fixture v_fixture [ c_fixture ] [ l_fixture ] [ r_dut ] 
                    [ l_dut ] [ c_dut ]

r_fixture ::= 'r_fixture' '=' real

v_fixture ::= 'v_fixture' '=' real

c_fixture ::= 'c_fixture' '=' real

l_fixture ::= 'l_fixture' '=' real

r_dut ::= 'r_dut' '=' real

l_dut ::= 'l_dut' '=' real

c_dut ::= 'c_dut' '=' real

waveform_table ::= { waveform_point }

waveform_point ::= time_point typ_min_max

time_point ::= real

rate ::= real '/' real

packagedefinitionsection ::= definepackage package_header package_description 
			     endpackage

definepackage ::= '[' 'define package model' ']' string40

//*** Insert "number_pins" and "pin_numbers" definition corrected"

package_header ::= manufacturer oem description number_pins pin_numbers pin_names 

oem ::= '[' 'oem' ']' string40

description ::= '[' 'description' ']' string60

//*** Correction here and define "pin_numbers"

number_pins ::= '[' 'number of pins' ']' pos_integer

pin_numbers ::= '[' 'pin numbers' ']' pin_names

pin_names ::= pin_name { pin_name }

pin_name ::= string5

package_description ::= '[' 'model data' ']' model_body '[' 'end model data' ']'

model_body ::= inductance_matrix capacitance_matrix [ resistance_matrix ]

inductance_matrix ::= '[' 'inductance matrix' ']' matrix

capacitance_matrix ::= '[' 'capacitance matrix' ']' matrix

resistance_matrix ::= '[' 'resistance matrix' ']' matrix

matrix ::= full_matrix | banded_matrix | sparse_matrix

full_matrix ::= 'full matrix' matrix_line { matrix_line }

//*** Refinded matrix_line definitions for banded and sparce matricies and 
//*** broke out "row".  Corrected bandwidth spelling.

banded_matrix ::= 'banded matrix' bandwidth banded_matrix_line 
                  { banded_matrix_line }

sparse_matrix ::= 'sparse matrix' sparce_matrix_line 
                  { sparce_matrix_line }

bandwidth ::= '[' 'bandwidth' ']' pos_integer

matrix_line ::= row real { real }

banded_matrix_line ::= row real

sparce_matrix_line ::= row string5 real { string5 real }

row ::= '[' 'row' ']'  string5

endpackage ::= '[' 'end package model' ']'

//*** Made explicit that characters can follow real, certain FIRST characters are
//*** Units

real ::= <real_number> [ anychar { anychar } ]

real9 ::= <real_with_max_9_characters>

//*** Put in extended unit definition using ' '

anychar ::= unit | char

unit ::=  'f' | 'p' | 'n' | 'u' | 'm' | 'k' | 'M' | 'G' | 'T' 

string5 ::= <character_string_with_max_5_characters>

string8 ::= <character_string_with_max_8_characters>

string15 ::= <character_string_with_max_15_characters>

string20 ::= <character_string_with_max_20_characters>

string40 ::= <character_string_with_max_40_characters>

string60 ::= <character_string_with_max_60_characters>

string  ::= <unlimited_character_string>

char ::= <valid_character>

pos_integer ::= <positive_decimal_integer>





From Will_Hobbs@ccm2.jf.intel.com  Fri Sep  9 13:50:54 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940909134712_4@ccm.jf.intel.com>
To: ibis@vhdl.org
Subject: Special SI issue of IEEE MTT journal

---------------------------- Forwarded with Changes ---------------------------
From: Raymond.Anderson@EBay.Sun.COM at SMTPGATE
Date: 9/9/94 1:10PM
*To: si-list@android.EBay.Sun.COM at SMTPGATE
Subject: Special SI issue of IEEE MTT journal
-------------------------------------------------------------------------------

Text item: 

IBIS clan,

This was posted to the si-list@android.EBay.Sun.Com reflector.  I'm 
cross-posting here FYI.

Will Hobbs
Intel Corp.

In case anyone on the list hasn't noticed, the September 1994 issue 
of the IEEE Transactions on Microwave Theory and Techniques (Part 2) 
is a special issue devoted to Interconnects and Packaging. There are 
about 20 papers, all related to signal integrity issues.

Ray Anderson

raymonda@uranium.ebay.sun.com

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The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

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Subject: Special SI issue of IEEE MTT journal
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From: lfs@Synopsys.COM (Larry Saunders) (by way of lfs@synopsys.com (Larry Saunders))
Subject: Standardization Call for Participation
X-Mailer: <Windows Eudora Version 2.0.2>

        =========================================
        ||       Call For Participation        ||
        ||         DIE and DIET Format         ||
        ||  EIA Standards Committee formation  ||
        =========================================

                  13 September, 1994
                 Synopsys Corporation
                700 E. Middlefield Rd.
               Mt. View, CA. 94043-4033
                     Building C

Just a reminder that you and your interested associates are invited to 
participate in the formation of the DIE Format and the DIET Format EIA 
Standardization Committees. These committees will be convened on Tuesday 
as part the fifth DIE Format workshop to be held on Tuesday, the 13th 
and Wednesday the 14th of September at Synopsys Corporation in Mt.View, 
CA.

Considerable information regarding the DIE Format version 1.0 and the 
DIET Format version 0.7 is available electronically via anonymous FTP 
to vhdl.org or, dial-in using the "guest" account to(415) 335-0110, or 
via electronic mail to archive@vhdl.org.  The DIE and DIET Format 
information is located in the /pub/die directory.

--------------------------------------------------------------------
         Die Information Exchange (DIE) Format
              Orientation and Workshop
               Tuesday Meeting Agenda

Tuesday September 13, 1994 (1:00am to 5:30pm)
Orientation, EIA Standardization, Steering Committee Formation

1:00pm Session begins
    Introductions & Overview

    Overview and History of DIE Format version 1.0
      Issues and Suggestions for DIE Format version 1.1

    The EIA Standardization Process
      The balloting process, schedule, requirements

3:30pm Break with refreshments

    Steering Committee Formation
    Description of Wednesday's working sessions

5:30pm Adjourn


From Derrick_Duehren@ccm2.jf.intel.com  Mon Sep 12 12:08:04 1994
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From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940912120403_1@ccm.hf.intel.com>
To: IBIS@vhdl.org
Cc: Will_Hobbs@ccm2.jf.intel.com
Subject: IBIS 9/16/94 Meeting Agenda


Text item: Text_1


                       IBIS Open Forum Meeting Agenda 
                                for 9/16/94

                          Bridge:         Res:
                         (415) 904-8944   #809164 

 All meetings are 8:00 AM to 10:00 AM PDT (15:00 to 17:00 UTC).  When you call 
 into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give 
 the reservation number.

  8:00 Check-in, Intros, Announcements                           Hobbs
       - Intros of new IBIS participants              
       - Review of previous meeting's minutes         
       - Miscellany/announcements/treasurer's report  
       - Opens for new issues                         
       - Press updates                                
       - New models available                         

  8:20 Progress toward enlisting new IC vendors                  All

       Golden Parser, 2.1                                        Hobbs

       IBIS Librarian                                            Duehren

       Spice-to-IBIS converter                                   Ross

       2.0 BNF                                                   Rochel

  9:00 IBIS General Session (face-to-face)
       - In Nov?
       - At ICDAC?
       - Topics
         o 2.1 Ratification
         o EIA Affiliation

       1995 Design Automation Conference                         Franzon
       (papers are due)

  9:55 Wrap-up, next meeting plans                               Hobbs



From Arpad_Muranyi@ccm.fm.intel.com  Mon Sep 12 14:47:43 1994
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Date: Mon, 12 Sep 94 14:44:02 PST
From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <940912144402_1@ccm.hf.intel.com>
To: ibis@vhdl.org
Subject: s2ibis for PCs


Text item: Text_1

I tried to look at the s2ibis program, but I did not find a PC version.
I remember someone saying that they succeeded compiling it.  Is this true?
If yes, where is it on VHDL.ORG (I mean which directory)?

Arpad

From mbs@eos.ncsu.edu  Thu Sep 15 11:28:17 1994
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From: mbs@eos.ncsu.edu
Message-Id: <9409151824.AA18340@mbs.ece.ncsu.edu>
To: ibis@vhdl.org
Subject: Proposed IBIS librarian protocol
Date: Thu, 15 Sep 94 14:24:32 EDT

Please Comment:

Procedure for Submitting IBIS Models for Inclusion in the IBIS Model Library.


			       DRAFT 
			  September 9, 1994

		    Michael Steer <mbs@ncsu.edu>

Vendors and others are encouraged to submit IBIS models to the IBIS model
library.  The models are maintained by the IBIS librarian who can be reached
via email at ibis_librarian@vhdl.org .

  1.  Before submission models must be readable by the Golden
      Parser with out errors or warning messages being generated.

  2.  A submission should consist of the following:

      a.  A readme file ( named IBIS.RED ) including the following
	  
	  Name of Person Submitting:   XXXXXXXXXXXX
	  Address:     XXXXXXXXXXXXXXXXXXXXXXXXXXXX
	  Affiliation: XXXXXXXXXXXXXXXXXXXXXXXXXXXX
	  E-Mail:      XXXXXXXXXXXXXXX
	  Telephone Number: XXXXXXXXXXXXXXXXXXXXXXX
	  Fax Number:       XXXXXXXXXXXXXXXXXXXXXXX
	  Suggested Top Directory XXXXXXXXXXXXXXXXx
	    Structure for models

      b.  A Model Transfer Agreement (sample below) must be signed and mailed
          to the IBIS librarian see vhdl.org:/pub/IBIS/models/library.faq.

	  The model check-in procedure will not be finalized until
	  this agreement has been received by the IBIS librarian.
          Check with the librarian via email using the address
          ibis-librarian@vhdl.org  (not yet established).

      c.  All files should be
	      gnu tar'ed and uuencoded
	  OR  tar'ed and compressed and uuencoded
	  OR  zip'ed and uuencoded 
	  into a single file before mailing.  Files should be mailed to 
	  the IBIS librarian.   Expect an acknowledgement within two days.

  3.  When models are received:
	 a. The following will be added to each IBIS file:

             [Disclaimer] IBIS Open Forum disclaims all warranties. See
	     disclaim.txt in vhdl.org:/pub/IBIS/models for full disclaimer.

	 b. The IBIS models will be checked with the Golden Parser and if
	    they parse successfully they will be accepted.


  4.   The IBIS models will be treated as confidential until they are
       publically released.  When new models are added an announcement will
       be made.
       
  5.   The Librarian may change from time-to-time and so the
       file vhdl.org:/pub/ibis/models/library.faq
       should be consulted for contact information.  However
       the librarian can always be contacted via email using
       ibis-librarian@vhdl.org  (not yet established).



 ==============================================================================
		                  SAMPLE
		    
		    IBIS Model Transfer Agreement

The under-signed submitter has submitted the following models to
the IBIS library (list model filenames)

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

Hereafter these will be referred to as the "Work".


The submitter represents that the Work can be made publicly available.
Furthermore the submitter represents that the Work does not infringe on
the proprietary rights of others.

The model files will be provided as is except for the addition of the
following statement to each file:

     IBIS Open Forum disclaims all warranties. See disclaim.txt (see sample
     below) in vhdl.org:/pub/IBIS/models for full disclaimer.

If the models were written as a work made for hire in the course of
employment, the Work is owned by the company/employer which must sign this
agreement in the space provided below.


Submitter's Signature and Date _______________________________

Typed or Printed Name          _______________________________

Institution or Company         _____________________________________________



Authorization (if required)    _______________________________

Typed or Printed Name          _______________________________



Please Check
___________

			 ___
  Submitter's Own Work   |  |
			 |__|
			 ___
  Work done for Hire     |  |
			 |__|




 ==============================================================================
		                  SAMPLE
				DISCLAIMER

disclaim.txt


The IBIS Open Forum disclaims all implied warranties, including the implied
warranties of merchantability and fitness for a particular purpose.
The IBIS Open Forum is not liable for any damages incurred by the use of this
software and/or documentation, including direct, indirect, special, incidental,
or consequential damages.  All the files within this directory are provided as
is. The user assumes all responsibility for using these files.



================================================================================


library.faq

Current Librarian:   Michael Steer
e-mail:              mbs@ncsu.edu
facsimile:           (+1)-919-515-3027
Address              Department of Electrical and Computer Engineering
		     Daniels Hall
		     North Carolina State University
		     Raleigh, North Carolina 27695-7911
		     U.S.A.


Responsibilities:    The IBIS librarian maintains the IBIS models
		     stored on vhdl.org in the directory /pub/ibis/models .


================================================================================

OPEN ISSUES

1. The mail address ibis-librarian.org needs to be established.

2. Mail sent to ibis_librarian@vhdl.org should be stored on vhdl.org
   and forwarded to mbs@ncsu.edu .

3. The disclaimers have not been ratified by a lawyer.

4. New models will be announced  to the ibis@vhdl.org maillist.

5. No differentiation will be made between IBIS versions.

6. All IBIS model versions of the same part will be kept in the library.


From bracken@bacon.performance.com  Thu Sep 15 13:13:01 1994
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Message-Id: <199409152012.QAA17107@bacon.performance.com>
To: mbs@eos.ncsu.edu
Cc: ibis@vhdl.org
Subject: Re: Proposed IBIS librarian protocol 
In-Reply-To: Your message of "Thu, 15 Sep 1994 14:24:32 EDT."
             <9409151824.AA18340@mbs.ece.ncsu.edu> 
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Id: <17104.779659938.1@bacon.performance.com>
Date: Thu, 15 Sep 1994 16:12:31 -0400
From: "J. Eric Bracken" <bracken@bacon.performance.com>

>>      c.  All files should be
>>	      gnu tar'ed and uuencoded
>>	  OR  tar'ed and compressed and uuencoded
>>	  OR  zip'ed and uuencoded 
>>	  into a single file before mailing.  Files should be mailed to 

UUENCODE is bad news for some mailers.  Sometimes, as part of its
encoding, it uses blank spaces at the end of a line.  Certain 
mailers will remove the blanks from the end of the line, because
they don't add any information for a HUMAN reading the message...

It makes for serious heartbreaks when it happens, because you have to
edit the file somehow to add the spaces.  Not fun.

There's another up-and-coming standard for transfers of binary
data via e-mail, called MIME (Multi-purpose Internet Mail Extensions, 
RFC 1341), that works a lot better.  To quote from the FAQ:

	One of the best things about MIME is that it's a "four-wheel drive
	protocol", to borrow a description of PhoneNet from Einar Stefferud.
	MIME was carefully designed to survive many of the most bizarre
	variations of SMTP, UUCP, and Procrustean mail transport protocols,
	such as BITNET and MMDF, that like to slice, dice, and stretch the
	headers and bodies of email messages.

At its simplest, the UUENCODE/UUDECODE programs are replaced in MIME by
the "mmencode" program, which is available (in source form) by anonymous 
FTP from thumper.bellcore.com, /pub/nsb/mm2.7.tar.Z.  Runs under both
DOS & UNIX.

This format should probably be made available to IBIS Library users as an 
alternative to UUENCODE.

--Eric

    |      .'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'`_'.       |
    | (*)  |My Opinions are mine and mine alone!!         |  \^/  |
    T_<">_.|~.  .~.  .~.  .~.  .~.  .~.  .~.  .~.  .~.  .~|._(#)_ |
    o\ ^ /\|  ~~   ~~   ~~   ~~   ~~   ~~   ~~   ~~   ~~  |/\`^'/(=)
     /_Y_\ | J. Eric Bracken                              | /_X_\
_____d|_|b_T_____________________bracken@performance.com__T_d|_|b________

From Derrick_Duehren@ccm2.jf.intel.com  Thu Sep 15 19:31:34 1994
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Date: Thu, 15 Sep 94 19:27:02 PST
From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940915192702_1@ccm.jf.intel.com>
To: mbs@eos.ncsu.edu, ibis@vhdl.org
Subject: Re: Proposed IBIS librarian protocol


Text item: 


My responses start with "**".  I also cleaned up the formatting (replaced tabs 
and indentations with spaces, etc.)
- Derrick 
================================================================================
Please Comment:

Procedure for Submitting IBIS Models for Inclusion in the IBIS Model Library.


                                  DRAFT
                            September 9, 1994

                      Michael Steer <mbs@ncsu.edu>

Vendors and others are encouraged to submit IBIS models to the IBIS model 
library.  The models are maintained by the IBIS librarian who can be reached via
email at ibis_librarian@vhdl.org.

1.  Before submission models must be readable by the Golden Parser with out 
    errors or warning messages being generated.

2.  A submission should consist of the following:

    a.  A readme file ( named IBIS.RED ) including the following

** Isn't README.TXT more common?

       Name of Person Submitting:   XXXXXXXXXXXX 
       Address:     XXXXXXXXXXXXXXXXXXXXXXXXXXXX 
       Affiliation: XXXXXXXXXXXXXXXXXXXXXXXXXXXX 
       E-Mail:      XXXXXXXXXXXXXXX
       Telephone Number: XXXXXXXXXXXXXXXXXXXXXXX 
       Fax Number:       XXXXXXXXXXXXXXXXXXXXXXX 
       Suggested Top Directory XXXXXXXXXXXXXXXXx 

** What is considered the "top" directory?  How about "Sugg. directory structure
location:"

         Structure for models

    b.  A Model Transfer Agreement (sample below) must be signed and mailed to 
        the IBIS librarian see vhdl.org:/pub/IBIS/models/library.faq.
** Mike, I'd put your mailing address in this file, rather than point somewhere 
else.  When this data changes, the first task of the new librarian will be to 
update this file.
** Are faxed copies OK?

        The model check-in procedure will not be finalized until this agreement 
        has been received by the IBIS librarian.  Check with the librarian via 
        email using the address ibis-librarian@vhdl.org (not yet established).

    c.  All files should be
            gnu tar'ed and uuencoded
        OR  tar'ed and compressed and uuencoded 
        OR  zip'ed and uuencoded
        into a single file before mailing.  Files should be mailed to the IBIS 
        librarian.  Expect an acknowledgement within two days.
** What about FTPing them to vhdl.org?  Then you don't need to worry about mail 
problems.

3.  When models are received:
    a. The following will be added to each IBIS file:

       [Disclaimer] IBIS Open Forum disclaims all warranties.  See disclaim.txt 
       in vhdl.org:/pub/IBIS/models for full disclaimer.

    b. The IBIS models will be checked with the Golden Parser and if they parse 
       successfully they will be accepted.

4.  The IBIS models will be treated as confidential until they are publically 
    released.  When new models are added, an announcement will be made.

5.  The Librarian may change from time-to-time and so the file 
    vhdl.org:/pub/ibis/models/library.faq should be consulted for contact 
    information.  However the librarian can always be contacted via email using 
    ibis-librarian@vhdl.org.
** What does the .faq suffix stand for?

==============================================================================
                                      SAMPLE

                        IBIS Model Transfer Agreement

The under-signed submitter has submitted the following models to the IBIS 
library (list model filenames)

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

Hereafter these will be referred to as the "Work".

The submitter represents that the Work can be made publicly available. 
Furthermore the submitter represents that the Work does not infringe on the 
proprietary rights of others.

** I know Intel will not indemnify the models, so the above line will not work 
for many companies.

The model files will be provided as is except for the addition of the following 
statement to each file:

IBIS Open Forum disclaims all warranties. See disclaim.txt (see sample below) in
vhdl.org:/pub/IBIS/models for full disclaimer.

If the models were written as a work made for hire in the course of employment, 
the Work is owned by the company/employer which must sign this agreement in the 
space provided below.


Submitter's Signature and Date _______________________________

Typed or Printed Name          _______________________________
** and title

Institution or Company         _______________________________



Authorization (if required)    _______________________________

Typed or Printed Name          _______________________________
** and title



Please Check
___________

                        __
Submitter's Own Work   |  |
                       |__|
                        __
Work done for Hire     |  |
                       |__|



==============================================================================
                                    SAMPLE

                                  DISCLAIMER

disclaim.txt

The IBIS Open Forum disclaims all implied warranties, including the implied 
warranties of merchantability and fitness for a particular purpose.
The IBIS Open Forum is not liable for any damages incurred by the use of this 
software and/or documentation, including direct, indirect, special, incidental, 
or consequential damages.  All the files within this directory are provided as 
is. The user assumes all responsibility for using these files.

================================================================================

library.faq

Current Librarian:   Michael Steer
e-mail:              mbs@ncsu.edu
facsimile:           (+1)-919-515-3027
Address              Department of Electrical and Computer Engineering 
                     Daniels Hall
                     North Carolina State University
                     Raleigh, North Carolina 27695-7911 
                     U.S.A.

Responsibilities:    The IBIS librarian maintains the IBIS models stored on 
                     vhdl.org in the directory /pub/ibis/models .

================================================================================

OPEN ISSUES

1. The mail address ibis-librarian.org needs to be established.

2. Mail sent to ibis_librarian@vhdl.org should be stored on vhdl.org
   and forwarded to mbs@ncsu.edu.

3. The disclaimers have not been ratified by a lawyer.
** They have been submitted to the Intel legal team for review and comment.

4. New models will be announced to the ibis@vhdl.org mail list.

5. No differentiation will be made between IBIS versions.
** What does this mean?

6. All IBIS model versions of the same part will be kept in the library.
** What does this mean?


Text item: External Message Header

The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

Date: Thu, 15 Sep 94 14:24:32 EDT
Subject: Proposed IBIS librarian protocol
To: ibis@vhdl.org
Message-Id: <9409151824.AA18340@mbs.ece.ncsu.edu>
From: mbs@eos.ncsu.edu
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From uunet!qdt.com!jonp@uunet.uu.net  Fri Sep 16 07:47:39 1994
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Date: Fri, 16 Sep 94 06:14:38 PDT
From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell)
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In-Reply-To: Derrick Duehren's message of Thu, 15 Sep 94 19:27:02 PST <940915192702_1@ccm.jf.intel.com>
Subject: Proposed IBIS librarian protocol

I have one question about this general procedure and I will
admit it is a somewhat esoteric one.

Should IBIS make any attempts to verify that released models are
indeed being release from a given company. For Instance, how do we
know that Will Hobbs is indeed representing INTEL in this venture.
He is not a company officer nor (to my knowledge) have we had official 
INTEL correspondence to the IBIS committee. Do we allow anyone who
represents themselves as being from a company to submit models or should
they have some official blessing from their company?

For instance, what if Steven decides he doesn't like Wills model and releases
a new one to replace it.

I am not actually trying to make trouble but rather avoid it by
going and looking for it.


cheers,
jonp

From bracken@bacon.performance.com  Fri Sep 16 09:32:26 1994
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To: ibis@vhdl.org
Subject: Verifying Authenticity of IBIS Models
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Date: Fri, 16 Sep 1994 12:32:10 -0400
From: "J. Eric Bracken" <bracken@bacon.performance.com>

One techy-kind of way to verify the authenticity of IBIS models
is for the creator to include (as a comment) an electronic signature 
in the submitted file.

The basic idea is to run a checksum on the file, encrypt the checksum
using a secret key, and then to append (or prepend) this "signature"
to the file as a comment.

The person who downloads the file uses a verifier program to check 
the signature.  This program will find the signature, decrypt it using
the vendor's public key (which must be widely published) and then compares
the stored checksum with the checksum it computes.  If the checksums
match, it passes; if they don't match, the file is flagged as bogus.

When modern cryptographic techniques are used, it's EXTREMELY
difficult to fake the signature of another person/company.  And with
modern checksumming algorithms it's also very, very hard to create a
bogus file with the same checksum.

As far as administration goes, the signing program would belong to a
select few authorities within semi vendor companies, and would be 
password protected so that only those authorities could run it to put
the imprimatur on the file.  The signature-verification program, and
lists of vendor public keys, could be distributed freely on the 
bboard/FTP sites.

Just a wild idea...

--Eric

From cer@Cadence.COM  Mon Sep 19 05:45:45 1994
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From: cer@cadence.com (Chrisopher E. Reid)
Message-Id: <9409191241.AA05710@oahu>
To: ibis@vhdl.org
Subject: Re: Verifying Authenticity of IBIS Models

I like the idea. How about creating a field in the Ibis
model itself for the public key?

Chris


From bracken@bacon.performance.com  Mon Sep 19 07:29:21 1994
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To: cer@cadence.com (Chrisopher E. Reid)
Cc: ibis@vhdl.org
Subject: Re: Verifying Authenticity of IBIS Models 
In-Reply-To: Your message of "Mon, 19 Sep 1994 08:41:40 EDT."
             <9409191241.AA05710@oahu> 
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Date: Mon, 19 Sep 1994 10:28:35 -0400
From: "J. Eric Bracken" <bracken@bacon.performance.com>

>> From: cer@Cadence.COM (Chrisopher E. Reid)
>> To: ibis@vhdl.org
>> Subject: Re: Verifying Authenticity of IBIS Models

>> I like the idea. How about creating a field in the Ibis
>> model itself for the public key?

>> Chris

The problem there is that a disreputable person might generate a NEW
public/secret key pair, use the secret key to sign the bogus model
file, and then include the matching public key in the file.  The
signature verifier would pass the resulting bogus file...

Hence the need for publicly-readable tables of public keys, which ONLY
trusted authorities can write and update.

--Eric


From Will_Hobbs@ccm2.jf.intel.com  Tue Sep 20 17:19:44 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940920171556_12@ccm.jf.intel.com>
To: ibis@vhdl.org
Subject: CICC (Papers on interconnects and packages)

---------------------------- Forwarded with Changes ---------------------------
From: dileep%contec.COM%contec@netcom.com at SMTPGATE
Date: 9/20/94 12:16PM
*To: si-list@android.EBay.Sun.COM at SMTPGATE
*cc: dileep@contec.COM at SMTPGATE
Subject: CICC (Papers on interconnects and packages)
-------------------------------------------------------------------------------

Text item: 

IBIS-oids,

FYI. Forwarded from the si-list reflector.

Will Hobbs
Intel Corp.


______________________________ Forward Header __________________________________
Subject: CICC (Papers on interconnects and packages)
Author:  dileep%contec.COM%contec@netcom.com at SMTPGATE
Date:    9/20/94 12:16 PM


Custom Integrated Circuits Conference will be held in
Santa Clara Convention Center, Santa Clara, CA from May 1-4, 1995. 
We are trying to put together a session on simulation and modeling 
of IC interconnects and packages. In addition to original work, 
papers can be of tutorial or instructional nature.
The contents should be useful for IC designers and should not have been 
published before. Papers from IC designers are also solicited covering 
their needs in this area.
The papers will have to pass the normal review process.
If you are planning to submit a paper for this session, please let me
know. The papers have to be submitted in a camera-ready form by December 14. 
If you have not received the Call For Papers and need more information
about obtaining author's kit and detailed instructions, please contact: 
Melissa Widerkehr, CICC, 1545 18th Street, NW, Suite 610, Washington, 
DC 20036. Phone (202)-986-2166 Fax (202)-986-1139.
My e-mail address is given below. Thanks. 
dileep@contec.com

Text item: External Message Header

The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

Content-Length: 1000
Cc: dileep@contec.COM
Subject: CICC (Papers on interconnects and packages)
To: si-list@android.EBay.Sun.COM
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From: dileep@contec.COM (Dileep Divekar)
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From huq@rockie.nsc.com  Wed Sep 21 09:55:51 1994
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Date: Wed, 21 Sep 94 09:54:04 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9409211654.AA25604@rockie.nsc.com>
To: ibis@vhdl.org
Subject: ibis in 'Computer Design'
Cc: cjfgsc@tevm2.nsc.com, tdjzsc@tssc.nsc.com

Hi,

There was a brief mention of IBIS in 'Computer Design' Sept 1994 pg 52 in an 
article called 'Signal Integrity concerns slip into mainstream'.

Regards,
Syed huq
National Semiconductor

From Derrick_Duehren@ccm2.jf.intel.com  Thu Sep 22 16:43:04 1994
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From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940922163917_3@ccm.hf.intel.com>
To: IBIS@vhdl.org
Cc: Randy_L_Wilhelm@ccm.fm.intel.com, Jerry_Budelman@ccm2.jf.intel.com
Subject: IBIS 9/16/94 Meeting Minutes


Text item: Text_1


Date:    Sep. 22, 1994

From:    Will Hobbs (503) 696-4369, fax (503) 696-4210
         Will_Hobbs@ccm2.jf.intel.com
         XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum
         Intel Corporation
         5200 NE Elam Young Pkwy, Hillsboro, Oregon 97124 USA
         and
         Derrick Duehren (503) 696-4299, fax (503) 696-4904
         Derrick_Duehren@ccm.jf.intel.com
         Intel Program Manager

Subject: Minutes from IBIS Open Forum Meeting 9/16/94

To:
AT&T Global Info Systems      Dave Moxley
Anacad                        Steffen Rochel
Ansoft                        Henri Maramis
Atmel Corporation             Dan Terry
Cadence Design                Sandeep Khanna, C. Kumar
Cadlab                        Ralf Bruning
Contec                        Maah Sango
Digital Equipment Corp.       Barry Katz*
EIA                           Patty Rusher
High Design Technology        Michael Smith, Dr. Ing. Cosso
HyperLynx                     Kellee Crisafulli*
IBM                           Jay Diepenbrock, Joseph Flanigan
IBM-Motorola alliance         Lynn Warriner, Hoa Quoc, John Burnett
Integrated Silicon Systems    Eric Bracken*
Integrity Engineering         Greg Doyle
Intel Corporation             Stephen Peters*, Don Telian*, Will Hobbs*
                              Arpad Muranyi*, Derrick Duehren*,
Interconnectix, Inc.          Bob Ross*, Scott Bloom*
Intergraph                    Ian Dodd, David Wiens
IntuSoft                      Charles Hymowitz
Mentor Graphics               Ravender Goyal
Meta-Software                 Mei Wong, You-Pang Wei, John Sliney
NEC                           Hiroshi Matsumoto
MicroSim                      Arthur Wong
National Semiconductor        Syed Huq*
North Carolina State U.       Steve Lipa, Michael Steer*
OptEM Engineering, Inc.       Benny Leveille, Ken Ehn
PC Ware                       Paul Munsey*
Quad Design                   Jon Powell*
Quantic Labs                  Mike Ventham
Racal-Redac                   John Berrie
Siemens Nixdorf               Werner Rissiek, Olaf Rethmeier*
Symmetry                      Martin Walker
Synopsys, Logic Modeling G.   Randy Harr
Texas Instruments             Bob Ward*
Thomson-CSF/SCTF              Jean Lebrun
UniCAD Canada Ltd.            Stephen Lum*
Zeelan Technology             George Opsahl, Hiro Moriyasu

CC:
Intel Corporation             Randy Wilhelm, Jerry Budelman,
                              Intel IBIS team

In the list above, attendees at the meeting are indicated by *.

Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences 
are listed below:
     Date       Bridge Number    Reservation #
     10/7/94    (916) 356-9999   394217 (THIS IS A NEW NUMBER!)

All meetings are 8:00 AM to 10:00 AM PDT (15:00 to 17:00 UTC).  We try to have 
agendas out 7 days before each open forum and meeting minutes out within 7 
days after.  When you call into the meeting, ask for the IBIS Open Forum 
hosted by Will Hobbs and give the reservation number.

NOTE: "AR" = Action Required.

------------------------------------------------------------------------


Check-in, Intros, Announcements
There were no new participants.  

There were no corrections made to last month's minutes.
BNF Comment: Bob Ross will post BNF (not Bob Ward)...

Will has received confirmed 2.0 parser payment from HP.  HyperLynx and Quad 
Design said they have sent in their $500 each.

AR Will: Verify above two payments.
AR Derrick: Repost invoice, add beta copies are included in the one-time $500 
fee (a letter of intent is OK for beta copies).

New Agenda Item:  Gate drive in IBIS model macro

Press Updates:  An editor from EDN magazine called Derrick this week to see 
how we were doing on the IBIS article.  Derrick is redoing the examples, then 
it will be sent through Intel MarCom for publishing.  Derrick suggested to the 
editor that they tie the article to the 2.1 announcement this Fall.

Progress toward enlisting new IC vendors:  There was no new public model 
availability announced.  

Kellee relayed a comment from a customer in regards to Intel Pentium(TM) 
processor IBIS models not being available.  Will clarified that Intel has 
Simplified Electrical Models for the parts, as IBIS was not available when the 
PP models were created.  Will is leading a program to convert the SEM format 
data into IBIS format.  

Intel 960 IBIS models are avialable upon customer request to Intel.  Intel 
expects to post them to vhdl.org within the next month, pending final 
validation.

Old AR Will: Track down the DRAM IBIS vendor, see if they will post the 
models.


Golden Parser, 2.0
Paul believes he will have the parser done on time (9/30/94).  Paul will 
distribute both DOS executable and source code by US mail to a mailing list 
provided by Will Hobbs (get your 2.0 license checks/letters of intent in the 
mail! -- address above)

AR Will: Supply distribution mail list to Paul.
AR Bob Ross: Send details of passed BIRD 19, V_fixture sub-keyword to Paul.

Intel (Stephen P.) will have a sample 2.0 model ready by 9/30, possibly 
sooner.  Syed will have some 2.0 models ready in November, possibly sooner.


IBIS Librarian
Michael Steer has submitted a draft librarian protocol to ibis@vhdl.org.  He 
has been checking the /incoming directory and so far nothing relevant has 
shown up.

Michael sent a longer, more thorough disclaimer statement to Derrick for legal 
review, which is in process.

We decided to have all model postings announced on the reflector before they 
are actually posted.  This will give others a chance to object if an 
unauthorized person tries to post a model.


Spice-to-IBIS Converter
Kellee has had difficulty posting converter files to vhdl.org /incoming.  
Kellee to resolve with Michael Steer and Bill denBeste (billd@reprise.com).  

Old AR All:  Try out the converter and post comments to the reflector.  If 
nothing else, please send email to Michael.  He can use it when seeking 
additional ARPA funding.


Gate drive in IBIS model macro
Don Telian asked if simulator vendors can simulate gate-source potential 
changes / gate modulation.

AR Simulator Vendors: Can simulator vendors simulate gate modulation?  Respond 
to the reflector.


2.0 BNF
Bob Ross reported that good progress is being made in polishing the BNF spec.


IBIS General Session (face-to-face)
We will have our next face-to-face meeting the day after ICCAD, Friday 
November 11th in San Jose.  Agenda suggestions:
   o 2.1 Ratification
   o EIA Affiliation

We need to start making arrangements.  Any vollunteers?


1995 Design Automation Conference
No one will be writing papers.  Bob Ross suggested ICCAD `95.


Wrap-up, Next Meeting Plans
Our next meeting is 10/7/94.

==============================================================================
                                      NOTES
If you know of someone new who wants to join the e-mail reflector 
(ibis@vhdl.org), send e-mail to ibis-request@vhdl.org.

Check the pub/ibis directory on vhdl.org for more information on previous 
discussions and results.  You can get on via ftp anonymous, "guest" login from 
telnet or dial-in (408-945-4170), or send an email request to the automatic 
archive server, archive@vhdl.org.
==============================================================================


From paulf@eos.ncsu.edu  Fri Sep 23 06:28:48 1994
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From: paulf@eos.ncsu.edu
Message-Id: <9409231325.AA23476@c11059-364dan.ece.ncsu.edu>
To: ibis@vhdl.org
Subject: DAC papers
Date: Fri, 23 Sep 94 09:25:00 EDT

Sorry, it is difficult for me to `attend' IBIS meetings due
other commitments.

I note in the minutes:

=============
1995 Design Automation Conference
No one will be writing papers.  Bob Ross suggested ICCAD `95.
=============

Thanks for trying to contribute to an SI session at DAC.  I
appreciate your efforts.  Please let me know if you end
up submitting a paper, so I can still try to organize
a session if possible.  Right now, I feel the papers that
are being submitted are scattered too `widely' to make an SI
session (except as a stretch).

Just some comments on ICCAD if I may:
- few designers attend ICCAD.  CAD industry attendance is
  surprisingly poor too.
- the acceptance rate is about the same (and in fact will be
  worse than DAC for more `practical' papers).

I think ICCAD is an excellent technical conference.  However,
depending on your aims for presenting a paper, you might want to
hold out for DAC '96.

Next year, we hope to submit a `IBIS validation' paper somewhere
(`real-model' Spice vs. IBIS vs. measured results).

Regards,

Paul Franzon

From huq@rockie.nsc.com  Fri Sep 23 10:37:11 1994
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Date: Fri, 23 Sep 94 10:35:25 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9409231735.AA05429@rockie.nsc.com>
To: ibis@vhdl.org
Subject: Model for IBIS2.0

Hi,
By the end of next week, I will be able to provide a IBIS2.0 model for parser
verification and for Simulator vendors supporting v2.0 to try out.

Can someone suggest how I can pass this model ?

I will need feedback from any simulator vendor trying out this model. 

Regards,
Syed Huq
National Semiconductor

From Will_Hobbs@ccm2.jf.intel.com  Fri Sep 23 11:09:05 1994
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Date: Fri, 23 Sep 94 11:05:03 PST
From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940923110503_2@ccm.jf.intel.com>
To: huq@rockie.nsc.com, ibis@vhdl.org
Subject: Re: Model for IBIS2.0


Text item: 

Syed,

How big is it?  If it is relatively small, and non-proprietary, post it to the 
reflector.  If it is bigger and non-proprietary, we could put it in a special 
directory on the bbs.  I'd suggest putting into the incoming directory on 
vhdl.org and letting Michael Steer (OK Michael?) handle it.  If it contains 
proprietary info, you should probably work on a request basis from the simulator
vendors.

Will Hobbs
Intel Corp.

Hi,
By the end of next week, I will be able to provide a IBIS2.0 model for parser 
verification and for Simulator vendors supporting v2.0 to try out.

Can someone suggest how I can pass this model ?

I will need feedback from any simulator vendor trying out this model.

Regards,
Syed Huq
National Semiconductor

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***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

Subject: Model for IBIS2.0
To: ibis@vhdl.org
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From: huq@rockie.nsc.com (Syed Huq)
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From fkai@dellgate.us.dell.com  Mon Sep 26 06:54:39 1994
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Date: Mon, 26 Sep 94 08:55 CDT
From: fkai@dellgate.us.dell.com (Francis Kai)
To: "Wright, Richard" <Richard_Wright@ccm.fm.intel.com>, ibis@vhdl.org
Subject: Re: test message

Yes, I do receive your message, Mr. Wright.

Francis Kai
Dell Computer Corporation

From Derrick_Duehren@ccm2.jf.intel.com  Mon Sep 26 09:41:16 1994
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From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
Message-Id: <940926093726_2@ccm.hf.intel.com>
To: IBIS@vhdl.org
Subject: IBIS: How to order the Golden Parser v2.1


Text item: Text_1

 
   NOTE: Beta copies are included in the one-time $500 fee.  A letter of intent 
   is acceptable to receive beta copies.
   ============================================================================
 
   A company may obtain source code for the 2.1 Golden Parser by submitting 
   a request to:
 
   Conference Management Services
   407 Chester Street
   Menlo Park, CA 94025
   415-329-0510
   415-324-3150 (fax)
   cms@cis.stanford.edu
 
   Enclose a check for $500.00 made out to IBIS.  CMS will take care of 
   notifying Randy Harr and/or Will Hobbs who will take care of 
   distributing the source once it is available.
 
   Disclaimer:  The version 2.1 IBIS Golden Parser is currently under 
   development under the direction of the IBIS Open Forum.  There is no 
   guarantee implied in your license fee that the parser will be completed 
   or successful.
 
   - Derrick Duehren
     Intel

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Subject: IBIS: How to order the Golden Parser v2.1
To: IBIS@vhdl.org
Message-Id: <940824183925_2@ccm.hf.intel.com>
From: Derrick Duehren <Derrick_Duehren@ccm2.jf.intel.com>
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From Will_Hobbs@ccm2.jf.intel.com  Mon Sep 26 10:56:45 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940926105256_10@ccm.jf.intel.com>
To: Derrick_Duehren@ccm2.jf.intel.com, IBIS@vhdl.org
Subject: Re: IBIS: How to order the Golden Parser v2.1


Text item: Text_1

   IBIS-ers,
   
   Minor correction:
   
   CMS will notify Will Hobbs.  Randy is no longer handling this 
   responsibility.
   
   NOTE: Beta copies are included in the one-time $500 fee.  A letter of intent 
   is acceptable to receive beta copies. 
   ============================================================================

   A company may obtain source code for the 2.1 Golden Parser by submitting 
   a request to:

   Conference Management Services
   407 Chester Street
   Menlo Park, CA 94025
   415-329-0510
   415-324-3150 (fax)
   cms@cis.stanford.edu

   Enclose a check for $500.00 made out to IBIS.  CMS will take care of 
   notifying [Randy Harr or] Will Hobbs who will take care of 
   distributing the source once it is available.

   Disclaimer:  The version 2.1 IBIS Golden Parser is currently under 
   development under the direction of the IBIS Open Forum.  There is no 
   guarantee implied in your license fee that the parser will be completed 
   or successful.

   - Derrick Duehren
     Intel

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Subject: IBIS: How to order the Golden Parser v2.1
To: IBIS@vhdl.org
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From Ravender_Goyal@pdxml1.mentorg.com  Tue Sep 27 02:53:51 1994
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Date: 27 Sep 1994 02:56:28 -0800
From: "Ravender Goyal" <Ravender_Goyal@pdxml1.mentorg.com>
Subject: Re: ibis in 'Computer Design
To: ibis@vhdl.org, "Syed Huq" <huq@rockie.nsc.com>
Cc: cjfgsc@tevm2.nsc.com, tdjzsc@tssc.nsc.com

        Reply to:   RE>ibis in 'Computer Design'
IBIS WAS MENTIONED IN A PAPER AND SEMINAR THAT I PRESENTAED AT ISHM/
NORDIC IN FINLAND THIS WEEK ATTENDED BY MORE THAN 150 TECHNICAL EXPERTS
FROM NORDIC AND OTHER EUROPEAN COUNTRIES. ALERT! Mr. Hobbs MAY GET
REQUESTS FROM THESE PEOPLE TO BE INCLUDED IN IBIS MAILING LIST & other
related questions. !!!FAMOUS PEOPLE HAVE TOUGH LIFE!!!!!

- ravender
--------------------------------------
Date: 21.09.1994 10:14
To: Ravender Goyal
From: Syed Huq
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9409211654.AA25604@rockie.nsc.com>
To: ibis@vhdl.org
Subject: ibis in 'Computer Design'
Cc: cjfgsc@tevm2.nsc.com, tdjzsc@tssc.nsc.com

Hi,

There was a brief mention of IBIS in 'Computer Design' Sept 1994 pg 52 in
an 
article called 'Signal Integrity concerns slip into mainstream'.

Regards,
Syed huq
National Semiconductor




From fkai@dellgate.us.dell.com  Tue Sep 27 07:08:48 1994
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Date: Tue, 27 Sep 94 09:09 CDT
From: fkai@dellgate.us.dell.com (Francis Kai)
To: "Syed Huq" <huq@rockie.nsc.com>, ibis@vhdl.org,
        "Ravender Goyal" <Ravender_Goyal@pdxml1.mentorg.com>
Cc: cjfgsc@tevm2.nsc.com, tdjzsc@tssc.nsc.com
Subject: Re: ibis in 'Computer Design

Monsieur Goyal,

Could you please fax a copy of your paper to me (ISHM/NORDIC)? My fax number 
is (512) 728-9336. Merci.

Francis Kai
Fax: (512) 728-8349
Dell Computer Corporation

From Will_Hobbs@ccm2.jf.intel.com  Tue Sep 27 09:01:58 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940927085806_3@ccm.jf.intel.com>
To: ibis@vhdl.org
Subject: 1 week delay on Beta Parser release, and a reminder


Text item: Text_1

Greetings, IBISians,

Paul Munsey has informed me that he and Ron (the two engineers we have 
contracted to write version 2.0 of the IBIS Golden Parser) are making 
excellent progress, but require an additional week to merge their efforts and 
ensure a quality release.  Therefore, the Beta version will be delayed until 
October 7, and reviewers should expect to receive it in the following week.

Also, a reminder:  To date, the IBIS fund has only received payment from two 
companies. Intel's should go out this week.  We are counting on at least 10 
companies to license the V2.0 of the parser, to cover half the cost of Paul's 
and Ron's work.  The other half will draw on reserves in the IBIS account.  
Please submit the fee soon.  I would like to reach closure on this.

The Beta copy will only go out to those who have either: 1) paid the license 
fee, or 2) sent me a letter of commitment saying they would be submitting the 
fee shortly (please indicate when).

Regards,

Will Hobbs
Intel Corp.


From jonp@qdt.com  Wed Sep 28 15:48:29 1994
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Date: Wed, 28 Sep 94 15:36:54 PDT
From: jonp@qdt.com (Jon Powell)
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To: ibis@vhdl.org
Subject: SCOPE

Here is a general question.

Do IBIS pin models have SCOPE. That is, can you have a pin model
names (say) OUTPUTDRIVER in one .ibs file and another with the
same name in another .ibs file without the names being 
considered to overlap?

jonp@qdt.com

From Arpad_Muranyi@ccm.fm.intel.com  Thu Sep 29 09:10:39 1994
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <940929090630_1@ccm.hf.intel.com>
To: ibis@vhdl.org, jonp@qdt.com
Subject: Re: SCOPE


Text item: 

I think they should be handeled just like the "local variables" in programming 
languages like C.  If it is not handeled that way, you might run into duplicate 
buffers in a simulation, and if they are not identical despite their name being 
the same, you are in trouble.

Arpad


Here is a general question.
     
Do IBIS pin models have SCOPE. That is, can you have a pin model 
names (say) OUTPUTDRIVER in one .ibs file and another with the 
same name in another .ibs file without the names being 
considered to overlap?
     
jonp@qdt.com

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Subject: SCOPE
To: ibis@vhdl.org
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From jonp@qdt.com  Thu Sep 29 09:48:08 1994
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Date: Thu, 29 Sep 94 09:24:59 PDT
From: jonp@qdt.com (Jon Powell)
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To: ibis@vhdl.org
Subject: more on SCOPE

OK,

how about this. If indeed the Pin Model names have lexical scope
in an ibs file. How do we (humans) refer to them?

example:

I have a problem with this on Pin Model it is called OUTPUT. how
can I fix it?

1) the .ibs file name is unique so I can say ibs_file_name.OUTPUT

2) the .ibs file name is unique for any given company so I
   can say INTEL.ibs_file_name.OUTPUT

3) other ideas.

jonp

From Will_Hobbs@ccm2.jf.intel.com  Thu Sep 29 10:31:10 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940929102713_2@ccm.jf.intel.com>
To: Arpad_Muranyi@ccm.fm.intel.com, ibis@vhdl.org, jonp@qdt.com
Subject: Re[2]: SCOPE


Text item: 

Jon,

I agree with Arpad,  If they are not treated as local variables, you might have 
unintended cross-linking of models and erroneous data being used and generated.

Will

I think they should be handeled just like the "local variables" in programming 
languages like C.  If it is not handeled that way, you might run into duplicate 
buffers in a simulation, and if they are not identical despite their name being 
the same, you are in trouble.

Arpad


Here is a general question.

Do IBIS pin models have SCOPE. That is, can you have a pin model 
names (say) OUTPUTDRIVER in one .ibs file and another with the 
same name in another .ibs file without the names being 
considered to overlap?

jonp@qdt.com

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Subject: SCOPE
To: ibis@vhdl.org
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Subject: Re: SCOPE
To: ibis@vhdl.org, jonp@qdt.com
Message-Id: <940929090630_1@ccm.hf.intel.com>
From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
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From Arpad_Muranyi@ccm.fm.intel.com  Thu Sep 29 12:15:02 1994
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <940929121104_3@ccm.hf.intel.com>
To: jonp@qdt.com, ibis@vhdl.org
Subject: Re: more on SCOPE


Text item: 

Jon,

I am not sure what you mean by "fix it".

As a human, I would just call it: model OUTPUT of IBIS_FILE_NAME copmonent.  
This is the same as your first option.  However, if you think there might be 
more companies with the same component name (second sourcing), you might add the
company name to it as in your second option.  Then I would say: model OUTPUT of 
COMPANY's IBIS_FILE_NAME component.

Of course, I would say it this way only as a human...  I am not sure how those 
Godly people would say it who gathered earlier this year I believe in Oregon...

Arpad

OK,
     
how about this. If indeed the Pin Model names have lexical scope 
in an ibs file. How do we (humans) refer to them?
     
example:
     
I have a problem with this on Pin Model it is called OUTPUT. how 
can I fix it?
     
1) the .ibs file name is unique so I can say ibs_file_name.OUTPUT
     
2) the .ibs file name is unique for any given company so I
   can say INTEL.ibs_file_name.OUTPUT
     
3) other ideas.
     
jonp

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Subject: more on SCOPE
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From cheerl_r@karoshi.vlsi.com  Thu Sep 29 12:32:13 1994
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From: cheerl_r@karoshi.vlsi.com (Rakesh Cheerla)
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To: ibis@vhdl.org
Subject: Programmable Pads


Is there any prescribed way to model programmable pads in Ibis.

Depending on the logic value of a switch, a programmable pad may have different
rise/fall times or drive strength.



From Arpad_Muranyi@ccm.fm.intel.com  Thu Sep 29 13:08:33 1994
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <940929130403_2@ccm.hf.intel.com>
To: ibis@vhdl.org, cheerl_r@karoshi.vlsi.com
Subject: Re: Programmable Pads


Text item: 

As far as I can remember we cannot do this currently in IBIS, other than making 
a separate model for each value of the programming switch and then selecting the
desired model manually based on the value of the switch.

Arpad Muranyi
Intel Corporation

Is there any prescribed way to model programmable pads in Ibis.
     
Depending on the logic value of a switch, a programmable pad may have different 
rise/fall times or drive strength.

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Subject: Programmable Pads
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From: cheerl_r@karoshi.vlsi.com (Rakesh Cheerla)
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From huq@rockie.nsc.com  Thu Sep 29 13:21:47 1994
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9409292020.AA02495@rockie.nsc.com>
To: ibis@vhdl.org
Subject: v2.0 RS-232 model ready

Hi,
I have a v2.0 model available for verification by Simulation
vendors. I have passed this to the some companies on a request 
basis only. Once I get some feedback, it will be offically 
released to the IBIS forum.

Sometime in mid OCT, I will also pass around 2 more models that
use the differential features.

Regards,
Syed Huq
National Semiconductor.


From scott@icx.com  Thu Sep 29 16:00:03 1994
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To: ibis@vhdl.org
Subject: The '_' char vs. the ' ' char
Date: Thu, 29 Sep 1994 15:32:35 -0700
From: Scott Aron Bloom <scott@icx.com>

One thing that I have noticed is the lack of the '_' character in the 
[POWER Clamp] and [GND Clamp] keywords.  They are in the 1.1 version spec,
but not the 2.0.  Has this been addressed?  Should a parser recoginze both?
Should it be Version Specific?


Scott Aron Bloom
Interconnectix, Inc.

From Will_Hobbs@ccm2.jf.intel.com  Thu Sep 29 16:29:54 1994
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From: Will Hobbs <Will_Hobbs@ccm2.jf.intel.com>
Message-Id: <940929162204_2@ccm.jf.intel.com>
To: scott@icx.com, ibis@vhdl.org
Subject: Re: The '_' char vs. the ' ' char


Text item: 

Scott,

In IBIS V2.0, under the section, "General syntax rules and guidelines for 
ASCII IBIS files, guideline 7 says: "Underscores and spaces are equivalent in 
keywords.  Spaces are not allowed in sub-parameter names.

Regards,

Will Hobbs
Intel Corp.

One thing that I have noticed is the lack of the '_' character in the [POWER 
Clamp] and [GND Clamp] keywords.  They are in the 1.1 version spec, but not the 
2.0.  Has this been addressed?  Should a parser recoginze both? Should it be 
Version Specific?


Scott Aron Bloom
Interconnectix, Inc.

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From: Scott Aron Bloom <scott@icx.com>
Date: Thu, 29 Sep 1994 15:32:35 -0700
Subject: The '_' char vs. the ' ' char
To: ibis@vhdl.org
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From scott@icx.com  Thu Sep 29 17:59:32 1994
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To: ibis@vhdl.org
Subject: Addition to teh reflector
Date: Thu, 29 Sep 1994 17:30:05 -0700
From: Scott Aron Bloom <scott@icx.com>

My email address has changed.  Please change it from
blooms@icx.com to scott@icx.com

Also please add blooms@ece.orst.edu to the list

Scott Bloom
Interconnectix, Inc.

From Arpad_Muranyi@ccm.fm.intel.com  Fri Sep 30 11:07:13 1994
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <940929181145_6@ccm.hf.intel.com>
To: scott@icx.com, ibis@vhdl.org
Subject: Re: The '_' char vs. the ' ' char


Text item: 

Scott,

There was a BIRD, if I remeber correctly, which recommends the use of 
spaces instead of underscores in keywords.  I am not sure what number it 
was or when it happened, but as far as know it, it is official.  If nobody 
else responds to this, and you need more info I can check into it more.

Arpad Muranyi
Intel Corporation

******************************************************************


One thing that I have noticed is the lack of the '_' character in the 
[POWER Clamp] and [GND Clamp] keywords.  They are in the 1.1 version spec, 
but not the 2.0.  Has this been addressed?  Should a parser recoginze both? 
Should it be Version Specific?
     
     
Scott Aron Bloom
Interconnectix, Inc.

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From: Scott Aron Bloom <scott@icx.com>
Date: Thu, 29 Sep 1994 15:32:35 -0700
Subject: The '_' char vs. the ' ' char
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