
From huq@rockie.nsc.com  Mon Dec  4 10:11:22 1995
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Date: Mon, 4 Dec 95 10:04:26 PST
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9512041804.AA03621@rockie.nsc.com>
To: ibis@vhdl.org
Subject: IBIS face-to-face meeting plans..

IBISfans,

		EIA/ANSI-656 IBIS Face to Face meeting-1996
		 (hosted by National Semiconductor Corp.)
		------------------------------------------

Welcome to the upcoming IBIS face-to-face meeting January 1996.

	Place: Westin Hotel, Santa Clara, California
	Date:  Jan 29th Monday(one day)
	Time:  8am - 5pm

We are in the process of updating the meeting agenda and adding
any additional topics as necessary. The meeting will be open
for discussions on Semiconductor/EDA vendors issues regarding IBIS
as well as various technical discussions.

If you would like a particular item to be added to the agenda, pls
send an E-mail to either one of the following:

		Will Hobbs(Will_Hobbs@ccm.jf.intel.com)
		Bob Ross (bob@icx.com)
		Syed Huq (huq@rockie.nsc.com)

Breakfast, Lunch and Snacks will be provided so please RSVP to:
	
		huq@rockie.nsc.com

There will also be a celebration dinner after the meeting.

Details of Maps/directions/final agenda will be posted soon so stay
tuned.

Regards,
Syed
National Semiconductor Corp.


From kellee@montana.nwlink.com  Mon Dec  4 13:42:32 1995
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Date: Mon, 4 Dec 1995 13:35:29 -0800
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: New Visual IBIS editor shareware tool

I just finished up a new tool that many IBIS model developers may
enjoy.  It gives you an integrated environment for developing an IBIS
model and it is SHAREWARE.  

It includes the following features:
 - Text editor (standard very similar to the one in Microsoft C++)
 - IBIS version 1.1 and 2.1 syntax checker (uses the IBIS parser code)
 - V/I table viewer
 - Wavetable viewer
 - IBIS wizard, (creates a template file in either version 1.1 or 2.1
   format.


Visual IBIS Editor will run on Windows 95, Windows NT, or Windows 3.1.
If you run it on Windows 3.1 you will also need to have Win32S version 1.3
or newer loaded.

The program is available at the HyperLynx web site:  http://www.hyperlynx.com
Our web site is not officially open yet but you can still download the Visual
IBIS editor.

P.S.  Sorry I missed the Friday meeting.  I stayed up very late Thursday night
(read as Friday morning) trying to finish Visual IBIS Editor.

I hope this helps people create more IBIS models.

If you have any suggestions, comments, bugs etc you can email me at
kellee@hyperlynx.com

Have a great day...Kellee Crisafulli, HyperLynx Inc.


From Will_Hobbs@ccm.jf.intel.com  Mon Dec  4 15:27:11 1995
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From: Will Hobbs <Will_Hobbs@ccm.jf.intel.com>
Message-Id: <Mon, 04 Dec 95 15:19:14 PST_2@ccm.jf.intel.com>
To: kellee@montana.nwlink.com, ibis@vhdl.org
Subject: Re: New Visual IBIS editor shareware tool


Text item: 

Kellee,

Way to go! This is the in the truest IBIS cooperative effort 
tradition. One of the most gratifying aspects of IBIS has always been 
the extraordinary amount of cooperative effort, and yours is a shining 
example.

Will

I just finished up a new tool that many IBIS model developers may 
enjoy.  It gives you an integrated environment for developing an IBIS 
model and it is SHAREWARE.

It includes the following features:
 - Text editor (standard very similar to the one in Microsoft C++)
 - IBIS version 1.1 and 2.1 syntax checker (uses the IBIS parser code) 
 - V/I table viewer
 - Wavetable viewer
 - IBIS wizard, (creates a template file in either version 1.1 or 2.1
   format.


Visual IBIS Editor will run on Windows 95, Windows NT, or Windows 3.1.
If you run it on Windows 3.1 you will also need to have Win32S version 1.3 
or newer loaded.

The program is available at the HyperLynx web site:  http://www.hyperlynx.com 
Our web site is not officially open yet but you can still download the Visual 
IBIS editor.

P.S.  Sorry I missed the Friday meeting.  I stayed up very late Thursday night 
(read as Friday morning) trying to finish Visual IBIS Editor.

I hope this helps people create more IBIS models.

If you have any suggestions, comments, bugs etc you can email me at 
kellee@hyperlynx.com

Have a great day...Kellee Crisafulli, HyperLynx Inc.

Text item: External Message Header

The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

Subject: New Visual IBIS editor shareware tool
From: Kellee Crisafulli <kellee@hyperlynx.com>
To: ibis@vhdl.org
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From kellee@montana.nwlink.com  Mon Dec  4 17:54:25 1995
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Running Visual IBIS Editor on Windows 3.1

Hi Hiroshi,

you wrote:
>Dear Dr.Crisafulli,
>thank you for releasing WinIbis.
>My name is Hiroshi Matsumoto, a reflector of IBIS in NEC, Japan.
>I tried to use it on Windows 3.1, but the software made a 
>warning, saying "COMCTL32.DLL cannot be found".
>I suppose this DLL is for Windows 95, isn't it?
>I would like to know how to run WinIbis on Windows 3.1 more detail.
>Please let us (= all Ibisians) know this point.
>

Yes as I stated the Visual IBIS Editor runs great on Windows 95
and Windows NT.  It will also run on Windows 3.1 and WFW 3.11.
There is some extra software needed to run on the Windows 3.1
platform.

  It will run with windows 3.1 it does however require that
the Win32s extensions from Microsoft be loaded into windows.
I will probably make these available on our web site in the next
few days.  If you want to get them immediately you could download
them from our FTP site at:  ftp.hyperlynx.com   and then look in the
following sub directory:  pub/hyperlynx/outgoing.  You will need to
download 3 very large files:  w32s130a.zip, w32s130b.zip and w32s130c.zip
Each of these files is approximately 1 megabyte.  Each file should be
unzipped and the contents copied to a separate floppy diskette.  When
you have all 3 floppy disks you can install them into your windows
3.1 platform.  These are Microsoft programs which we have not modified
in any way.  These extensions allow Windows 3.1 to run 32bit software
just like Windows 95 or Windows NT.

I am not sure if the Win32s software will work properly with the Japanese
versions of Windows.  I don't know of any reason there would be a problem.
I don't believe there is any international versions of the Win32s program.

I wish you the best of luck.
Have a great day...Kellee Crisafulli, HyperLynx Inc.


From jonp@qdt.com  Tue Dec  5 16:05:03 1995
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Date: Tue, 5 Dec 95 09:25:13 PST
From: jonp@qdt.com (Jon Powell)
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	id AA14937; Tue, 5 Dec 95 09:25:12 PST
To: ibis@vhdl.org
Subject: LOGOS

Here is the status of the logos for the WWW page. Note that
I am missing many key players. For some of these people I do
have the logo I used at DAC but I at least need the release signed
with written direction to use the old logo.

come on, this is an easy one.

Please feel free to send email directly to jonp@qdt.com

12/5/95

COMPANY			LOGO			RELEASE

Interconnectix		icx.gif			X
ATT GIS			attgis.gif		X
National Semi		national.gif		X
Quantic			quantic.gif		X
Contec CAE		contec.gif		X
Hyperlynx		hyper.gif		X
Incases			incases.gif		X
Intel			intel.gif		X
Quad Design		quad.gif		X
Unicad			unicad.gif		X
Mentor			?			?
Cadence			?			?
VLSI			?			?
TI			?			?
IBM			?			?
Metasoftware		?			?
etc.			?			?

From bob@icx.com  Tue Dec  5 16:06:15 1995
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Date: Tue, 5 Dec 95 16:01 PST
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: IBIS MINUTES 12/01/95

 DATE:    December 5, 1995
 
 SUBJECT: 12/1/95 EIA IBIS Open Forum Meeting Minutes
 
 VOTING MEMBERS:
 AT&T Global Info Solutions     Dave Moxley*
 Cadence Design                 Sandeep Khanna, C. Kumar*
 Contec CAE, Ltd.               Dileep Divekar*
 HyperLynx                      Kellee Crisafulli
 IBM                            Jay Diepenbrock
 INCASES                        Werner Rissiek, Olaf Rethmeier*
 Intel Corporation              Stephen Peters*, Will Hobbs*, Arpad Muranyi,
                                Derrick Duehren
 Interconnectix, Inc.           Bob Ross*
 Meta-Software                  Les Spruiell, Mei Wong, You-Pang Wei, 
                                John Sliney
 Motorola                       Ron Werner
 National Semiconductor         Syed Huq*, Atul Agarwal, Cheng-Yang Kao
 NEC                            Hiroshi Matsumoto, Eldar Yazbashevz
 Quad Design                    Jon Powell*, Chris Myles, Chris Rokusek*
 Quantic Labs                   Mike Ventham*
 Tanner Research, Inc.          Scott Wedge, Ed Miller, Peter Parrish
 Texas Instruments              Roger Cline, Ben Andresen
 Thomson-CSF/SCTF               Jean LeBrun
 UniCAD Canada Ltd.             Stephen Lum
 VLSI Technology                Dick Ulmer, Sung Oh*
 Zuken-Redac                    John Berrie
 
 OTHER PARTICIPANTS:
 AMP                            Hank Herrmann*
 ARPA                           Randy Harr
 Anacad                         Steffen Rochel
 Ansoft                         Henri Maramis
 Atmel Corporation              Dan Terry
 Cadlab                         Ralf Bruning
 CFI                            Ron Christopher, Don Cottrell*
 Digital Equipment Corp.        Barry Katz
 EIA                            Patti Rusher*
 High Design Technology         Michael Smith, Dr. Ing. Cosso
 Hewlett Packard                Tom Langdorf, Karl Kachigan, Henry Wu
 Integrated Silicon Systems     Eric Bracken
 Intergraph                     Ian Dodd, David Wiens, Walter Katz
 IntuSoft                       Charles Hymowitz
 LSI Logic Corp.                Satish Pratadneni
 Mentor Graphics                Ravender Goyal, Greg Doyle
 Micron Technology              Brian Johnson                       
 MicroSim                       Arthur Wong
 North Carolina State U.        Steve Lipa, Michael Steer
 OptEM Engineering, Inc.        Benny Leveille, Ken Ehn
 Pacific Numerix                Paul K. U. Wang
 Symmetry                       Martin Walker
 Synopsys, Logic Modeling G.    Bill Lattin
 Univ. of Illinois, Urbana      Raj Mittra 
 Zeelan Technology              George Opsahl, Hiro Moriyasu
 (Independent)                  Bob Ward

 In the list above, attendees at the meeting are indicated by *.
 
 Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as 
 follows:

      Date       Bridge Number    Reservation #    Passcode  
      12/15/95   (916) 356-9200   2-41859          7747258
      1/12/96    (916) 356-9200   2-41860          1918954

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each open forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.
 
 -------------------------------- MINUTES -------------------------------------
 
 INTRODUCTIONS
 Hank Herrmann of AMP, Inc. indicated his interest in IBIS as a result of
 of meeting Stephen Peters at a JEDEC JC-15 meeting.  

 Don Cottrell of CFI joined us to discuss the DCL and Roadmap relationship
 with IBIS. 

 
 EIA MEMBERSHIP AND TREASURER'S REPORT
 No change in the treasury was reported.  TI did purchase the ibischk2 source
 code.


 MINUTES REPORT, MISC.
 The October 27, 1995 Minutes have been changed to include Kellee Crisafulli
 as an attendee.


 MISCELLANY/ANNOUNCEMENTS
 None.


 PRESS UPDATES
 Patti Rusher reported that the press release announcing the ratification
 of IBIS as EIA-656 was sent out last week.  Will Hobbs indicated that
 he has already had discussion from a United Kingdom publication editor.
 Will Hobbs also reported the EE Times article of November 27, 1995
 "Group eyes 'free' VHDL sim models", by Richard Goering, mentioned IBIS
 and quotes by Will in the article.  The article discussed the Free
 Model Forum activity which is seeking to acquire, develop and distribute
 IBIS models as well.  C. Kumar indicated that representatives were visiting
 Cadence to seek funding from Vendors for modeling efforts.


 NEW MODELS
 The PentiumPro (P6 Models) were made publically available November 1.


 OPENS FOR NEW ISSUES
 Free Model Foundation
 Depletion Capacitance Discussion


 EIA-656 ANSI RATIFICATION
 Patti Rusher has been pushing EIA-656 ratification as an ANSI standard.
 She still expects a 1995 date on the ANSI Standard.  No further action
 is needed by the IBIS committee.


 EIA/IBIS 1996 MEMBERSHIP
 Patti Rusher will send out EIA/IBIS 1996 membership renewal forms in
 December. Annual membership is $500 per company.  Bob Ross indicated that
 for the purposes of meeting quorums existing memberships will be carried 
 through the end of January to give time for the membership fees to be paid.
 No additional golden parser fee is needed for those who have already purchased
 the source code of Version 2.1, and the same 50% discounts apply for those
 who have not purchased the source code.  Will Hobbs indicated that there
 are 22 parser licencees.
 

 WEB UPDATE (AND EIA)
 Patti Rusher reported that the Web page issue is still under discussion
 and is of concern to many groups.  Uniformity of content and security are
 issues, and EIA has hired a consultant to help out.  She is pushing hard for
 a resolution at the Monday, December 4 internal meeting.  Syed Huq needs to
 know what can be published.  Everything is in place to be copied.

 Jon Powell indicated he received copies of logo permission letters from
 10 companies.  This needs to be checked since Quad Design was not included.
 Jon will work with Syed Huq to provide the Logos in a common format (probably
 GIF) so that a collage of logos can be created by pointers.  We also 
 discussed the possibility of linking the logos to their respective 
 companies' home pages.

 Unless the EIA web issues are resolved, further discussion on web plans
 including the possibility of setting up one separately on vhdl.org will
 occur at the next meeting.


 USERS' GROUP
 Bob Ross reported that the IBIS USERS' GROUP reflector ibis-users@vhdl.org
 is active.  No real activity has occurred to date, but discussion issues
 are expected.  Over 240 members are in this and the ibis@vhdl.org groups.
 No membership breakdown is available.  Many countries are represented.


 Also there is a new "wip" directory for work in progress under /pub/ibis
 on vhdl.org to be used for temporarily storing working documents.  Currently
 a draft of Version 3.0 exists which includes approved BIRD28.3 and BIRD30.2.
 

 FACE TO FACE MEETING
 Syed Huq has made arrangements for National to host the meeting on Monday,
 January 29 before SuperCon96.  He has scheduled a room, equipment and food.
 He is planning for about 35-40.  This meeting will be focused on technical
 discussions.  A group dinner is planned to celebrate the standardization
 of IBIS.

 AR - Syed Huq post details on meeting and request an RSVP for planning 
 purposes.  [Done]

 Will Hobbs discussed devoting a portion of time to the modeling validation
 concerns that exist in semiconductor companies, particularly in relations
 to on-going production testing.  The problem is how to verify in the 
 testers that the components meet the predictions of the models - what to
 measure, how many points on a V/I curve are sufficient, etc.  Can and/or
 should IC vendors guarantee by test that the models accurately bracket
 the silicon characteristics?   Intel and National will participate in this,
 but other vendors are encouraged to give their experiences and concerns as
 well.

 Another important segment is to seek actual users of IBIS models and ask
 them to present their experiences and problems.  IBIS participants who
 are users or who have worked with users are encouraged to seek their
 participation.  Several members indicated that they will follow through
 on this.

 Syed Huq did a direct polling of roster members and found that 7 supported
 IBIS Version 2.1 and 7 supported Version 1.1.  His concern was that some
 Version 2.1 level models will not work properly at lower levels and 
 encouraged EDA Vendor Discussion of their IBIS Verison 2.1 plans.  Such
 a discussion can also be tied in with the general modeling issue discussion.

 People who have topics to present should summit them to Bob Ross, Syed Huq
 or Will Hobbs.  Bob, Syed and Will will coordinate the agenda.

 AR - Everyone solicit participation by IBIS Users.
 
 AR - Anyone who wants to present notify Bob, Syed or Will.
 
 MODEL USAGE TRACKING
 Will Hobbs mentioned Intel has IBIS models on their bulletin board, but
 is not aware of any usage tracking activities.  Syed Huq stated that
 National IBIS models are available from the external National Web site:

   //www.nationalsemi.com

 They are trying to find a way to track models usage.


 GOLDEN PARSER UPDATE
 Jon Powell created the executables for ibischk2, and Bob Ross put them
 on vhdl.org.  Will Hobbs has sent out the final version of source code.

 Several problems have been discovered by Bob Ross and Chris Rokusek which
 will require a revised bug-fix release.  Our intent is to capture all
 of the bugs and do an update in January.   These problems will be sent to
 Paul Munsey for review and a quote on fixing the problems.

 AR - Anyone finding Parser bugs submit them to Bob Ross.  Include a test
 case, if possible.

 So far the bugs are (1) not accepting multiple [Disclaimer] keywords,
 (2) giving an incorrect Warning message when metric unit multipliers
 are used for [Define Package Model] matrix entries, and (3) not detecting
 a syntax error for incorrect [Model] sub-parameters "Model_type=", 
 "Polarity=", and "Enable=".


 SPICE TO IBIS VERSION 2.1
 Bob Ross reported that he has submitted some bugs and enhancement requests
 on s2ibis-v2.091 (a Beta version).  Since this is a Beta version an update
 is expected.


 BIRD31 - Connector Models
 Bob Ross introduced BIRD31.  The primary aspects are that it relies on
 existing syntax and introduces no new keywords or sub-parameters.  It
 is a new section which will follow the Package Modeling Section in the 
 Specification.  The controversial aspect of this proposal is that 
 connectors would be split into two parts for each board.  They would
 be joined by Simulator specification which "mates" the models by 
 series concatenation.  

 Hank Herrman of AMP expressed concern that "mated models" representing
 connectors are not easily split, nor are they necessarily meaningful
 in a split mode, which represents unconnected connector.  So an alternative
 proposal will be a "mated connector model" by itself.  Dave Moxely suggested
 that Components which are for connector pins could be designated by a
 "mated model" keyword.

 The BIRD did not address cables, but one possiblility is that cables could 
 be represented by mated models as longer connectors.

 Hank also would like to see a parameter that specifies the bandwidth
 or minimum time response for which a connector is valid because models
 of increased complexity are needed for higher speed applications.

 Bob Ross will write up some of the discussion and carry this on the
 reflector and at the Face-to-Face Meeting.


 BIRD28.3+  PACKAGE MODEL ENHANCEMENT
 Stephen Peters has reviewed C. Kumar's extension and now sees the merits
 of adding a pin ordering file and Matrix name parameter for extending
 the package model.  Kumar reported that one benefit will be to call
 smaller matrices that are used often, for a more compact description.
 This would allow a more general set of coupling relationships.

 C. Kumar plans to submit to Will Hobbs a new BIRD on this.

 Another discussion included generalizing the loss model to include the
 G matrix, since it may become more factor in MCMs, package models,
 cables with dielectric losses.  This would take another BIRD.


 EGG8 - PHYSICAL PACKAGE DISCUSSION
 Bob Ross introduced the subject of EGG8 which would be a significant
 departure for just the IBIS I/O models scope.  Will Hobbs expressed the
 concern that one of the biggest modeling issues is how to describe MCMs
 and SIMM packages.  So this proposal is of great interest to the IBIS
 community and needs to be pursued.  A discussion at the next meeting 
 can be reserved for this issue.

 
 DCL RELATIONSHIP WITH IBIS
 Don Cottrell of CFI reported that Ron Christopher has identified areas where
 the Delay Calculation Language (DCL) and IBIS may be related.  DCL needs
 loading conditions for correct delays, and IBIS can be of help.  DCL focuses
 on delays within an MCM or Chip.

 He requested that someone on the IBIS committee be identified to work
 with him and the DCL community on any joint common ground issues and help
 generate possible proposals.  Stephen Peters voluteered to get involved
 and report back on progress.
 

 EGG6 - TTL and CMOS
 Chris Rokusek indicated that the efforts to distinguish technologies by
 the data itself suggested by Arpad Muranyi and others does not always work.
 His major concern is that to simulate the rising edge of a TTL model,
 it is voltage source driven, versus a current source driven for CMOS and
 pulldown characteristics.  ECL type structures are already differentiated
 by Model_type.  He will present his findings on the reflector to stimulate
 discussion an consideration of alternatives.


 DEPLETION CAPACITANCE
 Bob Ross indicated that the depletion capacitance issue which has been
 discussed in the past is ripe for an Egg to generate more discussion.  He
 plans to submit one.


 NEXT MEETING:
 It is set on Friday, December 15, 1995, and the following meeting is on
 Friday, January 12, 1996 after the Christmas and New Years Holidays.


 ==============================================================================
                                       NOTES
 
 IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210
             will_hobbs@ccm.jf.intel.com
             Server Chipset System Validation Manager, Intel Corp.
             2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA
 
 VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259
             jonp@qdt.com
             1385 Del Norte Rd., Camarillo, CA 93010
 
 SECRETARY:  Bob Ross (503) 603-2523, fax (503) 639-3469
             bob@icx.com
             10220 SW Nimbus Ave, K4, Portland, OR 97223
 
 The following email addresses are used:

   ibis-request@vhdl.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
       or both.  State your request.

   ibis-info@vhdl.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@vhdl.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.

   ibis-users@vhdl.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via ftp anonymous, "guest" login from 
 telnet or dial-in (415-335-0110), or send an email request to the automatic 
 archive server, archive@vhdl.org.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================
 



From huq@rockie.nsc.com  Tue Dec  5 16:58:58 1995
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Date: Tue, 5 Dec 95 16:52:03 PST
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9512060052.AA11590@rockie.nsc.com>
To: ibis@vhdl.org, bob@icx.com
Subject: Re: IBIS MINUTES 12/01/95-correction

Hi,

A URL correction:
The National Web site is: http://www.natsemi.com

All National released IBIS models are available from the Web.

Thanks,
Syed
National Semiconductor.

>  
>  MODEL USAGE TRACKING
>  Will Hobbs mentioned Intel has IBIS models on their bulletin board, but
>  is not aware of any usage tracking activities.  Syed Huq stated that
>  National IBIS models are available from the external National Web site:
> 
>    //www.nationalsemi.com
> 
>  They are trying to find a way to track models usage.
> 
> 
> 

From hank.herrmann@amp.com  Wed Dec  6 05:40:40 1995
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From: Herrmann Hank <hank.herrmann@amp.com>
To: IBIS Reflector <ibis@vhdl.org>
Subject: RE: IBIS MINUTES 12/01/95
Date: Wed, 06 Dec 95 08:29:00 E
Encoding: 43 TEXT
X-Mailer: Microsoft Mail V3.0


Bob,

First I want to congratulate you on spelling my name correctly.   That 
almost never happens.  Also, you have done an excellent job of capturing all 
the discussions that took place in the last meeting.

There are two points that I think were discussed that I did not see in the 
minutes.  Perhaps they were too small to include but I would like to clarify 
and confirm them.

First, I thought someone mentioned the desire to discuss connector modes at 
the Face-to-Face Meeting in January.  I wonder if anyone has any specific 
points they would like to discuss.  Since I am considering trying to attend, 
this could significantly influence my decision.  (Cross country trips for a 
one day meeting are not popular with me or my management.)

Second, when BIRD 31 was discussed, I recognized the need for many users to 
have unmated models to simulate "not-fully-populated busses".  They would 
not be used for such analyses as cables or I/O connectors when there is a 
complete interconnection.  While we do not routinely supply unmated models 
now, there is no reason that they could not be provided.  They would even be 
simpler than "part of the mated model" which the BIRD suggests.  What I 
recommend is that two types of connector models be defined.  First, mated 
models for most interconnection applications.  Second, unmated models that 
have no through connection for situations that demand simulations of 
 "not-fully-populated busses".

I hope these points are helpful to the forum.  I enjoyed participating with 
you all and look forward to future work together.

Regards,

Hank Herrmann
Technical Staff Member
AMP Incorporated, Electro-Magnetic Technology
M.S. 106-14
P.O. Box 3608
Harrisburg, PA 17105-3608

            Phone:  717-986-5534
                 FAX:  717-986-5643
   INTERNET:  hank.herrmann@amp.com

From hank.herrmann@amp.com  Wed Dec  6 07:54:04 1995
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From: Herrmann Hank <hank.herrmann@amp.com>
To: IBIS Reflector <ibis@vhdl.org>
Subject: RE: IBIS MINUTES 12/01/95
Date: Wed, 06 Dec 95 10:43:00 E
Encoding: 103 TEXT
X-Mailer: Microsoft Mail V3.0


Thank you for your observation and question.

My concept of "unmated" is that the model should be self-sufficient (i.e., 
work properly without extra 'patches and band aids' and have connections at 
one side only.   So it would look like this ...

     Board1--> conn_model (unmated)

There would be no additional load required outside of the model.

For SPICE type simulators there may have to be some standard DC path, or 
'assumed load' to enable an unmated connector model to function properly. 
 That would not likely be required by most models, however, because there 
would already be the necessary DC paths to satisfy SPICE within the model 
itself or the bus.  A standard load may be something that should be defined 
for stand-off type stacking connectors that are long relative to the models' 
minimum applicable edge rate.

At this point I have only proposed, for consideration, the concept of both 
mated and unmated connector models as opposed to a mated model with an 
interface connection such as is proposed in BIRD 31.  Many details need to 
be worked out until that is finally accomplished if the concept is 
acceptable to everyone.

Hope this is helpful.

Regards,

 Hank
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 ----------
From: cpk
To: amp03847
Subject: RE: IBIS MINUTES 12/01/95
Date: Wednesday, December 06, 1995 9:51AM

Clarification:

Does unmated mean that you assume some kind of load at the other end

Board1--> conn_model --> assumed load  (unmated)
Board1 -> conn_model->board2 - full model

Thanx
 - kumar

>
>
> Bob,
>
> First I want to congratulate you on spelling my name correctly.   That
> almost never happens.  Also, you have done an excellent job of capturing
all
> the discussions that took place in the last meeting.
>
> There are two points that I think were discussed that I did not see in the 

> minutes.  Perhaps they were too small to include but I would like to
clarify
> and confirm them.
>
> First, I thought someone mentioned the desire to discuss connector modes 
at
> the Face-to-Face Meeting in January.  I wonder if anyone has any specific
> points they would like to discuss.  Since I am considering trying to
attend,
> this could significantly influence my decision.  (Cross country trips for 
a
> one day meeting are not popular with me or my management.)
>
> Second, when BIRD 31 was discussed, I recognized the need for many users 
to
> have unmated models to simulate "not-fully-populated busses".  They would
> not be used for such analyses as cables or I/O connectors when there is a
> complete interconnection.  While we do not routinely supply unmated models 

> now, there is no reason that they could not be provided.  They would even
be
> simpler than "part of the mated model" which the BIRD suggests.  What I
> recommend is that two types of connector models be defined.  First, mated
> models for most interconnection applications.  Second, unmated models that 

> have no through connection for situations that demand simulations of
>  "not-fully-populated busses".
>
> I hope these points are helpful to the forum.  I enjoyed participating 
with
> you all and look forward to future work together.
>
> Regards,
>
> Hank Herrmann
> Technical Staff Member
> AMP Incorporated, Electro-Magnetic Technology
> M.S. 106-14
> P.O. Box 3608
> Harrisburg, PA 17105-3608
>
>             Phone:  717-986-5534
>                  FAX:  717-986-5643
>    INTERNET:  hank.herrmann@amp.com
>

From huq@rockie.nsc.com  Thu Dec  7 13:20:25 1995
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Date: Thu, 7 Dec 95 13:13:30 PST
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9512072113.AA17603@rockie.nsc.com>
To: ibis@vhdl.org, jonp@qdt.com
Subject: Re: LOGOS and Website Links

Hello all,

I am in the process of adding all these company logos on the EIA/IBIS
home page. In order to create a hypertext link, I will need your Web
URL. If you have a Web site already setup, pls pass me your URL.
If you do not have one, let me know anyway.

> Interconnectix		www.icx.com			
> ATT GIS			??????????
> National Semi		        www.natsemi.com		
> Quantic			??????????		
> Contec CAE		        ??????????		
> Hyperlynx		        www.hyperlynx.com		
> Incases			??????????		
> Intel			        www.intel.com		
> Quad Design		        ??????????		
> Unicad			??????????		

By clicking on your company logo, a user will be able to access your
Website.

Responses are requested no later than Fri Dec 8th(tomorrow !!)

Regards,
Syed.
---------------------------------------------------------------------------
> From jonp@qdt.com Tue Dec  5 16:39:39 1995
> Date: Tue, 5 Dec 95 09:25:13 PST
> From: jonp@qdt.com (Jon Powell)
> To: ibis@vhdl.org
> Subject: LOGOS
> Content-Length: 708
> 
> Here is the status of the logos for the WWW page. Note that
> I am missing many key players. For some of these people I do
> have the logo I used at DAC but I at least need the release signed
> with written direction to use the old logo.
> 
> come on, this is an easy one.
> 
> Please feel free to send email directly to jonp@qdt.com
> 
> 12/5/95
> 
> COMPANY			LOGO			RELEASE
> 
> Interconnectix		icx.gif			X
> ATT GIS			attgis.gif		X
> National Semi		national.gif		X
> Quantic			quantic.gif		X
> Contec CAE		contec.gif		X
> Hyperlynx		hyper.gif		X
> Incases			incases.gif		X
> Intel			intel.gif		X
> Quad Design		quad.gif		X
> Unicad			unicad.gif		X
> Mentor			?			?
> Cadence			?			?
> VLSI			?			?
> TI			?			?
> IBM			?			?
> Metasoftware		?			?
> etc.			?			?
> 

From uunet!qdt.com!jonp@uunet.uu.net  Thu Dec  7 17:14:51 1995
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From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell)
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To: uunet!uunet!rockie.nsc.com!huq@uunet.uu.net
Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net
In-Reply-To: <9512072113.AA17603@rockie.nsc.com> (uunet!rockie.nsc.com!huq)
Subject: Re: LOGOS and Website Links

Syed,

For now, Quad Design will be using

www.viewlogic.com/products/timing.html


We should have our own web site up in the next month or so and then I will update you.

From speters@ichips.intel.com  Fri Dec  8 08:46:26 1995
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To: ibis@vhdl.org
Subject: IBIS WEB SITES
Date: Fri, 08 Dec 1995 08:37:55 -0800
From: Stephen Peters <speters@ichips.intel.com>



Hello All:

     While we are in the mode of collecting Web Sites with
IBIS info, Intel's IBIS model can be found at

   http://techdoc.wais.net:2160/

     You will have to 'register', and then you can load
the data sheet and buffer models.



        Regards,
        Stephen Peters
        Intel Corp.

     

From bob@icx.com  Fri Dec  8 12:36:27 1995
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Date: Fri, 8 Dec 95 12:31 PST
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: IBIS AGENDA 12/15/95

                       IBIS Open Forum Meeting Agenda 
                                for 12/15/95
 
                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   2-41859         7747258


 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 
 8:00 Check-In, Intros, Announcements                         Hobbs

      - Intros of New IBIS Participants, Meeting Quorum       Hobbs
      - Membership Update and Treasurers Report               Rusher/Hobbs
      - Review of Previous Meeting's Minutes (and ARs)        Ross
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              All
      - New Models Available, Library Update                  All
      - Opens for New Issues                                  All


 8:15 EIA/IBIS Activities                                            

      - ANSI Ratification of IBIS (EIA-656) Progress          Rusher/Hobbs
      - 1996 Membership                                       Hobbs/Rusher
 
 8:25 Administrative and Project Discussions

      Web Project Update                                      Huq

      January 29, 1996 Face-to-Face Meeting                   Huq
      Model Topics                                            Hobbs/All
      Technical Topics                                        Hobbs/All

      Model Usage Tracking on vhdl.org                        Huq/Peters

      Golden Parser 2.1 Status                                Powell/Ross
 
      S2IBIS 2.1 Status                                       Ross/Steer
       
      New Administrative Issues                               All


 9:00 Technical Discussions

      EGG8 - Physical Package Description Discussion          Crisafulli

      BIRD31 - Connector Models                               Ross

      BIRDxx - Matrix Name Enhancement proposal               Kumar/Peters

      EGG6 - CMOS and TTL Data                                Powell

      New Technical Issues                                    All


 9:50 Wrap Up and Next Meetings Plans                         Hobbs

 9:55 Sign Off
 



From bob@icx.com  Sun Dec 10 18:50:34 1995
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Date: Sun, 10 Dec 95 18:45 PST
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: IBIS EGG9 - Stored Charge

To IBIS members:

Attached is an EGG concerning an old topic - Stored Charge effects in Diodes.
Because of stored charge, a clamping diode will not release instanteously
from the clamped mode as predicted by IBIS models.  There will be a delay
while the diode is turning off.  This creates a glitch which itself can
propogate up and down a line.  This glitch is significant enough that IBIS
should support a way to model its effect.

The major contributor to the effect is the TT parameter which contributes
a non-linear transit time capacitance when a diode is conducting.  The
proposal here is to use a similar parameter by adding [TTgnd] and [TTpower]
keywords to the [Model] keyword description.

Bob Ross,
Interconnectix, Inc.

EGG9 - Proposal for handing Stored Charge Effects:

|==============================================================================
|    Keywords:  [TTgnd], [TTpower]
|    Required:  No.
| Description:  The data for these keywords enters the transist time parameters
|               to estimate the transit time capacitances for the [Gnd Clamp]
|               and [Power Clamp] tables.
| Usage Rules:  For each of these keywords, the three columns hold the transit
|               values corresponding to the typical, minimum and maximum
|               [Gnd Clamp] or [Power Clamp] tables, respectively.  The
|               entries for TT(typ), TT(min), and TT(max) must be placed on
|               a single line and must be separated by at least one white
|               space or tab or tab character.  All three columns are 
|               required under these keywords.  However, data is required
|               only in the typical column.  If minimum and/or maximum values
|               are not available, the reserved word "NA" must be used 
|               indicating the TT(typ) value by default.
| Other Notes:  The transit time capacitance is added to C_comp.  Its value
|               value Ct is approximated by Ct = TT * (q/kT) * Id where TT
|               is transit time, q is electron charge, k is Boltzmann's 
|               constant, T temperature in degrees Kelvin, and Id is the 
|               dynamic diode current when the diode is conducting.  Id can
|               can be found from the [Gnd Clamp] or [Power Clamp] operating
|               points.  If the [Temperature] keyword is not defined, use
|               the default temperature for all Ct calculations
|  |------------------------------------------------------------------------------
| variable      TT(typ)         TT(min)         TT(max)
[TTgnd]         10n             12n             9n
[TTpower]       12n             NA              NA
|
|==============================================================================


Refer to Spice diode reference information concerning the complete equations.
The emission coefficient (N) is assumed to be 1.  For measured values or
cases where N is not 1, use the effective TT values.  So the TT values
may not be the exact values used in a Spice model.

The Spice diode and transistor models differs slightly from the IBIS Clamp
models.  The definition and position of the capacitances is different.
Furthermore, the IBIS table combines the diode and resistor, but can support
more complex non-linear characteristics.
                          
                   Intrinsic
             RS      Diode                        +-----+
                      |\ | ----> Id               |     | ----> Id
       o---/\/\/\--+--| >|--+----o          +-----|Clamp|-----+
                   |  |/ |  |               |     |     |     |
                   |        |          o----|     +-----+     |----o
                   |   | |  |               |       | |       |
                   +---| |--+               +-------| |-------+
                       | |                          | |

                     Cj + Ct                     C_comp + Ct


Fixed values of C_comp serve to estimate voltage dependent non-linear
junction capacitance plus other metalization effects

The Ct value is a function of absolute temperature.  As an approximation,
the default typical temperature is sufficient if [Temperature] is not
specified.  It is recommended to include the [Temperature] keyword when
TT is specified to remove ambiguity regarding minimum and maximum transit
time calculations for CMOS versus Bipolar technologies.

An underlying assumption is that the equations will be applied only to
the Clamping data, not the combined data that includes [Pulldown] and
[Pullup] data.  So when this detail is needed for Output models, the
clamping data needs to be derived, if not provided.

Because of these differences and possible missing details, the simplified
equation and approximation approach is justified to capture the dominant
behavioral effects.  So the TT values may be the effective values 
consistent with the IBIS model and data.


There are several formatting choices to describe transit time:

(1) A [Model] sub-parameter similar to Vinl and Vinh, e.g.,

TTgnd   = 12n
TTpower = 10n

This was not chosen because minimum and maximum process Spice models may have
different values.

(2) A [Model] sub-parameter similar to C_comp, e.g.,

TTgnd      10n       12n        9n
TTpower    12n       NA         NA

This was not chosen because the rules for minimum and maximum columns for
C_comp are by magnitude, whereas the rules for TT are by process extremes.

(3) A [Gnd Clamp] and [Power Clamp] sub-parameter similar to C_comp, e.g

[Gnd Clamp]
TT        10n       12n        9n

This was not chosen for the same reason as (2) and because of [Gnd Clamp]
and [Power Clamp] table complexity.

(4) A [Model] keyword modifier similar to [Temperature] and other keywords
which are a function of typical, minimum and maximum process and measurement
conditions. e.g.,

[TTgnd]         10n             12n             9n
[TTpower]       12n             NA              NA

Since these keywords are related to the [Gnd Clamp] and [Power Clamp] 
tables and to the conditions under which they were derived, this format was
chosen.



From uunet!qdt.com!jonp@uunet.uu.net  Mon Dec 11 09:43:50 1995
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Date: Mon, 11 Dec 95 08:19:50 PST
From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell)
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To: uunet!uunet!icx.com!bob@uunet.uu.net
Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net
In-Reply-To: <m0tOyF6-000GilC@icx.com> (uunet!icx.com!bob)
Subject: Re: IBIS EGG9 - Stored Charge

Do we already have a place for the Rs? The experiments I did last year when we
were talking about this indicate that Rs is essential (for at least) scientific
study of TT. It is unclear if Rs is ever very much bigger that 0 for real circuits.

jon

If people are looking for a good mathematical expression of this they can look in
any text book on SPICE under diode behavior. Working (and simple) equations are
presented.

                          
                   Intrinsic
             RS      Diode                        +-----+
                      |\ | ----> Id               |     | ----> Id
       o---/\/\/\--+--| >|--+----o          +-----|Clamp|-----+
                   |  |/ |  |               |     |     |     |
                   |        |          o----|     +-----+     |----o
                   |   | |  |               |       | |       |
                   +---| |--+               +-------| |-------+
                       | |                          | |

                     Cj + Ct                     C_comp + Ct


From bob@icx.com  Mon Dec 11 11:04:48 1995
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Date: Mon, 11 Dec 95 10:58 PST
From: bob@icx.com ( Bob Ross)
To: uunet!qdt.com!jonp@uunet.uu.net, uunet!uunet!icx.com!bob@uunet.uu.net
Subject: Re: IBIS EGG9 - Stored Charge
Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net

Jon:

The RS that appears in Spice models would be modeled inside the IBIS Clamp
tables.  The package Resistance is not shown.  RS should be small, but
is not always 0.

Bob Ross
Interconnectix, Inc.

> Do we already have a place for the Rs? The experiments I did last year when we
> were talking about this indicate that Rs is essential (for at least) scientific
> study of TT. It is unclear if Rs is ever very much bigger that 0 for real circuits.

> jon

> If people are looking for a good mathematical expression of this they can look in
> any text book on SPICE under diode behavior. Working (and simple) equations are
> presented.

>                           
>                    Intrinsic
>              RS      Diode                        +-----+
>                       |\ | ----> Id               |     | ----> Id
>        o---/\/\/\--+--| >|--+----o          +-----|Clamp|-----+
>                    |  |/ |  |               |     |     |     |
>                    |        |          o----|     +-----+     |----o
>                    |   | |  |               |       | |       |
>                    +---| |--+               +-------| |-------+
>                        | |                          | |

>                      Cj + Ct                     C_comp + Ct




From Arpad_Muranyi@ccm.fm.intel.com  Mon Dec 11 11:21:53 1995
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <Mon, 11 Dec 95 11:14:03 PST_2@ccm.hf.intel.com>
To: ibis@vhdl.org
Subject: Re[2]: IBIS EGG9 - Stored Charge


Text item: 

Didn't we say that Rs is actually included in the I-V curve?
Arpad
================================================================================
Do we already have a place for the Rs? The experiments I did last year when we
were talking about this indicate that Rs is essential (for at least) scientific
study of TT. It is unclear if Rs is ever very much bigger that 0 for
real circuits.

jon

If people are looking for a good mathematical expression of this they
can look in
any text book on SPICE under diode behavior. Working (and simple) equations are
presented.


                   Intrinsic
             RS      Diode                        +-----+
                      |\ | ----> Id               |     | ----> Id
       o---/\/\/\--+--| >|--+----o          +-----|Clamp|-----+
                   |  |/ |  |               |     |     |     |
                   |        |          o----|     +-----+     |----o
                   |   | |  |               |       | |       |
                   +---| |--+               +-------| |-------+
                       | |                          | |

                     Cj + Ct                     C_comp + Ct

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Subject: Re: IBIS EGG9 - Stored Charge
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From speters@ichips.intel.com  Mon Dec 11 13:51:31 1995
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To: ibis@vhdl.org
Subject: EGG9 and C_comp
Date: Mon, 11 Dec 1995 13:39:57 -0800
From: Stephen Peters <speters@ichips.intel.com>


Hello Bob, and others:

    In your diagram in EGG9, you show C_comp and being in
parallel with Ct (the circuit representation of transit time).

         Pad  X------------------------|  DEVICE
                      |           |    |
                      |           |    |
                     ---         ---   +------
                  Ct ---  C_comp ---         
                      |           |
                      |           |
                      -------------
                      gnd        gnd
                    

For the [TTgnd] case that is how I would draw it, but what about the 
[TTpwr] case?  I've always thought of C_comp as between the I/O
node and ground.  Could C_comp be also modeled between the pad and Vcc?
Does it make a difference (at least as far as our black box
representation goes)?  Just wondering.....

          Thanks,
          Stephen Peters
          Intel Corp.

From jonp@qdt.com  Mon Dec 11 14:48:11 1995
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Subject: [uunet!icx.com!bob: Re: IBIS EGG9 - Stored Charge]

bob asked me to forward this to the repeater

Return-Path: <uunet!icx.com!bob>
Date: Mon, 11 Dec 95 12:56 PST
From: uunet!icx.com!bob ( Bob Ross)
To: uunet!uunet!qdt.com!jonp
Subject: Re: IBIS EGG9 - Stored Charge

Jon:

Since the IBIS table for a diode will contain Rs, we then need to be concerned
about how large the Rs is before the differences become significant.  I have
assumed that Rs itself has a negligible effect for the region of operation.
However, the topology of the IBIS model is not exactly that of a Spice model,
so I would expect some difference.  Can you characterize how large the
difference is or what the different effects are?

Also, my intent was to create a current dependent capacitance model where
the current is better defined than the voltage.

Bob Ross
Interconnectix, Inc.


> Bob,

> If you are suggesting that the Rs be a part of the IV table itself and just
> restrict the current, I believe that this will not work. The Voltage that contrains
> the current is actually across the (what is now) voltage controled capacitor and
> and Rs is external to this effect. I have done tests with behavior models both ways
> and believe I can show the difference.

> jon powell
> quad design





From jonp@qdt.com  Mon Dec 11 14:48:13 1995
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Subject: [jonp: Re: IBIS EGG9 - Stored Charge]

This is my reply to bobs previous thing


Return-Path: <jonp>
Date: Mon, 11 Dec 95 14:31:53 PST
From: jonp (Jon Powell)
To: uunet!icx.com!bob
Cc: jonp@qdt.com
In-Reply-To: <m0tPFGq-000GilC@icx.com> (uunet!icx.com!bob)
Subject: Re: IBIS EGG9 - Stored Charge

Bob,

As long as we agree on the definition of TT I guess it doesn't matter if
you use a current implementation or a voltage implementation. I saw the
Rs matter with as little as 1 ohm.

I think I can dig up my simulations and show you the difference. My conclusions
at Quad were, however, that you need a unique Rs to make things work right.

I will find my simulations and re-run them and post the results in a word file.

jon


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Date: Mon, 11 Dec 95 11:17:37 PST
From: uunet!uunet!uunet!qdt.com!jonp@uunet.uu.net (Jon Powell)
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In-Reply-To: <m0tPDQo-000GilC@icx.com> (uunet!icx.com!bob)
Subject: Re: IBIS EGG9 - Stored Charge


Bob,

If you are suggesting that the Rs be a part of the IV table itself and just
restrict the current, I believe that this will not work. The Voltage that contrains
the current is actually across the (what is now) voltage controled capacitor and
and Rs is external to this effect. I have done tests with behavior models both ways
and believe I can show the difference.

jon powell
quad design


From bob@icx.com  Mon Dec 11 17:35:18 1995
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Date: Mon, 11 Dec 95 17:30 PST
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: Re:  EGG9 and C_comp

Arpad, Stephen and Jon and All:

My IBIS model diagram is in error since C_comp does go to 
ground in all cases.  However, for the purposes of Time response
simulation, the C_comp and/or Ct could go to any reference voltage.
The main idea is that both the [Gnd Clamp] and [Power Clamp] diodes may
independently contribute to stored charge effects.

The discussion that is taking place is showing the importance of 
understanding the details and assumptions of the Spice and IBIS models.
I do not think we are in technical disagreement.  I think the value and 
position of Rs or its effective value within tables can be important for 
properly handing the stored charge effects and time constants.  The
real concerns are: is the proposed approach accurate enough?, or what
alternative approach would be better - within the IBIS framework?  

Bob Ross,
Interconnectix, Inc.

> Hello Bob, and others:

>     In your diagram in EGG9, you show C_comp and being in
> parallel with Ct (the circuit representation of transit time).

>          Pad  X------------------------|  DEVICE
>                       |           |    |
>                       |           |    |
>                      ---         ---   +------
>                   Ct ---  C_comp ---         
>                       |           |
>                       |           |
>                       -------------
>                       gnd        gnd
>                     

> For the [TTgnd] case that is how I would draw it, but what about the 
> [TTpwr] case?  I've always thought of C_comp as between the I/O
> node and ground.  Could C_comp be also modeled between the pad and Vcc?
> Does it make a difference (at least as far as our black box
> representation goes)?  Just wondering.....

>           Thanks,
>           Stephen Peters
>           Intel Corp.



From kellee@alaska.nwlink.com  Tue Dec 12 14:22:57 1995
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Egg 9  (diode turn on/off)

Bob, I really like your egg.  I was the one pushing this thing
a year ago, I am very glad you have become the champion for it.

Steven, it shouldn't matter from a black box approach if the
capacitor goes to ground or power from the position of the
output pin.  It does make a difference to the currents flowing
in the power pin itself.  It seems to me it would be acceptable to
model it either way if desired.

My only major concern about the egg is:
 The equation for computing the capacitance based on the forward current
 should be included in the text before it becomes a birdy.  This way
 everyone will use the same equation, or at least know which equation
 is suggested by the IBIS group.




Have a great day...Kellee Crisafulli, HyperLynx Inc.


From Arpad_Muranyi@ccm.fm.intel.com  Thu Dec 14 08:25:24 1995
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From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-Id: <Thu, 14 Dec 95 08:17:27 PST_3@ccm.hf.intel.com>
To: ibis@vhdl.org, kellee@alaska.nwlink.com
Subject: Re: Egg 9  (diode turn on/off)


Text item: 

Hi Diode gurues,

I don't 100 % agree with Kellee with his statement that it does not matter which
way the capacitor is connected.  As he rightly stated it, it does make a 
difference to the currents flowing in the power pins.  Now, there are provisions
in IBIS that ground and power bounce are possible to simulate.  Therefore, the 
current of the capacitor should go through the appropriate GND or power pin to 
make the bounce simulation more accurate.  This is one of the reasons that we 
went through all the pain to get everyone think in Vcc relative terms for the 
pullups...  Let's not ruin it now with a simplification like this.

Arpad
================================================================================

Bob, I really like your egg.  I was the one pushing this thing
a year ago, I am very glad you have become the champion for it.

Steven, it shouldn't matter from a black box approach if the
capacitor goes to ground or power from the position of the
output pin.  It does make a difference to the currents flowing
in the power pin itself.  It seems to me it would be acceptable to
model it either way if desired.

My only major concern about the egg is:
 The equation for computing the capacitance based on the forward current
 should be included in the text before it becomes a birdy.  This way
 everyone will use the same equation, or at least know which equation
 is suggested by the IBIS group.




Have a great day...Kellee Crisafulli, HyperLynx Inc.

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Subject: Egg 9  (diode turn on/off)
From: Kellee Crisafulli <kellee@hyperlynx.com>
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From speters@ichips.intel.com  Fri Dec 15 11:38:56 1995
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To: ibis@vhdl.org, si-list@silab.Eng.Sun.com
Subject: I/O Model opening at Intel
Date: Fri, 15 Dec 1995 11:30:55 -0800
From: Stephen Peters <speters@ichips.intel.com>




JOB OPENING:

Intel has an opening for a Senior I/O Modeling Engineer.  Basic job
responsibilities include:

  Working with both the I/O buffer designers and board level simulation teams
to create and validate I/O buffer models for Intel's flagship microprocessors.

  Planning and executing customer releases of both I/O buffer and package
modeling information.

  Identifying Intel's future modeling needs (both I/O buffer and packaging)
and, by working with industry groups such as the IBIS Open Forum, ensure
that modeling solutions are made available to our customers.


REQUIREMENTS:
   The candidate must have a strong background in high speed board level
logic design, including transmission line analysis of PC board traces,
modeling of packages thru the use of field solver software, and use of 
board level timing and signal integrity analysis tools.  The candidate 
must also poses strong analytical skills. Familiarity with Unix, HSPICE, 
and some programming experience (PERL, C, etc.) is a definite plus.  The 
individual must be a self-starter, be self directed (comfortable working
with little or no direct supervision), and have a proven record of managing
small projects to completion.  BSEE/CE or equivalent required.


     Please direct all inquires/resumes to Stephen Peters at 
speters@ichips.intel.com.  You may also FAX your resume to (503) 264-4210.

              Best Regards,
              Stephen Peters
              Intel Corp.


From mbs@eos.ncsu.edu  Fri Dec 15 13:01:08 1995
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From: mbs@eos.ncsu.edu
Message-Id: <199512152053.PAA00799@c11142-343dan.ece.ncsu.edu>
To: ibis@vhdl.org
Subject: Model updates.
Date: Fri, 15 Dec 95 15:53:16 EST

 
National has updated some of their IBIS models. Details follow.
 
ct2525m.ibs  cgs        03-10-95  2.0  1.1  1to8 Min. Skew Clk Drvr (TTL
Compa)
ct2525n.ibs  cgs        03-10-95  2.0  1.1  1to8 Min. Skew Clk Drvr (TTL
Compa)
ct2527v.ibs  cgs        03-23-95  2.0  1.1  1to8 Min. Skew Clk Drvr (TTL
Compa)
 
More models are being added to the library and  afull model listing will be
distributed shortly.
 
Michael Steer
IBIS librarian
~
~

From kellee@alaska.nwlink.com  Mon Dec 18 11:57:13 1995
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: New version of Visual IBIS Editor V0.96

Hello in IBIS land..

  There is a new version of Visual IBIS Editor for anyone interested.
  Some new features have been added per user requests.
   - R,L,C for pin, c_comp, Voltage range are now shown in views
   - input clamp curves are now displayed in views
   - a few minor bugs were fixed.
   - a button to access the IBIS 2.1 spec was added.

  Enjoy...

  To download a free copy:  http://www.hyperlynx.com

  Have a happy holiday season.

  
Have a great day...Kellee Crisafulli, HyperLynx Inc.


From ventham@quantic.mb.ca  Mon Dec 18 20:21:06 1995
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From: ventham@quantic.mb.ca (Mike Ventham)
Message-Id: <9512190327.AA08394@quantic.mb.ca>
Subject: See a young IBIS
To: ibis@vhdl.org
Date: Mon, 18 Dec 95 21:27:51 CST
X-Mailer: ELM [version 2.3 PL11]

Here is a picture I found in Kodak's sample digital images. Can't
remember the URL but if anyone wants to know I can dig it up again.

It is of an immature IBIS taken on Kodak film (what else!). Check with
them regarding copyright before using.

You will need to uudecode it, then view it using a JPEG viewer.

Regards

Mike
+======================================================================+
| Mike Ventham - Vice President Engineering, Quantic Laboratories Inc, |
| 12th Floor, 191 Lombard Ave, Winnipeg, Manitoba, Canada R3B 0X1      |
| Tel: (204) 942 4000 Fax: (204) 957 1158 Email: ventham@quantic.mb.ca |
+======================================================================+
----------------------- Cut here --------------------------------------
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MIX(;8D3S/921W0WZ;!L ,@J+WR?I%%IW;1NVJ%\SIMCR5B7%6J!NM6'&2!*G
MLGD:J+-T#GY)S/\ "^2D'!PBE:V4DPV(*3>%!O!Y^:D//E3AC+.?:@VQH>Z+
A[=JKV1NTB>THSV6ACO\ X/X+S=>B:^?/GRO.U!JN?__9
 
end

From bob@icx.com  Tue Dec 19 09:34:20 1995
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Date: Tue, 19 Dec 95 09:29 PST
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: IBIS MINUTES 12/15/95

 DATE:    December 19, 1995
 
 SUBJECT: 12/15/95 EIA IBIS Open Forum Meeting Minutes
 
 VOTING MEMBERS:
 AT&T Global Info Solutions     Dave Moxley*
 Cadence Design                 Sandeep Khanna, C. Kumar*
 Contec CAE, Ltd.               Dileep Divekar*
 HyperLynx                      Kellee Crisafulli
 IBM                            Jay Diepenbrock
 INCASES                        Werner Rissiek, Olaf Rethmeier
 Intel Corporation              Stephen Peters*, Will Hobbs, Arpad Muranyi*,
                                Derrick Duehren
 Interconnectix, Inc.           Bob Ross*
 Meta-Software                  Les Spruiell, Mei Wong, You-Pang Wei, 
                                John Sliney
 Motorola                       Ron Werner
 National Semiconductor         Syed Huq*, Atul Agarwal, Cheng-Yang Kao
 NEC                            Hiroshi Matsumoto, Eldar Yazbashevz
 Quad Design                    Jon Powell*, Chris Myles, Chris Rokusek*
 Quantic Labs                   Mike Ventham
 Tanner Research, Inc.          Scott Wedge, Ed Miller, Peter Parrish
 Texas Instruments              Roger Cline, Ben Andresen, Sri Jandhyadla*,
                                Tareq Shahwan*
 Thomson-CSF/SCTF               Jean LeBrun
 UniCAD Canada Ltd.             Stephen Lum
 VLSI Technology                Dick Ulmer*, Sung Oh
 Zuken-Redac                    John Berrie
 
 OTHER PARTICIPANTS:
 AMP                            Hank Herrmann*
 ARPA                           Randy Harr
 Anacad                         Steffen Rochel
 Ansoft                         Henri Maramis
 Atmel Corporation              Dan Terry
 Cadlab                         Ralf Bruning
 CFI                            Ron Christopher, Don Cottrell
 Digital Equipment Corp.        Barry Katz
 EIA                            Patti Rusher*
 High Design Technology         Michael Smith, Dr. Ing. Cosso
 Hewlett Packard                Tom Langdorf, Karl Kachigan, Henry Wu
 Integrated Silicon Systems     Eric Bracken
 Intergraph                     Ian Dodd, David Wiens, Walter Katz
 IntuSoft                       Charles Hymowitz
 LSI Logic Corp.                Satish Pratadneni
 Mentor Graphics                Ravender Goyal, Greg Doyle
 Micron Technology              Brian Johnson                       
 MicroSim                       Arthur Wong
 North Carolina State U.        Steve Lipa, Michael Steer
 OptEM Engineering, Inc.        Benny Leveille, Ken Ehn
 Pacific Numerix                Paul K. U. Wang
 Symmetry                       Martin Walker
 Synopsys, Logic Modeling G.    Bill Lattin
 Univ. of Illinois, Urbana      Raj Mittra 
 Zeelan Technology              George Opsahl, Hiro Moriyasu
 (Independent)                  Bob Ward

 In the list above, attendees at the meeting are indicated by *.
 
 Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as 
 follows:

      Date       Bridge Number    Reservation #    Passcode  
      1/12/96    (916) 356-9200   2-41860          1918954

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each open forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.
 
 -------------------------------- MINUTES -------------------------------------
 
 INTRODUCTIONS
 Jon Powell chaired the meeting.
 
 Sri Jandhyadla and Tareq Shahwan joined us from Texas Instruments, Sherman
 Texas.  They have been providing IBIS models directly to customers on a
 per request basis including models for JTAG devices and bus drivers. Models
 provided include components in the LVT and ABT series.  They are working
 on GTL models.  There is still discussion on how best to distribute IBIS
 models.
 

 EIA MEMBERSHIP AND TREASURER'S REPORT
 The membership is the same and the treasury has been reduced by a payment
 for parser code development.  We estimate $7,000 to $8,000.


 MINUTES REPORT, MISC.
 The December, 1995 Minutes National Semiconductor Web Site has been corrected
 to read:
      http://www.natsemi.com

 Two additional points by Hank Herrmann on the BIRD31 discussion are added
 to the minutes.  (1) Connector models will be discussed at the Face to Face
 meeting, although specific items of discussion have not been identified.
 (2) "not-fully-populated busses" could be modeled by separate models
 rather than by partial models as the BIRD suggests.  The minutes will
 contain the more detailed discussion which Hank has sent to the reflector.


 MISCELLANY/ANNOUNCEMENTS
 None.


 PRESS AND WEB PAGE UPDATES
 "Meeting Timing and Signal Quality Requirements" in Printed Circuit Design, 
 December 1995 by Rod Strange and Peter Suaris mentions IBIS.

 The web page discussion documented below occured at this time.


 NEW MODELS
 Syed Huq reports that some updated versions of National models have been
 submitted to Michael Steer.

 Arpad Murayni reports that information concerning the Intel 82439HX has
 been sent to Michael Steer concerning IBIS model availability under NDA.


 OPENS FOR NEW ISSUES
 Egg9 - Transit Time Modeling.


 EIA-656 ANSI RATIFICATION
 Patti Rusher reported that on December 13, 1995, IBIS has been formally
 ratified by ANSI as ANSI/EIA-656.

 A motion was made by Bob Ross and seconded by Jon Powell to forward
 ANSI/EIA-656 to IEC (International Electrotechnical Commission) working
 group TC-93 on Design Automation as the first step toward international
 ratification.  Motion was approved by unanimous vote.

 Patti will forward the document at a January meeting.  She expects the
 standardization process may take up to 3 years.


 EIA/IBIS 1996 MEMBERSHIP
 Patti Rusher will send out EIA/IBIS 1996 membership renewal forms in
 early January instead of December.
 

 EIA WEB UPDATE
 Syed Huq has been working with Patti Rusher and Steven Malone on Web page
 details.  They are making excellent progress and will report on the 
 reflector when the Web page is up.  All documents are approved.

 Contents of the Web page include:

     Intel EDN article
     Links to vhdl.org for IBIS information including
        Models
        IBIS Specifications
        Roster
        FAQ's (Frequently Asked Questions)
     Links to Member Companies Home Pages.

 Syed needs to know which companies are member companies.  Jon Powell has
 logo information and Logos from 12 companies.  Since HP nor NCSU are not
 official members, their logos cannot be used.  TI is planning to submit
 a logo, (and sign the EIA/IBIS permission letter form set by Patti Rusher),
 but at this time does not need a link to the company home page.  Links
 can be provided later.  Jon Powell reported that the following companies
 have supplied logos: Interconnectix, ATT-GIS, National Semiconductor
 Quantic, Contec, Hyperlynx, Incases, Intel, Unicad, Quad Design, and
 Cadence.  


 FACE TO FACE MEETING
 Syed Huq has made arrangements for National to host the meeting on Monday,
 January 29 before SuperCon96.  So far he has 15 confirmations.  Lunch and
 snacks will be provided along with the meeting place.  For those who are
 staying over, plan on a celebration dinner together.  Syed will send another
 reminder giving more details on location. 

 TI indicated that they may send one or two people.  Syed has made some
 other semiconductor vendor contacts.  While details will be firmed up
 later, Intel and National are expected to participate on the model
 development/model validation topic.

 Other topics with details to be firmed up later are expected to cover
 connector modeling, stored charge modeling, feedback mechanisms, TTL
 measurements, adding more timing specifications, hysteresis, bus keeper
 circuits, etc.

 At Design SuperCon96 on January 30 - February 2, there will be at least two
 presentations by National Semiconductor and one by Quad Design which will
 refer to IBIS.


 MODEL USAGE TRACKING
 This issue will be dropped until there is further proposals by vendors.
 National's Model listing on their Web site links directly to vhdl.org so
 that only a single library is managed.  Jon Powell found a Web site which
 appeared to register participation.  He will forward details to Syed Huq.


 GOLDEN PARSER UPDATE
 Several errors have been reported by Chris Rokusek to Bob Ross.  One of
 them will lend itself to a specification clarification BIRD since the
 ibischk2 is functioning correctly.

 These problems will be sent to Paul Munsey for an update expected early
 next year.

 AR - Anyone finding Parser bugs submit them to Bob Ross.  Include a test
 case, if possible.


 SPICE TO IBIS VERSION 2.1
 Bob Ross reported that a crash bug found by Altera has been sent to NCSU
 on s2ibis-v2.091 (a Beta version). 


 WINIBIS (NEW DISCUSSION)
 The Hyperlynx supplied utility was discussed.  Bob Ross reported success
 in using it on Windows 3.1.  Dave Moxley and others reported problems
 bringing it up on Windows NT.  It gives a similar error to Windows 3.1 when
 the latest Win32S is NOT loaded.   The action item is to contact Kellee
 Chrisafulli directly.


 EGG8 - PHYSICAL PACKAGE DISCUSSION
 No discussion.


 BIRD31 - CONNECTOR MODELS
 Some discussion occured and Bob Ross still plans to submit some examples
 to the reflector.  Bob indicated that the required keyword [Description]
 for the expanded [Define Package Model] extension could be used to 
 place any edge rate or bandwidth limitation requested by Hank Herrmann.
 Jon Powell raised the question regarding what EDA vendors are supposed
 to do with this information.


 BIRD28.3+  PACKAGE MODEL ENHANCEMENT
 C. Kumar has sent a proposal to Stephen Peters for early review before
 sending it out as a BIRD.


 EGG6 - TTL and CMOS
 Jon Powell reported that there exist counter-examples for all proposed
 methods to distinguish the technologies from the data itself.  However,
 even though the transition mechanisms are different, he is thinking that
 the test load to get the dynamic parameters are a more important factor.
 So no change in the Specification may be needed.  If he discovers some
 test load set that works well, he will supply the recommendations.


 EGG9 - HANDLING STORED CHARGE
 Bob Ross discussed EGG9 and reflector comments.  He agrees with Jon Powell
 that RS is important.  Jon indicated that it may not be a factor if RS 
 is less than 4 ohms.  This needs to be validated.  The issue is that the
 transit time capacitance is modeled in parallel with the intrinsic diode,
 to the time constant remains constant.  When the IBIS Clamp table is used,
 the effective RS is also included.  This makes the time constant vary 
 with forward diode currents, and may cause different effects.  Since
 the IBIS Clamp table can represent a clamping circuit instead of just one
 diode or transistor, the notion of an effective TT is put forth.  It may be
 derived indirectly - supply the TT that matches the desired performance,
 as opposed to trying to use the TT in a Spice model or obtained directly.

 For background, Bob indicated that other approaches are possible for this
 problem.  (1) A complete simplified verion of the diode equation used by
 Spice could be added (the set of parameters would be specified to describe
 this diode) and the Clamp tables would be difference currents from the
 measured IV characteristics.  (2) Or a best fit diode equation could
 be extracted form the tables to estimate RS and intrinsic diode, although
 experience indicates that this does not always give a reasonable estimate.

 This will be a topic for the face to face discussion and is open for more
 reflector discussion.


 HYSTERESIS AND INPUT RISE TIME SPECIFICATION (NEW DISCUSSION)
 Arpad Muranyi discussed IBIS USERS' GROUP reflector questions from John
 Fitzpatrick.  One question dealt with whether IBIS supports hysteresis.
 Bob Ross indicated that hysteresis could be supported by putting in the
 smaller threshold for Vinh and the larger one for Vinl.  This may work
 for timing limits.  One question is whether the actual threshold values
 or the specification limits should be used.  The data itself may cause
 a too conservative timing estimate for a hysteresis input designed to 
 tighten up the timing tolerances.  So there is expected to be more
 discussion on this subject at the Face to Face Meeting.

 Another topic concerned a Tinr and Tinf input rise and fall time 
 specification.  This would be similar to the threshold limits Vinh and
 Vinl that are specification limits for the [Model].  A few devices do
 have input rise and fall specifications.  For some cases, if the input
 is too slow the device can be destroyed.  In other cases, it may be
 needed to assure compliance with other timing specification.  This also
 can be a topic for the Face to Face Meeting.


 DOUBLE COUNTING OF PULLUP AND PULLDOWN RESISTORS (NEW DISCUSSION)
 Arpad Muranyi recounted his experience and caution that one must understand
 the Clamping tables when modeling devices with internal pullup or pulldown
 resistors to avoid double counting the resistors.  Bob Ross indicated
 that it is permissible to supply data outside of the (minimum) ranges
 mandated by the Specification.  The minimum ranges are appropriate for 
 most devices where the clamps will converge to nearly 0ma at the Vcc points.
 With an internal pullup, for example the [Power Clamp] table would
 be extended all the way to -Vcc to accurate model its effect.  Arpad
 has correctly taken this into account in the models he has supplied and
 cautions others to be alert to double counting problems if they have
 internal pullup and pulldown elements.  Dick Ulmer indicated that the
 values may be negligible (e.g., 50k) for many cases.  However, there can
 be cases where the elements are significant.


 NEXT MEETING:
 It is set on Friday, January 12, 1996, and the Face-to-Face Meeting is on
 Monday, January 29, 1996.

 ==============================================================================
                                       NOTES
 
 IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210
             will_hobbs@ccm.jf.intel.com
             Server Chipset System Validation Manager, Intel Corp.
             2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA
 
 VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259
             jonp@qdt.com
             1385 Del Norte Rd., Camarillo, CA 93010
 
 SECRETARY:  Bob Ross (503) 603-2523, fax (503) 639-3469
             bob@icx.com
             10220 SW Nimbus Ave, K4, Portland, OR 97223
 
 The following email addresses are used:

   ibis-request@vhdl.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org)
       or both.  State your request.

   ibis-info@vhdl.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@vhdl.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.

   ibis-users@vhdl.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via ftp anonymous, "guest" login from 
 telnet or dial-in (415-335-0110), or send an email request to the automatic 
 archive server, archive@vhdl.org.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================
 



From kellee@alaska.nwlink.com  Wed Dec 20 02:51:13 1995
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Received: (from kellee@localhost) by alaska.nwlink.com (8.6.12/8.6.9) id CAA19676; Wed, 20 Dec 1995 02:44:38 -0800
Date: Wed, 20 Dec 1995 02:44:38 -0800
Message-Id: <199512201044.CAA19676@alaska.nwlink.com>
X-Sender: kellee@mail.nwlink.com
X-Mailer: Windows Eudora Pro Version 2.1.2
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Visual IBIS Editor V0.97 (long path name bug fixed)

Hello IBIS land,

  I have fixed the bug Karl found.  The IBIS validation
checker in the Visual IBIS Editor would crash if the 
file path was extremely long.  I made the mistake of missing
one of the DOS/UNIX flags in the IBIS open forum parser code.
This caused one of the path parsing routines to use the wrong slash.

Version 0.97 is available at http://www.hyperlynx.com


Let me know if you find any other problems...


Best holiday wishes to all and to all a good night .....





  
Have a great day...Kellee Crisafulli, HyperLynx Inc.


From kellee@alaska.nwlink.com  Wed Dec 20 13:47:26 1995
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Dave Moxley's email address at AT&T

Sorry to broadcast this to everyone.

Does anyone know Dave Moxley's email address?
I would like to reach him regarding a problem he
reported with Visual IBIS Editor.

Have a great day...Kellee Crisafulli, HyperLynx Inc.


From kellee@alaska.nwlink.com  Tue Dec 26 17:13:00 1995
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To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: ACER chip set models

Hi all,

  Some good and some bad news.  The good news is ACER has IBIS models
for many of their IC's.  The bad news is I don't know who to contact
at ACER and at least one of their models has a minor bug.
ACER fell into the Power_clamp table polarity problem that most new IBIS
file creators hit.  The signs on all the currents in the table are
wrong.  HyperLynx tools detect this and correct the problem.  Other
vendor's products may not correct this problem so it is important to
get the word to ACER before they create any more models with the currents
backward.  Does anyone know who to contact at ACER, or is anyone at ACER
reading IBIS mail?

I was not able to find out which ACER model was causing the problem.




Have a great day...Kellee Crisafulli, HyperLynx Inc.


