From bob@icx.com Wed Jul 5 13:25:57 1995 Return-Path: Received: from icx.com ([204.119.8.12]) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11874; Wed, 5 Jul 95 13:25:57 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Jul 95 13:17 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Jul 95 13:20 PDT Message-Id: Date: Wed, 5 Jul 95 13:20 PDT From: bob@icx.com ( Bob Ross) To: 75123.3477@compuserve.com Subject: Re: BIRD29.1 questions Cc: 73053.721@compuserve.com, bob@icx.com, ibis@vhdl.org Ron: I have given your questions some thought because the bandwidth B in IBIS Version 2.1 and in BIRD29.1 are not explicitly limited. I plan to issue BIRD29.2 to put in the limits explicitly. With respect to the case where there is no circle-back, there is an implicit limit by construction that B < N. The parser issues an error if B >= N. When B = N - 1 the Banded-matrix entries are the same as the Full-matrix entries. When circle-back occurs, we have a case where the Banded-matrix can have redundant terms and actually contain more entries than the Full-matrix specification. Your example illustrates such a case. Your example (when corrected) would have 12 entries, but the Full-matrix specification would have 10 entries. Since redundant entries create ambiguity in the data base, I think that they should be flagged as an error. All other forms of the matrix specification avoid redundant entries by definition. The test to avoid redundant entries is: IF the Banded-matrix is a circle-back banded matrix AND B > int((N - 1) / 2) THEN issue an error In your example, N = 4, and B = 2. An error should be issued since 2 > 1. In this way, you do not need to test to see entries 31 = 13 and 24 = 42. We should not allow the opportunity to specify twice the same value. So, with respect to your specific questions, [1] Your are correct - row 4 is in error because row 3 determined that this is a circle-back banded matrix and row 4 does not contain B+1 entries. [2] Rather than checking for individual values, also issue an Error based on the B > int((N - 1) /2) test above. The message can be of the form ... Bandwidth > (calculate the limit value) not permitted when entering circle-back coupling form of Banded_matrices. This could be a row 3 error since it may be ambiguous what form was really intended. [3] The alternative style of coupling without circle-back is equally valid, so no warning should be issued. Bob Ross, Interconnectix, Inc. > Date: 03 Jul 95 23:22:14 EDT > From: "Ronald M. Neville" <75123.3477@compuserve.com> > To: Bob Ross > Cc: Paul Munsey <73053.721@compuserve.com> > Subject: BIRD29.1 questions > Hi Bob, > I have received a copy of BIRD29.1, handling "wrap-around" or "circle-back" > coupling in banded matrices. > Before I jump into implementation, an example and a few questions: > [1] "All rows will contain B + 1 entries." (when we are describing a > a circle-back matrix...) So, the following 4X4 matrix contains an error: > [Inductance Matrix] Banded_matrix > [Bandwidth] 2 > [Row] 1 > 0.01 0.12 0.37 | this row ok, "11", "12", and "13" > [Row] 2 > 3.21 5.89 2.22 | this row ok, "22", "23", and "24" > [Row] 3 > 2.81 4.69 3.22 | this row ok, "33", "34", and "31" > [Row] 4 > 7.91 5.89 | this row is incomplete, "42" is missing > Row 3, where the column exceeds the rows, is where the Parser determines that > this matrix is a circle-back banded matrix type matrix. > [2] In the matrix above, "13" is listed as 0.37 and "31" is listed as 3.22 . > Should this be flagged as an error? (Is coupling commutative?) > [3] Should an old-style, non-circleback banded matrix generate a warning from > the parser? > thanx, ron From bob@icx.com Wed Jul 5 13:32:17 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11928; Wed, 5 Jul 95 13:32:17 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Jul 95 13:25 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 5 Jul 95 13:27 PDT Message-Id: Date: Wed, 5 Jul 95 13:27 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: BIRD29.2 Cc: 73053.721@compuserve.com, 75123.3477@compuserve.com IBIS Members: BIRD29.1 was approved at the June 30, 1995 forum. BIRD29.2 is issued to add some bandwidth limits to comply with a practical IBISCHK2 implementation. In one case the limit is already implied by construction and has already been implemented in IBISCHK2. In the other case, the limit is set to avoid the ambiguity associated with allowing the same entry to be specified twice (and possibly differently). The BIRD29.2 changes are designated by four "|**" lines. Bob Ross, Interconnectix, Inc. ***************************************************************************** ***************************************************************************** Buffer Issue Resolution Document (BIRD) BIRD ID#: 29.2 ISSUE TITLE: Banded_matrix Extension REQUESTOR: Bob Ross, Interconnectix, Inc. DATE SUBMITTED: 26 May 1995 DATE REVISED: 5 June 1995 DATE ACCEPTED BY IBIS OPEN FORUM: BIRD29.1: 30 June 1995 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: In the Package Model description in IBIS Version 2.1, the Banded_matrix format needs to be extended to remove a technical limitation. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The relevant portion of the original Specification is given along with edited remarks or deletion comments are designate by "|*" lines. BIRD29.2 changes are designate by "|**" lines to add upper bound bandwidth limits. | Banded_matrix | | A Banded_matrix is one whose entries are guaranteed to be zero if they | are farther away from the main diagonal than a certain distance, known | as the "bandwidth." Let the matrix size be N, and let the bandwidth | be B. An entry [I,J] of the matrix is zero if: | | | I - J | > B | | where |.| denotes the absolute value. | | The bandwidth for a Banded_matrix must be specified using the [Bandwidth] | keyword: | |============================================================================== | Keyword: [Bandwidth] | Required: Yes (for Banded_matrix matrices only) | Description: Indicates the bandwidth of the matrix. The bandwidth field | must be a nonnegative integer. This keyword must occur after | the [Resistance Matrix], etc. keywords, and before the matrix | data is given. | Usage Rules: |------------------------------------------------------------------------------ [Bandwidth] 10 | |============================================================================== | Specify the banded matrix one row at a time, starting with row 1 and | working up to higher rows. Mark each row with the [Row] keyword, as | above. As before, symmetry is exploited: do not provide entries below the | main diagonal. | | The first row only needs to specify the entries [1,1] through [1,1+B] since | any other entries are guaranteed to be zero. The second row will need to | specify the entries [2,2] through [2, 2+B], and so on. In general, for row M | the entries [M,M] through [M,M+B] are given. | | Unlike the Full_matrix, each successive row will typically have the same | number of entries, except for the last few rows. When M + B finally exceeds | the size of the matrix N, then the number of entries in each row starts to | decrease; the last row (row N) has only 1 entry. | | As in the Full_matrix, if all the entries for a particular row do not fit | into a single 80-character line, the entries can be broken across several | lines. | | It is possible to use a bandwidth of 0 to specify a diagonal matrix (a matrix | with no coupling terms.) This is sometimes useful for resistance matrices. | |**** Reword the Above Text with Changes Shown: ********************* | Banded_matrix | | A Banded_matrix is one whose entries are guaranteed to be zero if they | are farther away from the main diagonal than a certain distance, known |* as the "bandwidth." Let the matrix size be N x M, and let the bandwidth | be B. An entry [I,J] of the matrix is zero if: | | | I - J | > B | | where |.| denotes the absolute value. |* |* The Banded_matrix is used to specify the coupling effects up to B pins |* on either side. Two variations are supported. One allows for the coupling |* to circle back on itself. This is technically a simple form of a bordered |* block diagonal matrix. However, its data can be completely specified in |* in terms of a Banded_matrix for an N x M matrix consisting of N rows |* and M = N + B columns. The second variation is just in terms of an N x N |* matrix where no circle back coupling needs to be specified. |* | The bandwidth for a Banded_matrix must be specified using the [Bandwidth] | keyword: | |============================================================================== | Keyword: [Bandwidth] | Required: Yes (for Banded_matrix matrices only) | Description: Indicates the bandwidth of the matrix. The bandwidth field | must be a nonnegative integer. This keyword must occur after | the [Resistance Matrix], etc. keywords, and before the matrix | data is given. | Usage Rules: |------------------------------------------------------------------------------ [Bandwidth] 10 | |============================================================================== | Specify the banded matrix one row at a time, starting with row 1 and | working up to higher rows. Mark each row with the [Row] keyword, as | above. As before, symmetry is exploited: do not provide entries below the | main diagonal. | |* For case where coupling can circle back on itself, consider a matrix of |* N pins organized into N rows 1 ... N and M columms 1 ... N, 1 ... B. | The first row only needs to specify the entries [1,1] through [1,1+B] since |* all other entries are guaranteed to be zero. The second row will need to |* specify the entries [2,2] through [2,2+B], and so on. For row K |* the entries [K,K] through [K,K+B] are given when K + B is less than or |* equal to the size of the matrix N. When K + B exceeds N, the entries in the |* last columns 1 ... B specify the coupling to the first rows. For row K, the |* entries [K,K] ... [K,N] [K,1] ... [K,R] are given where R = |** mod(K + B - 1, N) + 1. All rows will contain B + 1 entries. To avoid |** redundant entries, the bandwidth is limited to B <= int((N - 1) / 2). |* |* For the case where coupling does not circle back on itself, the process is |* modified. Only N columns need to be considered. When K + B finally exceeds |* the size of the matrix N, the number of entries in each row starts to |** decrease; the last row (row N) has only 1 entry. This construction |** constrains the bandwidth to B < N. | | As in the Full_matrix, if all the entries for a particular row do not fit | into a single 80-character line, the entries can be broken across several | lines. | | It is possible to use a bandwidth of 0 to specify a diagonal matrix (a matrix | with no coupling terms.) This is sometimes useful for resistance matrices. | |**************************************************************************** | | Sparse_matrix | | A Sparse_matrix is expected to consist mostly of zero-valued entries, except | for a few nonzeros. Unlike the Banded_matrix, there is no restriction on | where the nonzero entries can occur. This feature is useful in certain | situations, such as for Pin Grid Arrays (PGAs.) | | As usual, symmetry can be exploited to reduce the amount of data by | eliminating from the matrix any entries below the main diagonal. | | An N x N Sparse_matrix is specified one row at a time, starting with | row 1 and continuing down to row N. Each new row is marked with [Row] | keyword, as in the other matrix formats. | | Data for the entries of a row is given in a slightly different format, | however. For the entry [I, J] of a row, it is necessary to explicitly | list the name of pin J before the value of the entry is given. This | specification serves to indicate to the parser where the entry is put into | the matrix. | | The proper location is not otherwise obvious because of the lack of | restrictions on where nonzeros can occur. Each (Index, Value) pair is | listed upon a separate line. An example follows. Suppose that row 10 | has nonzero entries [10,10], [10,11], [10,15], and [10,25]. The | following row data would be provided: | [Row] 10 | Index Value 10 5.7e-9 11 1.1e-9 15 1.1e-9 25 1.1e-9 | | Note that each of the column indices listed for any row must be | greater than or equal to the row index, because they always come from | the upper half of the matrix. When alphanumeric pin names are used, | special care must be taken to ensure that the ordering defined in the | [Pin Numbers] section is observed. | | Also, note that it is again necessarily the case that the N'th | row of an N x N matrix has just a single entry (the diagonal entry.) | |**** Reword the Above Sentence: ******************************* | |* With this convention, please note that the N'th row of an |* N x N matrix has just a single entry (the diagonal entry). | |**************************************************************** |============================================================================== ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION In order to reduce the size of the symmetrical matricies, there are several statements describing data entries only ON or ABOVE the main diagonal. That was the intention of the banded-matrix description. However the format prevented entering the coupling between the last pins and the first pins. A simple 4-pin example with a bandwidth of 1 illustrates the problem. The "data" entries are the two digit subscripts of the matrix entries and are shown using quote marks "". Version 2.1 does not allow defining the coupling between pin 4 and 1: [Inductance Matrix] Banded_matrix [Bandwidth] 1 [Row] 1 "11" "12" [Row] 2 "22" "23" [Row] 3 "33" "34" [Row] 4 "44" One possible solution is to augment the Banded_matrix format for the first rows by the entries that could not be entered in the last rows. This would preserve the ABOVE the diagonal convention. [Inductance Matrix] Banded_matrix [Bandwidth] 1 [Row] 1 "11" "12" "14" [Row] 2 "22" "23" [Row] 3 "33" "34" [Row] 4 "44" However, the solution proposed here is to keep the number of columns the same and to wrap around the entries for the last rows as needed. Technically the entries are BELOW the main diagonal. The "41" entry would really be entered as "14" in the reduced upper-triangle matrix data structure. [Inductance Matrix] Banded_matrix [Bandwidth] 1 [Row] 1 "11" "12" [Row] 2 "22" "23" [Row] 3 "33" "34" [Row] 4 "44" "41" BIRD29.1 provides another way looking at the formating. The "41" entry can now be viewed as an upper-triangle entry of the original matrix augmented by repeating columns 1 ... B. Using symmetry, this format gives all of the information needed to describe all coupling by the B adjacent pins. Commentors on BIRD29 discussed nomenclature (banded, bandwidth, bordered block diagonal matrix) and proposed other terms. One concern was whether to retain the existing definition and add another term (such as Augmented_matrix) to handle the wrap around situation. The revised data entry format can still be referred to as banded when the first N columns are augmented by repeating existing columns 1 ... B. For compatibility reasons, support of the existing Banded_matrix format was desireable. The proposed new format was only a slight variation on the existing format, so it did not seem appropriate to introduce new nomenclature for the change. The solution proposed in BIRD29.1 is to accept simutaneously both format options. The intent is allow the technically robust functionality within the existing nomenclature, and to allow the technically limited descriptions be supported where wrap around coupling is of no concern. This works because the terms missing in the existing format are zero in the more robust format. The old format should be phased out rather than endorsed by separate notation which must be supported indefinitely because it would allow technically incomplete package model libraries. This is a compromise position between those who would like the original format definition deleted and those who would like to see both formats supported using different terminology. The parser definition will be overloaded, but for this situation, this is not a significant complication. This problem does not occur in the Sparse_matrix format. So the restriction text has a minor change in that portion of the Specification. BIRD29.2 is issued to explicitly put in bandwidth limits. This is in response to an IBISCHK2 question raised by Ron Neville regarding how to treat redundant Banded_matrix entries when the entries are different. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION From slipa@eos.ncsu.edu Thu Jul 6 17:41:46 1995 Return-Path: Received: from mw7.ece.ncsu.edu (c11049-336dan.ece.ncsu.edu) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24269; Thu, 6 Jul 95 17:41:46 PDT Received: by mw7.ece.ncsu.edu (5.65/Eos/C-U-09Sep93) id AA17452; Thu, 6 Jul 1995 20:35:24 -0400 From: slipa@eos.ncsu.edu Message-Id: <9507070035.AA17452@mw7.ece.ncsu.edu> To: ibis@vhdl.org Cc: slipa@eos.ncsu.edu Subject: New models added to IBIS library at vhdl.org. Date: Thu, 06 Jul 95 20:35:23 EDT Two new IBIS models have been added to the IBIS library: Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- dp8440vj dram_ctl 062895 1.0 1.1 Prog. DRAM Controller/Driver dp8441vj dram_ctl 062895 1.0 1.1 Prog. DRAM Controller/Driver -------------------------------------------------------------------------------- These are in /pub.ibis/models/national/dram_ctl. -------------------------------------------------------------------------------- Currently the IBIS library contains the following models: National Semiconductor Corporation - Advanced Systems & Interface Product Group IBIS Files on vhdl.org as of 7/06/95 Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- ds26c31.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Drvr ds26c32.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Recvr lct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr lct2524n.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524n.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr c2525m.ibs cgs 04-05-85 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2525m.ibs cgs 04-05-85 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2525m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) c2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2527v.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2528m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2528n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2528v.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2529v.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) 2534v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Commercial) 2535v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) 2536v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) b303m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr 701v.ibs cgs 04-05-95 1.0 1.1 Low Skew PLL 1to8 CMOS Clk Drvr 2537v.ibs cgs 04-17-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) pc87306.ibs superI_O 05-25-95 1.0 1.1 pc87306vul(SuperI/O) FDC,KBC,RTC,UARTs,IR,PP and IDE int g612mea.ibs gtl 6/06/95 1.0 1.1 18-Bit CMOS GTL SSOP 56 Lead g612mtd.ibs gtl 6/06/95 1.0 1.1 18-Bit CMOS GTL TSSOP 56 Lead gp612mea.ibs gtl 6/06/95 1.0 1.1 18-Bit CMOS GTL SSOP 56 Lead gp612mtd.ibs gtl 6/06/95 1.0 1.1 18-Bit CMOS GTL TSSOP 56 Lead dp8440vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver dp8441vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver Intel Corporation IBIS Files on vhdl.org as of 7/06/95 Part/File vhdl.org alpha rev. rev. IBIS name Directory name date level ver. Notes -------------------------------------------------------------------------------- 82425ex.ibs chipset PSC 06-17-94 R0.93 V1.1 Aries chipset 82426ex.ibs chipset IB 06-17-94 R0.93 V1.1 Aries chipset 82374eb.ibs chipset ESC 05-13-94 R2.11 V1.1 PCI-EISA Bridge 82374sb.ibs chipset ESC 06-17-94 R0.93 V1.1 PCI-EISA Bridge 82375eb.ibs chipset PCEB 05-13-94 R2.11 V1.1 PCI-EISA Bridge 82375sb.ibs chipset PCEB 06-17-94 R0.93 V1.1 PCI-EISA Bridge 82378ib.ibs chipset SIO 05-13-94 R2.11 V1.1 PCI-ISA Bridge 82378zb.ibs chipset SIOZ 06-17-94 R0.93 V1.1 PCI-ISA Bridge 82433lx.ibs chipset LBX 05-13-94 R2.11 V1.1 Mercury chipset 82434lx.ibs chipset PCMC 05-13-94 R2.11 V1.1 Mercury chipset 82433nx.ibs chipset LBX 06-17-94 R0.94 V1.1 Neptune chipset 82434nx.ibs chipset PCMC 06-17-94 R0.94 V1.1 Neptune chipset 82423tx.ibs chipset DPU 05-13-94 R2.11 V1.1 Saturn chipset 82424zx.ibs chipset CDC 05-13-94 R2.11 V1.1 Saturn chipset dx4pga.ibs cpu DX4 05-04-94 R2.0 V1.1 IntelDX4(TM) uP pp66sem.ibs pentium PP66 10-16-94 R3.0 V1.1 66MHz Pentium* pp100sem.ibs pentium PP100 10-15-94 R3.0 V1.1 100MHz Pentium* * Translated from an Intel Simplified Electrical Model. From bob@icx.com Thu Jul 6 17:51:51 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24337; Thu, 6 Jul 95 17:51:51 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Jul 95 17:45 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 6 Jul 95 17:47 PDT Message-Id: Date: Thu, 6 Jul 95 17:47 PDT From: bob@icx.com ( Bob Ross) To: 73053.721@compuserve.com, 75123.3477@compuserve.com, ibis@vhdl.org Subject: IBISCHK2 TESTMATRIX.7 AND SAMPLE Hello Fellow IBISans, Paul and Ron: I checked IBISCHK2, version 7 and found the following has been fixed: The crash problems that I reported previously all seem to have been fixed both for DOS and UNIX systems. The "Sparse_matrix" choices now accepts alpha_numeric indicies properly. As a result, IBISCHK2 now accepts correctly formatted Version 2.1 files, or gracefully reports an error. As part of the expanded project, the following items are now added to the list. A revised pkg1.ibs at the end contains tests for these items. (1) The "Banded_matrix" works correctly as defined in IBIS Version 2.1. However, BIRD29.1 and pending BIRD29.2 gave an additional format option which now needs to be implemented. (2) In the Sparse_matrix test, there are some details are given or implied in the IBIS Version 2.1 that should be checked: (a) The Specification states that the [Row] entries have to be ordered according to the [Pin Numbers] list. This check is already done for Banded_matrix and Full_matrix specifications and the same check should be done for Sparse_matrix formats. This test then will trap repeated rows, missing rows, and out of order rows. [Row] entries must exist for all [Pin Numbers], even for Sparse_matrix formats. (b) The indicies for each row are constrained by the Specification to be equal or "larger" than the row number, i.e., the upper triangle indicies. This should be checked. You already issue an error if they are repeated. The specification does not state that the indicies should follow any order. However, checking that they exist as one of the upper-triangle entries and also that they are not repeated will be sufficient. (c) One final constraint implied, but not specifically stated is that each [Row] must contain a self coupled index and entry. It is only stated that the last [Row] must contain only one entry, and this implies that all the rows must contain the self coupled entry. So the final check is that there exist an index equal to the [Row] number. I cannot think of any case where the self coupled entry would not exist based on the definitions of the Matrix entries. (3) Finally, an additional test on each [Component]'s [Pin] list is needed if it has a [Package Model] keyword. The [Define Package Model] section contains a [Pin Numbers] list that must match the entries of the [Pin] list both in content and quantity. The order can be different. This added comparison test should be done for each [Component] even if they refer to the same [Package Model] because the order and content of each [Component] [Pin] list can differ. At this point the IBISCHK2 works very well, but these additional checks complete the first order Specification checking of the [Define Package Model] section and its relationship to the [Pin] keyword. Great Job Ron and Paul! Bob Ross Interconnectix, Inc. A TEST MATRIX FOR IBIS VERSION 2g (Beta 7) DATE: 10/31/94, 12/2/94, 1/26/95, 3/4/95, 3/8/95 5/25/95 7/6/95 SPECIFICATION TESTED PASS Comments/who tested --------------------------------------+-----+-----------------------------+ Test that the parser only | | | accepts 1.0, 1.1, 2.0, 2.1 as | | | valid arguments to the [IBIS Ver] | yes | Stephen Peters | keyword. | | | | | | Tab character warning | yes | Bob Ross | | | | --------------------------------------+-----+-----------------------------+ Scaling Factors: | | | | | | Test that the parser recognizes | | | "T", "G" and "f" as valid scaling | yes | No indication either way | factors. | | Bob Ross - this is proper | | | operation | Test that the parser does not | | | recognize "t", "g" and "F" as | yes | No indication either way | Valid scaling factors. | | Bob Ross - proper operation | | | | --------------------------------------+-----+-----------------------------+ Keywords rules: | | | | | | Test that the parser recognizes | | | the [GND clamp] and [PWR clamp] | yes | Stephen Peters | keywords without the underscore. | | | Test Underscore rule for 3-word | yes | Bob Ross | Keyoreds - all 4 cases. | | | | | | Test that the parser issues an | | | error if a keyword does not begin | yes | Stephen Peters | in column 1. | | | | | | Test case insensitivity of all | | | keywords, reserved words and | yes | Pin mapping keyword does not| sub-parameters | | recognize "power" and "gnd" | | | Bob Ross - OK, should be | | | "pulldown_ref", "pullup_ref,| | | "gnd_clamp_ref", and | | | "power_clamp_ref" | | | | --------------------------------------+-----+-----------------------------+ Comments and Notes: | | | | | | Test that the parser does not | | | accept "+" and "-" as valid | yes | Stephen Peters | comment characters. | | | | | | Test that the parser recognizes | yes | Stephen Peters | the [Copyright] keyword. | | | | | | | | | --------------------------------------+-----+-----------------------------+ Component keyword related: | | | | | | Test that the parser issues an | | | error if the [Component] keyword | yes | Stephen Peters | has no component name after it. | | | | | | Test that the parser issues a warning | | | if the component name contains blanks | yes | Stephen Peters | | | | Test the component name length | | | rules: | | | parser accepts name < 40 characters | yes | Stephen Peters | parser accepts name = 40 characters | yes | " | parser fails if name > 40 characters | yes | " | | | | Test that the parser issues an | | | error if the [Manufacture] keyword | yes | Stephen Peters | has no Manufactures name after it. | | | | | | Test the Manufactures name length | | | rules: | | | parser accepts name < 40 characters | yes | Stephen Peters | parser accepts name = 40 characters | yes | Stephen Peters | parser fails if name > 40 characters | yes | Stephen Peters | | | | Test that an .ibs file can contain | yes | Bob Ross | more than one [Component] keyword | | | and component description. | | | | | | --------------------------------------+-----+-----------------------------+ Pin keyword related: | | | | | | Test that the parser recognizes | yes | Stephen Peters | the [Pin] keyword. | | | | | | Test that the parser issues a | | | error when every model_name does | yes | Bob Ross | not have a corresponding model | | (I don't see the problem) | defined. | | | | | | Test the "3 column or 6 column" | | | rule. | yes | Stephen Peters | | | | Test that the parser issues an error | | | when non-numeric data is in the pin | yes | Stephen Peters | data columns | | | | | | Test that [Pin] entries agree with | NO | NEW TEST | [Pin Numbers] entries if the [Package | | | Model] keyword is used. | | | | | | --------------------------------------+-----+-----------------------------+ Package Model related: | | | | | | Test that the parser recognizes | yes | Stephen Peters | the [Package Model] keyword. | | | | | | Test the package model name length | yes | Bob Ross | rules | | Fixed: | parser accepts name < 40 characters | yes | Name is taken as a DOS file | parser accepts name = 40 characters | yes | name and not as argument to | parser fails if name > 40 characters | yes | the [Define Package Model] | | | keyword | Verify that the parser issues an | | | error if it cannot find: | | | | | | 1. A [Define Package Model] keyword | | | that has the same argument as the | yes | Bob Ross | [Package Model] keyword or | | | | | | 2. An external .pkg file that has | yes | Bob Ross | a [Define Package Model] keyword | | | with has the same argument as the | | | [Package Model] keyword. | | | | | | 3. Test that the parser recognizes | | | all keywords in the package model | | | description and operation below: | | | (1) Error if Missing | | | (2) Error if Duplicate | | | (3) Error if Wrong Argument | | | [Define Package Model] 1,2,3 | yes | Bob Ross | [Manufacturer] 1,2,3 | yes | | [OEM] 1,2,3 | yes | | [Description] 1,2,3 | yes | | [Number of Pins] 1,2,3 | yes | fixed | [Pin Numbers] 1,2,3 | yes | | [Model Data] 1,2 | yes | | [Resistance Matrix] 2,3 | yes | | [Inductance Matrix] 1,2,3 | yes | | [Capacitance Matrix] 1,2,3 | yes | | [Bandwidth] 1,2,3 | yes | fixed | [Row] 1,2,3-fails | NO | (problems below) | [End Model Data] 1,2 | yes | Bob Ross | [End Package Data] 1,2 | yes | " | | | | | | | 4. Full_matrix Tests | | Bob Ross | [Bandwidth] error test | yes | | [Row] number entry (match pin) | yes | fixed | [Row] number entry (repeated) | yes | fixed | [Row] number entry (all rows entered) | yes | fixed | [Row] number entry (ascending order) | yes | | [Row] format (upper triange matrix) | yes | fixed | [Row] format (excessive data) | yes | | [Row] format (missing data) | yes | fixed | | | | 5. Banded_matrix Tests | | Bob Ross | [Bandwidth] req'd test | yes | fixed | [Bandwidth] argument req'd | yes | | [Bandwidth] argument value | yes | | [Row] number entry (match pin) | yes | fixed | [Row] number entry (repeated) | yes | fixed | [Row] number entry (all rows entered) | yes | | [Row] number entry (ascending order) | yes | | [Row] format (excessive data) | yes | | [Row] format (missing data) | yes | fixed | [Row] format non-circular coupling | yes | | [Row] format circular coupling (cc) | NO | BIRD29.1 | [Row] format bandwidth limits (cc) | NO | pending BIRD29.2 | | | | 6. Sparse_matrix Tests | | Bob Ross | [Bandwidth] error test | yes | | [Row] number entry (match pin) | yes | fixed | [Row] number entry (repeated) | NO | STILL PROBLEM | [Row] number entry (all rows entered) | NO | NEW ITEM | [Row] number entry (ascending order) | NO | NEW ITEM | [Row] index match | yes | | [Row] index upper-triangle | NO | NEW ITEM | [Row] index repeated | yes | | [Row] index (alpha string) | yes | Fixed | [Row] format (excessive data) | yes | fixed | [Row] format (missing data) | yes | fixed | | | | --------------------------------------+-----+-----------------------------+ Pin Mapping keyword related: | | | | | | Test that the parser recognizes | yes | Stephen Peters | the [Pin Mapping] keyword. | | | | | | Test that the parser issues an | | | error if every pin listed in the | yes | Bob Ross - fixed | [Pin] keyword does not have an | | | entry in the [Pin Mapping] table | | | | | | Test the "3 column or 5 column" | yes | Stephen Peters | rule. | | | | | | Test that NC is a valid entry | | | in a column. | yes | Stephen Peters | | | | Test that each unique entry label | | | must connect to at least one pin | | | whose model name is POWER or GND | yes | Stephen Peters | | | | Test that NA is NOT a valid | | | column entry | yes | Bob Ross | | | | --------------------------------------+-----+-----------------------------+ Diff Pin keyword related: | | | | | | Test that the parser recognizes | yes | Bob Ross | the [Diff Pin] keyword. | | | | | | Test that the parser recognizes | yes | Bob Ross | the 5 associated sub-parameters | | | | | | Test the "4 column or 6 column" | yes | Bob Ross | rule. | | | | | | Test that NC is NOT a valid | yes | Bob Ross | column entry. | | | | | | Test that NA is a valid column | yes | Bob Ross | entry. | | | | | | Reports error for duplicate pin | yes | Bob Ross | numbers. | | | | | | --------------------------------------+-----+-----------------------------+ [Model] keyword: | | | | | | Test that the parser recognizes | yes | Bob Ross | the [Model] keyword. | | | | | | Test that the parser recognizes | | | each Model_type: | | | Input | yes | Bob Ross | Output | yes | | I/O | yes | | 3-state | yes | | Open_drain | yes | | I/O_open_drain | yes | | Open_sink | yes | | I/O_open_sink | yes | | Open_source | yes | | I/O_open_source | yes | | Input_ECL | yes | | Output_ECL | yes | | I/O_ECL | yes | | Terminator | yes | | | | | Test that the parser issues | | | a warning if an input type model | yes | Stephen Peters | does not have Vinh or Vinl defined. | | | For All I/O_* cases. | yes | Bob Ross | | | | | | | Test that the parser issues an | | | error if the Model_type or C_comp | yes | Stephen Peters | sub-parameters are missing. | | | | | | Test that the parser accepts a | | | [Model] description with only the | | | Model_type and C_comp sub-params | yes | Stephen Peters | defined. | | | | | | Test that the parser allows NA in | | | the min and max columns only of the | yes | Stephen Peters | C_Comp sub-parameter. | | | | | | Test that the parser allows only | | | Non-inverting and Inverting as | yes | Stephen Peters | choices for the Polarity sub-param | | | | | | Test that the parser allows only | | | Active-High and Active-Low as | yes | Stephen Peters | choices for the Enable sub-param | | | | | | Test that the parser recognizes | | | the Vmeas, Cref, Rref and Vref | yes | Stephen Peters | sub-parameters. | | | | | | --------------------------------------+-----+-----------------------------+ Temperature keyword related: | | | | | | Test that the parser recognizes | yes | Stephen Peters | the [Temperature Range] keyword | | | | | | --------------------------------------+-----+-----------------------------+ Power supply rail related: | | | | | | Test that the parser recognizes | | | the supply rail keywords | | | [Voltage Range] | yes | Stephen Peters | [Pullup Reference] | " | | [Pulldown Reference] | " | | [POWER Clamp Reference] | " | | [GND Clamp Reference] | " | | | | | Test that the parser issues an | | | error if the [Voltage Range] | | | keyword is absent and all four of | | | the other supply rail keywords are | yes | Stephen Peters | NOT present. | | | | | | --------------------------------------+-----+-----------------------------+ I/V table related: | | | | | | Test that the parser recognizes | | | the [Pullup], [Pulldown], [GND | yes | Stephen Peters | Clamp] and [Power Clamp] keywords. | | | | | | Test that the parser issues an | yes | Bob Ross | error if all three columns are | | | not included | | | | | | Test that NA is accepted in the | yes | Bob Ross | min and max columns. | | | | | | Test that the parser issues an | yes | Bob Ross | error if a column contains over | | | 100 points. | | | | | | Test that the parser issues an | | | error if a table contains less | yes | Stephen Peters | than two points. | | | | | | Test that the parser issues a | yes | Bob Ross | warning if non-monotonic data | | | is found. | | | Test for One Warning per Column | yes | Bob Ross | | | | --------------------------------------+-----+-----------------------------+ Terminator related: | | | | | | Test that the parser recognizes | yes | Bob Ross | the [Rgnd], [Rpower], [Rac] and | | | [Cac] keywords. | | | | | | Test if [Rac], then [Cac] req'd. | yes | Bob Ross | | | | Test if [Cac], then [Rac] req'd. | yes | Bob Ross | | | | Test if parser issues an error with | | | above keywords AND Model_type is NOT | yes | Bob Ross | Terminator. | | | | | | Test that parser DOES NOT issue an | yes | Bob Ross | error if above models are NOT | | | defined. (Clamps or no components | | | can also be "Terminators") | | | | | | Test that the parser issues an | yes | Bob Ross | error if all three columns are | | | not included | | | | | | Test that NA is accepted in the | yes | Bob Ross | min and max columns. | | | | | | --------------------------------------+-----+-----------------------------+ Ramp keyword related: | | | | | | Test that the parser recognizes | | | the [Ramp] keyword and the | yes | Stephen Peters | dv/dt_r and dv/dt_f sub-parameters. | | | | | | Test that the parser recognizes | yes | Stephen Peters | the R_load sub-parameter. | | | | | | Test that the R_load sub-parameter | yes | Stephen Peters | is optional. | | | | | | --------------------------------------+-----+-----------------------------+ Waveform Related: | | | | | | Test that the parser recognizes | | | the [Rising Waveform] and [Falling | yes | Bob Ross | Waveform] keywords. | | | | | | Test that the parser recognizes | | | the sub-parameters: | | | R_fixture | yes | Bob Ross | V_fixture | yes | | V_fixture_max | yes | | V_fixture_min | yes | | C_fixture | yes | | L_fixture | yes | | R_dut | yes | | L_dut | yes | | C_dut | yes | | | | | Test that the parser issues an | | | error if the R_fixture and | yes | Bob Ross | V_fixture sub-parameters are not | | | present. | | | | | | Test that the parser issues an | | | error if a column contains over | yes | Bob Ross | 100 points. | | | | | | Test that the parser issues an | | | error if a table contains less | yes | Bob Ross | than two points. | | | | | | Test NA permitted in typical column | yes | Bob Ross | --------------------------------------+-----+-----------------------------+ |*************************************************************** | [IBIS Ver] 2.1 [File Name] pkg1.ibs [File Rev] 0.1 [Date] July 6, 1995 [Source] Interconnectix Inc. [Disclaimer] Provided for modeling purposes only. Results are not guaranteed. | |*************************************************************** | [Component] PACKAGE-TEST [Manufacturer] Test File [Package] | variable typ min max R_pkg 0.0m NA NA L_pkg 0.0nH NA NA C_pkg 0.0pF NA NA | |*************************************************************** | [Pin] signal_name model_name R_pin L_pin C_pin A1 P_1 NC 2 P_2 NC 5 P_3 NC 4 P_4 NC | A different order is OK. | 3 P_5 NC | This missing pin should produce | an error. [Package Model] test [Define Package Model] test [Manufacturer] anyone [OEM] this file shows [Description] some failed test cases [Number of Pins] 5 [Pin Numbers] A1 2 3 4 5 [Model Data] [Inductance Matrix] Banded_matrix [Bandwidth] 2 [Row] A1 .01 .01 .01 [Row] 2 .01 .01 .01 [Row] 3 .01 .01 .01 [Row] 4 .01 .01 .01 [Row] 5 .01 .01 .01 | Correct circle back test. Two errors are issued | based on non-circle back format [Capacitance Matrix] Banded_matrix [Bandwidth] 3 [Row] A1 .01 .01 .01 .01 [Row] 2 .01 .01 .01 .01 | Circle back test with bandwidth too large. [Row] 3 | An error should be issued. .01 .01 .01 .01 | Three errors are issued based on the non- [Row] 4 | circle back test. .01 .01 .01 .01 [Row] 5 .01 .01 .01 .01 [Resistance Matrix] Sparse_matrix [Row] A1 A1 .01 2 .01 [Row] 2 3 .01 | There is no column 2 entry for self coupling. A1 .01 | This entry lower triangle entry should not be accepted. [Row] 2 | This row is repeated, Row 3 is missing. 5 .01 | This out of order entry is OK. 2 .01 | This entry would not be accepted for [Row] 3. 4 .01 [Row] 4 4 .01 5 .01 [Row] 5 5 .01 5 .01 | Duplicate entries are correctly flagged as an error. [End Model Data] [End Package Model] | [End] From medtron!relay.medtronic.com!hsin-huei.lin@uunet.uu.net Fri Jul 7 12:53:48 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03757; Fri, 7 Jul 95 12:53:48 PDT Received: from uucp6.UU.NET by relay3.UU.NET with SMTP id QQyxjz12556; Fri, 7 Jul 1995 15:47:41 -0400 Received: from medtron.UUCP by uucp6.UU.NET with UUCP/RMAIL ; Fri, 7 Jul 1995 15:47:27 -0400 Received: from medtron.medtronic.COM by relay.medtronic.com with SMTP id AA18030 (5.65c/IDA-1.4.4 for ); Fri, 7 Jul 1995 14:46:15 -0500 Received: from mspeos.cis.corp.medtronic.COM (eos.cis.corp.medtronic.COM) by medtron.medtronic.COM with SMTP id AA18026 (5.65c/IDA-1.4.4 for ); Fri, 7 Jul 1995 14:46:13 -0500 Received: from eos.cis.corp.medtronic.COM by mspeos.cis.corp.medtronic.COM (5.x/SMI-SVR4) id AA26646; Fri, 7 Jul 1995 14:45:57 -0500 Received: from MSPEOS-Message_Server by eos.cis.corp.medtronic.COM with Novell_GroupWise; Fri, 07 Jul 1995 14:45:57 -0500 Message-Id: X-Mailer: Novell GroupWise 4.1 Date: Fri, 07 Jul 1995 14:47:13 -0500 From: Hsin-Huei Lin To: ibis@vhdl.org Subject: Battery operated device Hi, I have a questio about IBIS modeling, the device I am trying to model is battery operated and as time goes by the voltage level will drop. Does anyone know whether IBIS can accomodate this and how? Thank you for your response. Hsin-Huei Lin Medtronic, Inc. From fred_floresca@powertalk.apple.com Fri Jul 7 13:54:18 1995 Return-Path: Received: from alink-gw.apple.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04050; Fri, 7 Jul 95 13:54:18 PDT Received: from federal-excess.apple.com by alink-gw.apple.com with SMTP (921113.SGI.UNSUPPORTED_PROTOTYPE/7-Oct-1993-eef) id AA16500; Fri, 7 Jul 95 13:47:44 -0700 for ibis@vhdl.org Received: from powertalk.apple.com by federal-excess.apple.com (5.0/1-Nov-1994-eef) id AA06522; Fri, 7 Jul 1995 13:46:15 +0800 for ibis@vhdl.org Message-Id: Date: 7 Jul 1995 20:49:39 -0700 From: "Fred Floresca" Subject: Spice to IBIS conversion To: "ibis@vhdl.org" Cc: "David Reha" X-Mailer: Mail*Link SMTP 3.0.2 b1 Content-Length: 525 Greetings All, Help!!! I just downloaded "s2ibis" (version 11) and I can't get it to work!! I'm running the executable on a Sparcstation 2 (Sun OS 4.1.3) and a Solbourne Series 5 (Sun OS 4.1B). I ran the sparc executable on a spice model and it just hung (had to Control-C to get out). I also tried recompiling the source using gcc and ended up with the same results. Would anyone have any suggestions on what I can do to get s2ibis to work? Any help would be highly appreciated. Fred Floresca Apple Computer, Inc. From bob@icx.com Fri Jul 7 13:59:32 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04056; Fri, 7 Jul 95 13:59:32 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 7 Jul 95 13:53 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 7 Jul 95 13:55 PDT Message-Id: Date: Fri, 7 Jul 95 13:55 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS 6/30/95 MEETING MINUTES DATE: June 30, 1995 SUBJECT: 6/30/95 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS: AT&T Global Info Solutions Dave Moxley Cadence Design Sandeep Khanna, C. Kumar* Contec Dileep Divekar HyperLynx Kellee Crisafulli INCASES Werner Rissiek, Olaf Rethmeier Intel Corporation Stephen Peters*, Will Hobbs*, Arpad Muranyi*, Derrick Duehren Interconnectix, Inc. Bob Ross* Meta-Software Les Spruiell, Mei Wong, You-Pang Wei, John Sliney Motorola Ron Werner National Semiconductor Syed Huq*, Atul Agarwal, Cheng-Yang Kao NEC Hiroshi Matsumoto Quad Design Jon Powell Quantic Labs Mike Ventham Texas Instruments Bob Ward* Thomson-CSF/SCTF Jean LeBrun UniCAD Canada Ltd. Stephen Lum Zuken-Redac John Berrie OTHER PARTICIPANTS: ARPA Randy Harr Anacad Steffen Rochel Ansoft Henri Maramis Atmel Corporation Dan Terry Cadlab Ralf Bruning Digital Equipment Corp. Barry Katz EIA Patti Rusher* High Design Technology Michael Smith, Dr. Ing. Cosso Hewlett Packard Tom Langdorf, Karl Kachigan, Henry Wu IBM Jay Diepenbrock Integrated Silicon Systems Eric Bracken Intergraph Ian Dodd, David Wiens, Walter Katz IntuSoft Charles Hymowitz LSI Logic Corp. Satish Pratadneni Mentor Graphics Ravender Goyal, Greg Doyle MicroSim Arthur Wong North Carolina State U. Steve Lipa, Michael Steer OptEM Engineering, Inc. Benny Leveille, Ken Ehn Pacific Numerix Paul K. U. Wang Symmetry Martin Walker Synopsys, Logic Modeling G. Bill Lattin VLSI Dick Ulmer*, Sung Ho* Zeelan Technology George Opsahl, Hiro Moriyasu In the list above, attendees at the meeting are indicated by *. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 7/21/95 (916) 356-9999 1-3147 7221442 8/11/95 (916) 356-9999 1-3150 8492193 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS, ANNOUNCEMENTS Dick Ulmer and Sung Oh of VLSI introduced themselves. They come from the PC Products Division and are finishing Version 2.1 IBIS models for PC chip sets. VLSI is in the process of becoming a Member of EIA/IBIS. MINUTES, TREASURER'S REPORT, MISC. Minutes of 6/15/95 meeting were approved. Patti Rusher did not have an update of the treasurer's report, but there have been two additional parser purchases. Will Hobbs reported that JEDEC packaging committee is interested in IBIS and particularly the package model extension activity of BIRD28.1. Stephen Peters has been invited to talk to the September JEDEC meeting. Bob Ward gave a brief overview of IBIS to the TI JEDEC representatives. There appears to be an opportunity for cooperation and coordination. OPENS FOR NEW ISSUES Pin programmable buffer strengths from Arpad Muranyi PRESS UPDATES IBIS press release Electronic News (May 29, 1995), pg 36. IBIS mentioned in product anouncements by Cadence in Electronic News (June 5, 1995), and by Savantage in EDN (June 8, 1995) and Electronic Engineering Times (June 5, 1995). NEW MODELS Syed Huq reported that National has submitted two more Version 1.1 models for DRAM controllers to vhdl.org Model providers are interested in knowning who uses the models. Syed will pursue this when Michael Steer returns from vacation. Bob Ward feels that it is possible to put directory monitors for statistics. The intent is that eacy company which submit models can get monthly statistics on who accesses their models. These statistics would be available only to the model provider, since as Will Hobbs pointed out, company may not want their model usage monitored (product plans) exposed to others. AR - Syed contacts Michael Steer on developing a tracking system with the System Administrator of vhdl.org. EIA IBIS MEMBERSHIP UPDATE We currently have 17 members with VLSI expected to join soon. Nine positive responses (with no comments) to the ballot have been received. EIA World Wide Web is running. Syed Huq will work with Patti to provide an IBIS home page and also access to public IBIS information that reside outside of participating company firewalls. The home page contents have to be approved by the IBIS Committee, and must also pass EIA legal review. AR - Syed will update the reflector on IBIS home page progress. Patti will be coordinating the EDA booth at DAC96 in Las Vegas. She would like to see standards participation. She has asked for free floor space. At DAC95, CFI and EIA/EDIF payed $15K and several others put in less. She expects the cost to go down next year. A workstation with demos for IBIS would be nice. Several knowledgeable IBIS people would be needed for booth duty. GOLDEN PARSER UPDATE Will has redistributed the corrected Version 7 ibischk2 disks as Beta 7.1 We have not had a chance to give feedback yet since it was sent out originally with ramp.c missing. This is expected to be the final release. However, some additional changes based on BIRD29.1 and on completeness of the parser may necessitate additional work. S2IBIS 2.1 Kumar will make progress reports. A while ago Michael Steer had requested ibischk2 header files for code compatibility. We agreed to provide these. AR - Will Hobbs send Michael all *.h files. Update - DONE AR - Kumar provide an update next week on s2ibis 2.1 progress. COOKBOOK AND OVERVIEW UPDATE Will mentioned that this would be a good Summer project since there is much interest in IBIS Version 2.1 BIRD27 NEW KEYWORD FOR DIFFERENTIAL I/O Bob Ward will submit BIRD27.1 using comments from Bob Ross and will this will be discussed at the next meeting. This change is intended for Version 3.0. AR - Bob Ward submit BIRD27.1 BIRD28.1 PACKAGE MODEL EXTENSION Stephen Peters has just sent BIRD28.1 with changes including revised syntax and removal of the [Units] keyword. Stephen retained the [Model Data] and [End Model Data] syntax. The key difference is that the groups of pins that are intended to couple one another need to be of the same length. The matricies used to describe the coupling are described in the BIRD and are consistent with those produced by field solvers. Stephen raised the question if VCC and GND pins should be handled differently with no coupling, and the consensus was that this was not necessary nor proper. Coupling the rails should be included in the format so simulators can handle the effects. As a reality check, Stephen will post a PQFP picture and corresponding IBIS description to illustrate the application of BIRD28.1 and perhaps generate further comment. The example may be in text or Word format. AR - Stephen Peters submit an example. BIRD29.1, BANDED MATRICES As written, Version 2.1 did not permit wrap-around coupling through the banded method. At DAC95 and on the reflector, we discussed a wrap-around mechanixm by extending the bands diagonally beyond the square perimeter of the matrix far enough to match the length of the diagonal at each fringe paralleling the diagonal. Bird29.1 was approved by vote. Thjs bird would apply to the EIA IBIS Version 2.1 and is regarded as an editorial clarification and slight expansion of functionality (keeping the existing functionality). AR - Bob Ross sends to EIA this BIRD as a comment to the EIA IBIS ballot from the committee. Update: DONE AR - Will Hobbs and Bob Ross, commmunicate this change to Paul Munsey and Ron Neville as an enhancement to the ibischk2 parser project. Update: DONE PIN PROGRAMMABLE BUFFER STRENGTHS Arpad Muranyi asked whether the current IBIS syntax could include specifying multiple buffer strengths for a particular pin, and the concensus was no. Bob Ward had raised this issue at the DAC Summit meeting in February, 1995. The ibis_chk and ibischk2 utilities would not handle several models on the same [Pin] line. The current method is to supply several models and supply the appropriate comments so that the user can enter the correct model in the [Pin] table. Another solution is to have multiple [Component] files having permutations of model combinations. This would work if only a few selections are needed. Buffer strength selection exists in several devices, so the need is real. It may be nice to have an IFDEF method to dynamically select buffer levels. AR - Arpad Muranyi write up a proposal (EGG) and submit to the reflector to generate discussion. NEXT MEETING: It is set on Friday, July 21, 1995. Will Hobbs will be gone, so Jon Powell or Bob Ross will moderate. AR - Will Hobbs contact Jon Powell. Update: DONE. Jon Powell will moderate. ============================================================================== NOTES IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210 Will_Hobbs@ccm.jf.intel.com Modeling Manager, Intel Corp. 2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259 JonP@qdt.com 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Bob Ross (503) 603-2523, fax (503) 639-3469 Bob@icx.com 10220 SW Nimbus Ave, K4, Portland, OR 97223 To become a voting member of the EIA IBIS Open Forum, send email to ibis-info@vhdl.org for instructions. If you want to join the e-mail reflector (ibis@vhdl.org), send e-mail to the IBIS secretary at ibis-request@vhdl.org. Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an email request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From slipa@eos.ncsu.edu Fri Jul 7 16:10:45 1995 Return-Path: Received: from mw7.ece.ncsu.edu (c11049-336dan.ece.ncsu.edu) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04722; Fri, 7 Jul 95 16:10:45 PDT Received: by mw7.ece.ncsu.edu (5.65/Eos/C-U-09Sep93) id AA20655; Fri, 7 Jul 1995 19:04:24 -0400 From: slipa@eos.ncsu.edu Message-Id: <9507072304.AA20655@mw7.ece.ncsu.edu> To: ibis@vhdl.org Cc: slipa@eos.ncsu.edu Subject: IBIS Library housekeeping Date: Fri, 07 Jul 95 19:04:24 EDT I have been doing a little housekeeping in the IBIS library. Here is an update of the current contents of the library: National Semiconductor Corporation - Advanced Systems & Interface Product Group IBIS Files on vhdl.org as of 7/07/95 Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- ds26c31.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Drvr ds26c32.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Recvr lct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524n.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr c2525m.ibs cgs 04-05-85 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2525m.ibs cgs 04-05-85 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2525m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) c2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2527v.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2528m.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2528n.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2528v.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2529v.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) 2534v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Commercial) 2535v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) 2536v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) b303m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr 701v.ibs cgs 04-05-95 1.0 1.1 Low Skew PLL 1to8 CMOS Clk Drvr 2537v.ibs cgs 04-17-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) pc87306.ibs superI_O 05-25-95 1.0 1.1 pc87306vul(SuperI/O) g612mea.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL SSOP 56 Lead g612mtd.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL TSSOP 56 Lead gp612mea.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL SSOP 56 Lead gp612mtd.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL TSSOP 56 Lead dp8440vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver dp8441vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver Intel Corporation IBIS Files on vhdl.org as of 7/07/95 Part/File vhdl.org alpha rev. rev. IBIS name Directory name date level ver. Notes -------------------------------------------------------------------------------- 82425ex.ibs chipset PSC 06-17-94 R0.93 V1.1 Aries chipset 82426ex.ibs chipset IB 06-17-94 R0.93 V1.1 Aries chipset 82374eb.ibs chipset ESC 05-13-94 R2.11 V1.1 PCI-EISA Bridge 82374sb.ibs chipset ESC 06-17-94 R0.93 V1.1 PCI-EISA Bridge 82375eb.ibs chipset PCEB 05-13-94 R2.11 V1.1 PCI-EISA Bridge 82375sb.ibs chipset PCEB 06-17-94 R0.93 V1.1 PCI-EISA Bridge 82378ib.ibs chipset SIO 05-13-94 R2.11 V1.1 PCI-ISA Bridge 82378zb.ibs chipset SIOZ 06-17-94 R0.93 V1.1 PCI-ISA Bridge 82433lx.ibs chipset LBX 05-13-94 R2.11 V1.1 Mercury chipset 82434lx.ibs chipset PCMC 05-13-94 R2.11 V1.1 Mercury chipset 82433nx.ibs chipset LBX 06-17-94 R0.94 V1.1 Neptune chipset 82434nx.ibs chipset PCMC 06-17-94 R0.94 V1.1 Neptune chipset 82423tx.ibs chipset DPU 05-13-94 R2.11 V1.1 Saturn chipset 82424zx.ibs chipset CDC 05-13-94 R2.11 V1.1 Saturn chipset dx4pga.ibs cpu DX4 05-04-94 R2.0 V1.1 IntelDX4(TM) uP pp66sem.ibs pentium PP66 10-16-94 R3.0 V1.1 66MHz Pentium* pp100sem.ibs pentium PP100 10-15-94 R3.0 V1.1 100MHz Pentium* * Translated from an Intel Simplified Electrical Model. From bob@icx.com Fri Jul 7 17:28:28 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05747; Fri, 7 Jul 95 17:28:28 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 7 Jul 95 17:21 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 7 Jul 95 17:24 PDT Message-Id: Date: Fri, 7 Jul 95 17:24 PDT From: bob@icx.com ( Bob Ross) To: hsin-huei.lin@medtronic.com, ibis@vhdl.org Subject: Re: Battery operated device Hsin-Huei Lin: Here is a brief response to your question. For most devices the IBIS models have [Voltage Range] for each [Model]. There are often "typ" and "min" tables. The "min" table represents a slow, weak corner and is always based on a minimum supply level. So the IBIS "typ" data can be used for starting operation, and the "min" data for worst case, low battery operation. If the "min" data is not defined, the low battery operation can be approximated by changing the [Voltage Range] "typ" value to a low voltage value in the IBIS model. The VI curves are relative to the defined voltages, so changing the voltage automatically shifts the tables but does not change the shape as an approximation. Bob Ross, Interconnectix, Inc. > Date: Fri, 07 Jul 1995 14:47:13 -0500 > From: Hsin-Huei Lin > To: ibis@vhdl.org > Subject: Battery operated device > Status: RO > Hi, > I have a questio about IBIS modeling, the device I am trying to > model is battery operated and as time goes by the voltage level will drop. > Does anyone know whether IBIS can accomodate this and how? Thank you for > your response. > Hsin-Huei Lin > Medtronic, Inc. From Arpad_Muranyi@ccm.fm.intel.com Mon Jul 10 08:41:52 1995 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02609; Mon, 10 Jul 95 08:41:52 PDT Received: from relay.jf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #7) id m0sVKrd-000UjTC; Mon, 10 Jul 95 08:35 PDT Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0sVKrd-000txZC; Mon, 10 Jul 95 08:35 PDT Received: by ccm.hf.intel.com (ccmgate 3.2 #2) Mon, 10 Jul 95 08:35:17 PDT Date: Mon, 10 Jul 95 08:26:00 PDT From: Arpad Muranyi Message-Id: To: ibis@vhdl.org, medtron!relay.medtronic.com!hsin-huei.lin@uunet.uu.net Subject: Re: Battery operated device Text item: Hsin, You could do this with the typ. min. max. method in IBIS. Define your max values at a fully charged battery voltage and the min values at the completely discharged battery voltage. The keyword [Voltage Range] might be used for this purpose. Arpad Muranyi Intel Corporation --------------------------------------------------------------------------- Hi, I have a questio about IBIS modeling, the device I am trying to model is battery operated and as time goes by the voltage level will drop. Does anyone know whether IBIS can accomodate this and how? Thank you for your response. Hsin-Huei Lin Medtronic, Inc. Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: Battery operated device To: ibis@vhdl.org From: Hsin-Huei Lin Date: Fri, 07 Jul 1995 14:47:13 -0500 X-Mailer: Novell GroupWise 4.1 Message-Id: Received: from MSPEOS-Message_Server by eos.cis.corp.medtronic.COM with Novell_GroupWise; Fri, 07 Jul 1995 14:45:57 -0500 Received: from eos.cis.corp.medtronic.COM by mspeos.cis.corp.medtronic.COM (5.x/ SMI-SVR4) id AA26646; Fri, 7 Jul 1995 14:45:57 -0500 Received: from mspeos.cis.corp.medtronic.COM (eos.cis.corp.medtronic.COM) by med tron.medtronic.COM with SMTP id AA18026 (5.65c/IDA-1.4.4 for ); Fri, 7 Jul 1995 14:46:13 -0500 Received: from medtron.medtronic.COM by relay.medtronic.com with SMTP id AA18030 (5.65c/IDA-1.4.4 for ); Fri, 7 Jul 1995 14:46:15 -0500 Received: from medtron.UUCP by uucp6.UU.NET with UUCP/RMAIL ; Fri, 7 Jul 1995 15:47:27 -0400 Received: from uucp6.UU.NET by relay3.UU.NET with SMTP id QQyxjz12556; Fri, 7 Jul 1995 15:47:41 -0400 Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03757; Fri, 7 Jul 95 12:53:48 PDT Received: from vhdl.vhdl.org by hermes.intel.com (5.65/10.0i); Fri, 7 Jul 95 12: 50:36 -0700 Received: from hermes.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0sUJQ6-000twWC; Fri, 7 Jul 95 12:50 PDT From uunet!qdt.com!jonp@uunet.uu.net Mon Jul 10 09:49:19 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02896; Mon, 10 Jul 95 09:49:19 PDT Received: from uucp3.UU.NET by relay3.UU.NET with SMTP id QQyxuo16051; Mon, 10 Jul 1995 12:43:05 -0400 Received: from qdt.UUCP by uucp3.UU.NET with UUCP/RMAIL ; Mon, 10 Jul 1995 12:42:54 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00404; Mon, 10 Jul 95 08:10:25 PDT Received: from qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA00557; Mon, 10 Jul 95 08:18:35 PDT Received: from uucp4.UU.NET by relay3.UU.NET with SMTP id QQyxui22411; Mon, 10 Jul 1995 11:14:59 -0400 Received: from qdt.UUCP by uucp4.UU.NET with UUCP/RMAIL ; Mon, 10 Jul 1995 11:14:50 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00353; Mon, 10 Jul 95 07:49:26 PDT Received: from f14.qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA00380; Mon, 10 Jul 95 07:57:36 PDT Date: Mon, 10 Jul 95 07:57:36 PDT From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell) Message-Id: <9507101457.AA00380@hal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA21676; Mon, 10 Jul 95 07:52:40 PDT To: uunet!uunet!medtronic.com!hsin-huei.lin@uunet.uu.net Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net In-Reply-To: (uunet!medtronic.com!hsin-huei.lin) Subject: Re: Battery operated device IBIS does not specifically handle this battery situation, though there may be some things that can be done. some questions: How much time is "as time goes by" and how much drop is "drop". jon powell From Will_Hobbs@ccm2.jf.intel.com Thu Jul 13 10:45:53 1995 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04817; Thu, 13 Jul 95 10:45:53 PDT Received: from relay.jf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #7) id m0sWRll-000UdtC; Thu, 13 Jul 95 10:09 PDT Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0sWRlk-000tx9C; Thu, 13 Jul 95 10:09 PDT Received: by ccm.jf.intel.com (ccmgate 3.2 #1) Thu, 13 Jul 95 10:09:48 PDT Date: Thu, 13 Jul 95 10:07:00 PDT From: Will Hobbs Message-Id: To: ibis@vhdl.org, CUNY@n413pdb.pdb.sni.de Subject: Re: QU: SPICE2IBIS, list of IBIS-models Text item: Roland, I understand your interest in obtaining a comprehensive list of IBIS models, buth public and private. Unfortunately, we have not been successful in assembling such a list. We are aware of a number of IC vendors making such models, but they have not responded to our suggestion of having the models listed, if not posted, on our server on vhdl.org. I am posting this reply to the IBIS reflector in hopes that companies that have such models, or knowledge of such models, will respond. SPICE2IBIS is freely available in support of IBIS V1.1, and an IBIS V2.1 version is under development. When complete, it too will be freely available. FTP into vhdl.org to obtain the current version of this utility. If you are not on the IBIS reflector mailing list, send a request to ibis-request@vhdl.org and request to be added. That way, you can follow the progress of spice2ibis through the meeting minutes. Past minutes can be ftp-ed from vhdl.org, too. I hope this information is helpful. Regards, Will Hobbs Chairman, EIA IBIS Committee and XTG Modeling Manager Intel Corp. Dear Sirs, could you please send detailed informations about SPICE2IBIS-converter to my address? (availability, price, etc.) We are using the EMC-Workbench from INCASES for many years and found out that there are not many semiconductor companies that supply IBIS-models. Even Intel which is main driver of the program, supports only a few components. Most suppliers do not want to create IBIS upon customers request because they do not have the data and need to perform expensive measurements. Therefore I would like to have a complete list of all semiconductor parts that have IBIS-models. This should include the non-public models as well. Please do not send the tiny list with the 30 parts that are available on the bulletin. This does not help us. With best regards, Roland Cuny ------------------------------------------------------------------------- | Siemens Nixdorf Informationssysteme AG | Roland H.G. Cuny Tel. : +49 (0)5251/8-20346 S i e m e n s | SU MR PD 152 Fax : +49 (0)5251/8-20349 ============= | Heinz Nixdorf Ring 1 EMAIL: cuny.pad@sni.de N i x d o r f | D-33094 Paderborn direct: cuny@n413pdb.pdb.sni.de | Germany ------------------------------------------------------------------------- Enjoy fast machines: No speed limit on computers, busses and autobahns Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Message-Id: <9400407492D@n413pdb.pdb.sni.de> X-Mailer: Pegasus Mail/Windows (v1.22) Priority: normal Return-Receipt-To: "Cuny,Roland,75742,M,940101,," X-Pmrqc: 1 X-Confirm-Reading-To: "Cuny,Roland,75742,M,940101,," Subject: QU: SPICE2IBIS, list of IBIS-models Date: Thu, 13 Jul 1995 10:48:23 +1 To: ibis-info@vhdl.org Organization: SNI SU MR From: "Cuny,Roland,75742,M,940101,," Received: from TEMPQ by N413PDB (Mercury 1.12); Thu, 13 Jul 95 10:48:25 +1 Received: from N413PDB/TEMPQ by n413pdb.pdb.sni.de (Mercury 1.12); Thu, 13 Jul 95 10:49:01 +1 Received: from n413pdb.pdb.sni.de (n413pdb.pdb.sni.de [129.103.151.11]) by nixpb e.pdb.sni.de (8.6.12/8.6.12) with SMTP id KAA04032 for ; Thu , 13 Jul 1995 10:46:12 +0200 Received: from nixpbe.pdb.sni.de ([192.109.2.33]) by vhdl.vhdl.org (4.1/SMI-4.1/ BARRNet) id AA28647; Thu, 13 Jul 95 01:54:50 PDT Received: from vhdl.vhdl.org by hermes.intel.com (5.65/10.0i); Thu, 13 Jul 95 01 :50:58 -0700 Received: from hermes.intel.com by ichips.intel.com (5.64+/10.0i); Thu, 13 Jul 9 5 01:51:12 -0700 Received: from ichips.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0sWJzI-000twmC; Thu, 13 Jul 95 01:51 PDT From medtron!relay.medtronic.com!hsin-huei.lin@uunet.uu.net Thu Jul 13 15:29:20 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06350; Thu, 13 Jul 95 15:29:20 PDT Received: from uucp4.UU.NET by relay3.UU.NET with SMTP id QQyygn09761; Thu, 13 Jul 1995 18:22:50 -0400 Received: from medtron.UUCP by uucp4.UU.NET with UUCP/RMAIL ; Thu, 13 Jul 1995 18:22:50 -0400 Received: from medtron.medtronic.COM by relay.medtronic.com with SMTP id AA09564 (5.65c/IDA-1.4.4 for ); Thu, 13 Jul 1995 17:17:18 -0500 Received: from mspeos.cis.corp.medtronic.COM (eos.cis.corp.medtronic.COM) by medtron.medtronic.COM with SMTP id AA09560 (5.65c/IDA-1.4.4 for ); Thu, 13 Jul 1995 17:17:17 -0500 Received: from eos.cis.corp.medtronic.COM by mspeos.cis.corp.medtronic.COM (5.x/SMI-SVR4) id AA11326; Thu, 13 Jul 1995 17:16:55 -0500 Received: from MSPEOS-Message_Server by eos.cis.corp.medtronic.COM with Novell_GroupWise; Thu, 13 Jul 1995 17:16:54 -0500 Message-Id: X-Mailer: Novell GroupWise 4.1 Date: Thu, 13 Jul 1995 17:18:36 -0500 From: Hsin-Huei Lin To: ibis@vhdl.org Subject: Experience with S2IBIS Hi, I would like to speak to anyone who has experience using s2ibis to create IBIS data for ASIC design, please call me at (612)-574-4641. Thank you. Hsin-Huei Lin Medtronic, Inc. From fvance@FirePower.COM Thu Jul 13 16:18:59 1995 Return-Path: Received: from FirePower.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06720; Thu, 13 Jul 95 16:18:59 PDT Received: from oahu by FirePower.COM (NX5.67e/NX4.0Mhb.0b) id AA12483; Thu, 13 Jul 95 16:09:03 -0700 Received: from protocol by oahu.FirePower.COM (NX5.67d/NX3.0M) id AA18398; Thu, 13 Jul 95 16:12:14 -0700 From: Fred Vance Message-Id: <9507132312.AA18398@oahu.FirePower.COM> Received: by protocol.FirePower.COM (NX5.67d/NX3.0X) id AA03051; Thu, 13 Jul 95 16:12:12 -0700 Date: Thu, 13 Jul 95 16:12:12 -0700 Received: by NeXT.Mailer (1.99.1) Received: by NeXT Mailer (1.99.1) To: Hsin-Huei Lin Subject: Re: Experience with S2IBIS Cc: ibis@vhdl.org Hsin-Huei, I have not used S2IBIS, but I have created IBIS models from SPICE models for use with ASIC designs. The models I created were for use as behavioral HSPICE models. This sounds circular (SPICE to IBIS to HSPICE), but IBIS SPICE models work a lot better than transistor-level SPICE in some of my applications. I have also converted SPICE models to XTK models using XTK's SPI2XTK utility. I have even converted IBIS models to SPICE models so that I could then convert them to XTK models. Something that is not always clear to new users of IBIS models is that IBIS models are independent of the tools that you use. If you are planning to use IBIS models with SPICE or Quad Design's XTK tool set and I can be of help to you, let me know. Fred Vance, Engineer FirePower Systems, Inc. (We make computers.) Menlo Park, CA From bob@icx.com Fri Jul 14 10:20:15 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15454; Fri, 14 Jul 95 10:20:15 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 14 Jul 95 10:13 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 14 Jul 95 10:16 PDT Message-Id: Date: Fri, 14 Jul 95 10:16 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS MEETING AGENDA 7/21/95 IBIS Open Forum Meeting Agenda for 7/21/95 Bridge Number Reservation # Passcode (916) 356-9999 1-3147 7221442 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Jon Powell for Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-in, Intros, Announcements Powell - Intros of New IBIS Participants Powell - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Opens for New Issues All - Press Updates All - New Models Available, Library Update All o Tracking usage Huq o Models Under NDA Huq 8:15 EIA IBIS Status - Membership Update Rusher - Treasurer's Report Rusher - Balloting Issues/Update Rusher - Company Logos Powell/Rusher - Web Update Rusher/Huq - Approval of Web Documents Huq 8:30 Administrative Discussions Golden Parser 2.1 status Ross Rev 2.1 Updates o S2IBIS 2.1 Status Kumar o Cookbook Chrisafulli/Ross o Overview Chrisafulli/Ross 9:00 Technical Discussions BIRD 27 - New keyword for differential I/O Ward BIRD 28.1 - Package model extension Peters BIRD 29.2 - Banded_matrix Extension (Vote) Ross Support of MCMs and SIMMs? If yes, how? Crisafulli Pin Programmable Buffer Strengths Muranyi New Issues All 9:55 Wrap-up, Next Meeting Plans Powell From Arpad_Muranyi@ccm.fm.intel.com Fri Jul 14 14:51:15 1995 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16797; Fri, 14 Jul 95 14:51:15 PDT Received: from relay.jf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #7) id m0sWsWH-000UhlC; Fri, 14 Jul 95 14:43 PDT Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0sWsWH-000twdC; Fri, 14 Jul 95 14:43 PDT Received: by ccm.hf.intel.com (ccmgate 3.2 #2) Fri, 14 Jul 95 14:43:36 PDT Date: Fri, 14 Jul 95 14:38:00 PDT From: Arpad Muranyi Message-Id: To: ibis@vhdl.org Subject: Programmable buffers Hi IBIS folks, I am writing this EMAIL to generate a discussion and a possible future EGG and BIRD on how to deal with programmable buffers in IBIS. Problem: There are buffers out there which have programmable strength, in other words, buffers which have not just a single set of I-V and edge rate description per pullup or pulldown structure. Currently there are no provisions in the IBIS specification for such buffers. The work around for such buffers is to create independent buffer models for the various buffer modes and include them as separate models in the IBIS file. In the notes section, one can make a comment about the use of these additional models for the programmable buffers. This method is possible in IBIS, since it is not illegal to have more buffers in an IBIS file than what the pin list section calls for. The area where IBIS is lacking is that there are no nice ways defined to help the user to switch between the various modes of a buffer. Suggestions: One thing that came to my mind was to allow the listing of several buffers for one pin name, something like this (forgive me the bogus pin and buffer names): 1 reset 74ALS244 1 reset 74F244 1 reset 74HCT244 | or without repeating the pin and signal names: 2 AD0 74ALS241 74F241 74HCT241 3 AD1 74ALS241 ..... and so on. The simulation tool could then give the user the option to select between the buffers when simulating with that pin. One problem with this method is that the pin list can grow fairly large if there are lot of programmable pins in it. Another idea would be to allow buffer models to contain more than just one set of I-V and edge rate data section. If this method is used, we might need to invent another keyword, or some mechanism to be able to select between these sections. This method would be more compact (at least in terms of the pin list) but might be more complicated on the buffer model level. This is what I came up with so far. Does anyone care to add comments, ideas to this conversation starter? Sincerely, Arpad Muranyi Intel Corporation From cshfta@taux01.nsc.com Sun Jul 16 23:14:38 1995 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07486; Sun, 16 Jul 95 23:14:38 PDT Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA09646 for ibis@vhdl.org; Sun, 16 Jul 95 23:08:12 -0700 Received: from taux01.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA25283 for ibis@vhdl.org; Sun, 16 Jul 95 23:07:26 -0700 Received: from tasu47.nsc.com by taux01.nsc.com (4.1/SMI-4.1) id AA21087; Mon, 17 Jul 95 09:09:02 IDT Received: by tasu47.nsc.com (4.1/SMI-4.1) id AA06808; Mon, 17 Jul 95 09:06:00 IDT Date: Mon, 17 Jul 95 09:06:00 IDT From: cshfta@taux01.nsc.com (Shimon Friedman ) Message-Id: <9507170606.AA06808@tasu47.nsc.com> To: Arpad_Muranyi@ccm.fm.intel.com Subject: Re: Programmable buffers Cc: ibis@vhdl.org Yes, this is a real problem, and even worth. There are buffers that are also programmed by function; for example they can operate as open drain or push-pull according to a programmable pin. Anyhow, the same mechanism that will be adopted for programmable strength can be used also for programmable function. Shimon Friedman National Semiconductor ----- Begin Included Message ----- From yoram@taux01 Sun Jul 16 09:02:12 1995 Date: Sun, 16 Jul 95 09:02:10 IDT From: yoram@taux01 (Yoram Avigdor) To: shimonf Subject: Programmable buffers Content-Length: 2424 ----- Begin Included Message ----- >From Arpad_Muranyi@ccm.fm.intel.com Sat Jul 15 03:56:39 1995 Date: Fri, 14 Jul 95 14:38:00 PDT From: Arpad Muranyi To: ibis@vhdl.org Subject: Programmable buffers Hi IBIS folks, I am writing this EMAIL to generate a discussion and a possible future EGG and BIRD on how to deal with programmable buffers in IBIS. Problem: There are buffers out there which have programmable strength, in other words, buffers which have not just a single set of I-V and edge rate description per pullup or pulldown structure. Currently there are no provisions in the IBIS specification for such buffers. The work around for such buffers is to create independent buffer models for the various buffer modes and include them as separate models in the IBIS file. In the notes section, one can make a comment about the use of these additional models for the programmable buffers. This method is possible in IBIS, since it is not illegal to have more buffers in an IBIS file than what the pin list section calls for. The area where IBIS is lacking is that there are no nice ways defined to help the user to switch between the various modes of a buffer. Suggestions: One thing that came to my mind was to allow the listing of several buffers for one pin name, something like this (forgive me the bogus pin and buffer names): 1 reset 74ALS244 1 reset 74F244 1 reset 74HCT244 | or without repeating the pin and signal names: 2 AD0 74ALS241 74F241 74HCT241 3 AD1 74ALS241 ..... and so on. The simulation tool could then give the user the option to select between the buffers when simulating with that pin. One problem with this method is that the pin list can grow fairly large if there are lot of programmable pins in it. Another idea would be to allow buffer models to contain more than just one set of I-V and edge rate data section. If this method is used, we might need to invent another keyword, or some mechanism to be able to select between these sections. This method would be more compact (at least in terms of the pin list) but might be more complicated on the buffer model level. This is what I came up with so far. Does anyone care to add comments, ideas to this conversation starter? Sincerely, Arpad Muranyi Intel Corporation ----- End Included Message ----- ----- End Included Message ----- From speters@ichips.intel.com Tue Jul 18 18:22:23 1995 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03163; Tue, 18 Jul 95 18:22:23 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Tue, 18 Jul 95 18:15:41 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Tue, 18 Jul 95 18:00:46 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Tue, 18 Jul 95 18:00:45 PDT Message-Id: <9507190100.AA26917@xtg801.intel.com> To: ibis@vhdl.org Subject: Example for Bird28 Date: Tue, 18 Jul 1995 18:00:43 -0700 From: Stephen Peters Hello All: Here is an example that illustrates how to describe a simple QFP package. My advance appologies for those who do not use PC's but I had to do the example as a Microsoft word document, I simply could not make a resonable ASCII drawing of a QFP leadframe. The document has been uuencoded for transmission thru the various mail systems. If you would like me to Fax you a copy please email me your fax number. Best Regards, Stephen Peters Intel Corp. ----------------- bird28ex.doc ----------------- begin 660 bird28ex.doc MT,\1X*&Q&N$ .P # /[_"0 & ! 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( end From speters@ichips.intel.com Wed Jul 19 08:32:36 1995 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12917; Wed, 19 Jul 95 08:32:36 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 19 Jul 95 08:26:06 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Wed, 19 Jul 95 08:25:57 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Wed, 19 Jul 95 08:25:55 PDT Message-Id: <9507191525.AA01652@xtg801.intel.com> To: ibis@vhdl.org Subject: Bird 28 example, postscript format Date: Wed, 19 Jul 1995 08:25:53 -0700 From: Stephen Peters Hello Fellow IBISans: Because of the large number of requests I've received to FAX the example [I had no idea this Bird was so popular :-) ] and because of a timely sugestion from Chris Reid (thanks!) I'm resending the example in postscript format. Again, it has been uuencoded to get it thru the Unix mail systems. Hope to hear from everyone friday. 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M+3,@2!E9"]D>"!E9"!D M>" P(')L=" P(&1Y(')L="!D>"!N96<@,"!R;'0@8W!]8F0-"B]#0GM"(&-L M:7 @;GUB9"]%V5R2 Y+C8@9&5F+TAE;'9E=&EC82!F:6YD9F]N=" N,B!S8V%L969O M;G0@"!Y(&UO=F5T;RA/9F9E;F1I;F<@0V]M;6%N9" ]("ES M:&]W+V-O;6UA;F0@;&]A9'MD=7 @='EP92]S=')I;F=T>7!E#0IN97LH;6%X M(&5R7!E#0IN97LH(&UA>"!E&5C(&5R MW@@ M,2!A9&0@>2 N,B!S=6(@;6]V971O(&5R2 N,B!S=6(@9&5F('@@,0T*861D('D@ M;6]V971O(&1U<"!T>7!E+W-T6EN9R!T;R!D97-C&%M<&QE('1H97)E(&%R92 Q-2!S:6=N86QS(&%N9" U(&=R;W5N9',L(&9O M2!O=&AE&ES('!O:6YT(%PR,C$Q-EPR,C(@=&\@7#(R,3$W7#(R,EPI+BD@,3,Y-2!3 M0@T*14H@4E,-"B4E4&%G951R86EL97(-"E-3#0HP(# @,C @,3$@.# Y(#$Q M,# @,S P(%--#0HS,B P(# @-3 @-3 @," P(# @-#4@+U1I;65S+5)O;6%N M("]F;VYT,S(@04Y3249O;G0@9F]N= T*," P(# @9D,-"C,Q-2 S,C@@,32!S M;6%L;"X@($EN(&$@2!D:69F97)E;G0@;&5N9W1H(&EN('-E8W1I;VX@,B!A;F0@" O($QE;CTT M+C @36%T" O($QE;CTQ+C0@ M36%T" O*2 Q-C P(%-"#0HS,34@,38X,2 Q-C P("A3:6" O($QE;CTT+C,@36%T" O($QE;CTQ+C(@36%T&5S(&1E9FEN960L(&]N M92!F;W(@96%C:"!S96-T:6]N+B!"96-A=7-E('-I9S$L('-I9S(@86YD('-I M9S,@8V]U<&QE+"D@,3&%M<&QE+BD@-30U(%-"#0HS,34@ M,C,S-2 Q-S(R("A%86-H(&EN9&EV:61U86P@;6%TF4@;V8@;6%T2 R+3-<*2!P:6YS M('1H870@87)E(&-O=7!L960@=&\@:70N*2 Q-C4U(%-"#0I%2B!24PT*)250 M86=E5')A:6QE<@T*)254 Received: from FirePower.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA14725; Wed, 19 Jul 95 11:58:31 PDT Received: from oahu by FirePower.COM (NX5.67e/NX4.0Mhb.0b) id AA04952; Wed, 19 Jul 95 11:51:55 -0700 Received: from protocol by oahu.FirePower.COM (NX5.67d/NX3.0M) id AA29779; Wed, 19 Jul 95 11:51:54 -0700 From: Fred Vance Message-Id: <9507191851.AA29779@oahu.FirePower.COM> Received: by protocol.FirePower.COM (NX5.67d/NX3.0X) id AA04852; Wed, 19 Jul 95 11:51:52 -0700 Date: Wed, 19 Jul 95 11:51:52 -0700 Received: by NeXT.Mailer (1.99.1) Received: by NeXT Mailer (1.99.1) To: kellee@hyperlynx.com Subject: Re: Experience with S2IBIS Cc: ibis@vhdl.org Kellee, In response to your question: > > I saw the posting you made to Hsin-Huei and was a little curious about >your statement that IBIS is independent of the tools. Are you aware >that several tools directly support IBIS? > Yes. What I meant about IBIS being independent of tools is that IBIS models can be used by more than one tool. I was trying to make the point that an IBIS model is not a tool, but information for use with a tool. Ironically, I caused a minor uproar in the past by stating (incorectly) that IBIS was not a model. At that time, I was trying to say that an IBIS model alone can not be used for simulation, but requires a simulation tool. I suppose that one could argue that since it is possible to use IBIS data in a Bergeron Plot that tools are not necessary for simulations with an IBIS model. I for one, want my tools. I have tried in the past to make a distinction between IBIS, the specification and IBIS, the information or model. Now, I think I will have to make the further delineation, IBIS tools and IBIS compatible simulators. You also wrote: > There are many tools out that directly support IBIS models. For example >both of our HyperLynx tools LineSim and BoardSim read and and use IBIS >models without conversion. I might have unintentionally given the impression that Quad Design doesn't have an IBIS tool. They do, it's called IBIS2XTK. (While I'm at it, I refered to Quad's tool SPI2MOD incorrectly as SPI2XTK.) Also, Syed Huq told me that Meta-Software has a utility to convert an IBIS model to an HSPICE behavioral model. I may have both of these utilities and haven't tried them yet. The reason? I did most of my library building in 1994 when these tools weren't available (or only under an NDA). Since then, new models that I received have been SPICE models. I would like to be a strong advocate of IBIS. I believe it is great for everyone. Regards, Fred From jonp@qdt.com Wed Jul 19 15:27:08 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16536; Wed, 19 Jul 95 15:27:08 PDT Received: from uucp3.UU.NET by relay3.UU.NET with SMTP id QQyzcr18252; Wed, 19 Jul 1995 18:20:41 -0400 Received: from qdt.UUCP by uucp3.UU.NET with UUCP/RMAIL ; Wed, 19 Jul 1995 18:20:41 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00270; Wed, 19 Jul 95 14:19:18 PDT Received: from f14.qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA11535; Wed, 19 Jul 95 08:27:32 PDT Date: Wed, 19 Jul 95 08:27:32 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9507191527.AA11535@hal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA02936; Wed, 19 Jul 95 08:22:25 PDT To: ibis@vhdl.org Subject: bird 28 Stephen, Though in general I like your idea I must disagree with the results you present in the word file (besides it being prepared on a PC, I mean). You state since pins 1 2 and 3 couple that they must have the same length, as do pins 8,9,10, and 19,20. The problem is that though pins 1,2,3 couple so do pins 2,3,4 and 4,5,6 and 6,7,8 and if your length argument applies, wires 1 and 20 must have the same length (by induction). I realize that you have ground wires in the lead frame and are using them as coupling signal separation but this is not a fair case. A lead frame would not NEED to have that many grounds, and signals do couple through grounds to the next pins over (so a sig3,GND,sig5 coupling would be a reasonable worry). Perhaps just the restriction of having the coupled segments being the same length is to stringent. Perhaps you should just specify the actual length and the actual coupling and let people do the database segmentation themselves. jon From speters@ichips.intel.com Wed Jul 19 16:30:54 1995 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17015; Wed, 19 Jul 95 16:30:54 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Wed, 19 Jul 95 16:24:27 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Wed, 19 Jul 95 16:23:57 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Wed, 19 Jul 95 16:23:56 PDT Message-Id: <9507192323.AA03023@xtg801.intel.com> To: ibis@vhdl.org Subject: bird 28 comments Date: Wed, 19 Jul 1995 16:23:55 -0700 From: Stephen Peters Hello Jon, and others: While I think that almost all realistic packages do have intersperced ground I have to agree with Jon -- there can be a situation of signal, GND, signal coupling and thus the restriction becomes unworkable. (There is also Jon's original example of no grounds and the leads couple to there nearest neighboor. Even if this is unlikely the spec should handle this case.) I guess my question now is what simulation tools will do if actual section lenghts are included. The scenario as I see it is: 1. The field solver assumes a bunch of parallel wires of infinite length, and reports coupling 'per unit length'. 2. The coupling per unit length, and the actual length of each section is entered into the package file. 3. Now, can existing simulation tools handle the actual, unequal lengths? For example, if one is stimulating a section of sig2, and it couples to sig1 and sig3, would a simulation tool assume that all three sections are of equal length (perhaps use the average length). Does a tool have to include the extra length of the longer sections as an uncoupled bit of L/C? This is the question I think we need to discuss Friday. Anyway, thanks for your comments. Regards, Stephen Peters Intel Corp. From uunet!qdt.com!jonp@uunet.uu.net Wed Jul 19 19:19:41 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17995; Wed, 19 Jul 95 19:19:41 PDT Received: from uucp4.UU.NET by relay3.UU.NET with SMTP id QQyzdg21276; Wed, 19 Jul 1995 22:11:40 -0400 Received: from qdt.UUCP by uucp4.UU.NET with UUCP/RMAIL ; Wed, 19 Jul 1995 22:11:40 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00926; Wed, 19 Jul 95 18:11:29 PDT Received: from qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA14574; Wed, 19 Jul 95 18:19:55 PDT Received: from uucp2.UU.NET by relay3.UU.NET with SMTP id QQyzdc15581; Wed, 19 Jul 1995 21:14:26 -0400 Received: from qdt.UUCP by uucp2.UU.NET with UUCP/RMAIL ; Wed, 19 Jul 1995 21:14:26 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00846; Wed, 19 Jul 95 16:50:46 PDT Received: from f14.qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA14252; Wed, 19 Jul 95 16:59:12 PDT Date: Wed, 19 Jul 95 16:59:12 PDT From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell) Message-Id: <9507192359.AA14252@hal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA03420; Wed, 19 Jul 95 16:54:04 PDT To: uunet!uunet!ichips.intel.com!speters@uunet.uu.net Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net In-Reply-To: <9507192323.AA03023@xtg801.intel.com> (uunet!ichips.intel.com!speters) Subject: Re: bird 28 comments Let me tell you what I think I would do. For any group of lines that couple you need an "ACTIVE" line, that is, the one that is going to be stimulated. This is usually the line in the middle of a group since outside lines would, per se, couple to more lines surrounding them if they were ACTIVE. Now you build your simulation net list. I would do something like: P1 =========================== A ======================== P2 ==================== |-------------------|---|--| (A is active net and P1 and P2 are passive nets. Pretend they are at 45% angle as in Stephens drawing) Net A would couple to P2 and P1 using a 3 config coupling for the length of P2. Net A would couple to net P1 with a 2 config coupling from the end of P2 to the end of A. Net P1 would have an additional, "self only" coupling for the rest of its length. Ideally, IBIS would supply this data, baring that, perhaps things could be hacked. Of course, if we know how people are going to hack things we should just give the right data to begin with. jon From jayd@VNET.IBM.COM Thu Jul 20 05:37:49 1995 Return-Path: Received: from VNET.IBM.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26194; Thu, 20 Jul 95 05:37:49 PDT Message-Id: <9507201237.AA26194@vhdl.vhdl.org> Received: from RALVM29 by VNET.IBM.COM (IBM VM SMTP V2R3) with BSMTP id 0302; Thu, 20 Jul 95 08:30:50 EDT Date: Thu, 20 Jul 95 08:18:46 EDT From: "J. C. (Jay) Diepenbrock ((919)-543-8804)" X-Addr: Communications Transceiver Dev't, D63/656 IBM Network Hdwe. Div. P. O. Box 12195 Research Triangle Park, NC 27709 To: ibis@vhdl.org Subject: Bird 28 Although I can see the reasoning behind trying to make simplifying assumptions, I agree with Jon that it is too restrictive to require that any coupling sections must be of equal length. I would also caution Stephen against designing a solution around specific packages (e. g., QFPs) that may not apply to other packages (yes, there are still people out there using DIPs). I would prefer to have a more complicated model that's accurate than a simple one that isn't. I suspect that someone who's done a detailed analysis of a real package will also disagree with the notion that pins never couple to other pins from which they are separated by a single Ground pin. I have not done extensive package analysis, and it may be a "noise" effect, so perhaps that's a reasonable compromise for the sake of complexity and compute time. In my opinion, whatever method the group chooses to adopt should not make any assumptions about the pin assignment as well (e. g., three signals for each Ground, all the way around), because real packages are seldom that orderly (and someone "out there" will come up with another one as soon as the model is done anyway, if not sooner). Jay Diepenbrock From medtron!relay.medtronic.com!hsin-huei.lin@uunet.uu.net Thu Jul 20 10:39:27 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA28149; Thu, 20 Jul 95 10:39:27 PDT Received: from uucp1.UU.NET by relay3.UU.NET with SMTP id QQyzfq26702; Thu, 20 Jul 1995 13:32:46 -0400 Received: from medtron.UUCP by uucp1.UU.NET with UUCP/RMAIL ; Thu, 20 Jul 1995 13:32:46 -0400 Received: from medtron.medtronic.COM by relay.medtronic.com with SMTP id AA19438 (5.65c/IDA-1.4.4 for ); Thu, 20 Jul 1995 12:31:13 -0500 Received: from mspeos.cis.corp.medtronic.COM (eos.cis.corp.medtronic.COM) by medtron.medtronic.COM with SMTP id AA19433 (5.65c/IDA-1.4.4 for ); Thu, 20 Jul 1995 12:31:11 -0500 Received: from eos.cis.corp.medtronic.COM by mspeos.cis.corp.medtronic.COM (5.x/SMI-SVR4) id AA28781; Thu, 20 Jul 1995 12:30:34 -0500 Received: from MSPEOS-Message_Server by eos.cis.corp.medtronic.COM with Novell_GroupWise; Thu, 20 Jul 1995 12:30:34 -0500 Message-Id: X-Mailer: Novell GroupWise 4.1 Date: Thu, 20 Jul 1995 12:32:22 -0500 From: Hsin-Huei Lin To: ibis@vhdl.org Subject: How to model the L and C of bondwire Everyone, I am trying to include the R/L/C of bondwire as part of the package parameter to the ASIC that is mounted on Hybrid substrate. I know the Resistence spec. but the vendors are not able to provide the L and C to me. Does anyone got some number that I can use? Any help is appreciated. Thank you. Hsin-Huei Lin Medtronic, Inc. (612)574-4641 From nihat@mucsun.sps.mot.com Fri Jul 21 01:12:18 1995 Return-Path: Received: from spsgate.sps.mot.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03484; Fri, 21 Jul 95 01:12:18 PDT Received: from mogate (mogate.sps.mot.com) by spsgate.sps.mot.com (4.1/SMI-4.1/Email 2.1 10/25/93) id AA02457 for ibis@vhdl.org; Fri, 21 Jul 95 00:54:48 MST Received: from emailmesa by mogate (4.1/SMI-4.1/Email-2.0) id AA03486; Fri, 21 Jul 95 00:54:46 MST Received: from nihoa.suedsee by mucsun.suedsee (4.1/SMI-4.1) id AA02096; Fri, 21 Jul 95 09:54:55 +0200 Date: Fri, 21 Jul 95 09:54:55 +0200 From: nihat@mucsun.sps.mot.com (Nihat Cabuk) Message-Id: <9507210754.AA02096@mucsun.suedsee> To: ibis@vhdl.org Subject: Re: How to model the L and C of bondwire Hi, You can use a lumped LRC model for a typical bond wire. The values are in the range of L=2nH, C=0.5pF, R=200mohm. Hope this helps, Nihat Motorola, Munich - Germany > From medtron!relay.medtronic.com!hsin-huei.lin@uunet.uu.net Thu Jul 20 20:22:24 1995 > X-Mailer: Novell GroupWise 4.1 > Date: Thu, 20 Jul 1995 12:32:22 -0500 > From: Hsin-Huei Lin > To: ibis@vhdl.org > Subject: How to model the L and C of bondwire > Content-Length: 352 > > Everyone, > I am trying to include the R/L/C of bondwire as part of the package > parameter to the ASIC that is mounted on Hybrid substrate. I know the Resistence > spec. but the vendors are not able to provide the L and C to me. Does anyone > got some number that I can use? Any help is appreciated. Thank you. > > Hsin-Huei Lin > Medtronic, Inc. > (612)574-4641 > > > From awglaser@eos.ncsu.edu Fri Jul 21 07:41:31 1995 Return-Path: Received: from c11007-343dan.ece.ncsu.edu by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09579; Fri, 21 Jul 95 07:41:31 PDT Received: by c11007-343dan.ece.ncsu.edu (8.6.11/EC06jan95) id KAA19509; Fri, 21 Jul 1995 10:35:01 -0400 From: "Alan Wolfram Glaser" Message-Id: <9507211035.ZM19507@eos.ncsu.edu> Date: Fri, 21 Jul 1995 10:35:00 -0400 X-Mailer: Z-Mail Lite (3.2.0 5jul94) To: ibis@vhdl.org Subject: Update on Spice to IBIS v 2 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii 7/20/95 Here is an update on our (North Carolina State University) progress on the next spice-to-ibis converter (s2ibis). We have been able to undertake this project thanks to the generous support of Cadence. The basic strategy is to parse an s2ibis input file, set up internal data structures completely (with the exception of the data tables for VI and tV curves) and then initiate analyses with a flavor of Spice. These analyses are parsed and the results used to complete the internal ibis data structures. The *.ibs file is then generated from the completed data structure. This is a departure from the way version 1 of s2ibis works--it was essentially an interpreter that fired off analyses as the input file was parsed. The new scheme does require more memory than s2ibis v1.1, and the command file can be more complex, but the new grammar seems to be the only reasonable way to embody the complexity allowed by the IBIS v2.1 specification, to provide meaningful message reporting, and to provide for relatively painless future expansion. We estimate that we have put 7 man-weeks into the coding so far. We have completed the output code, parts of the analysis code, and are currently addressing some initial deficiencies in our command grammar. We expect to have a beta version of the software (including documentation and a cut-and-paste command file template) within four weeks. The prototype will allow for all features contained in the IBIS v2.1 specification, with the exception of the Package Modeling capabilities. While our converter will handle the [Package Model] keyword correctly, it will not handle any of the information that can be contained in a .pkg file. The converter currently is compatible with the following flavors of Spice: HSpice, PSpice, Spectre, Berkeley Spice 2 and Berkeley Spice 3. Michael Steer Alan Glaser -- Alan Glaser ECE Dept. North Carolina State University From mbs@eos.ncsu.edu Fri Jul 21 07:49:54 1995 Return-Path: Received: from mbs.ece.ncsu.edu (c11058-335dan.ece.ncsu.edu) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09646; Fri, 21 Jul 95 07:49:54 PDT Received: by mbs.ece.ncsu.edu (5.65/Eos/C-U-09Sep93) id AA18180; Fri, 21 Jul 1995 10:43:25 -0400 From: mbs@eos.ncsu.edu Message-Id: <9507211443.AA18180@mbs.ece.ncsu.edu> To: ibis@vhdl.org Subject: S2IBIS update Date: Fri, 21 Jul 95 10:43:25 EDT Sorry if this is a repeat message but our earlier posting did not seem to turn up. 7/20/95 Here is an update on our (North Carolina State University) progress on the next spice-to-ibis converter (s2ibis). We have been able to undertake this project thanks to the generous support of Cadence. The basic strategy is to parse an s2ibis input file, set up internal data structures completely (with the exception of the data tables for VI and tV curves) and then initiate analyses with a flavor of Spice. These analyses are parsed and the results used to complete the internal ibis data structures. The *.ibs file is then generated from the completed data structure. This is a departure from the way version 1 of s2ibis works--it was essentially an interpreter that fired off analyses as the input file was parsed. The new scheme does require more memory than s2ibis v1.1, and the command file can be more complex, but the new grammar seems to be the only reasonable way to embody the complexity allowed by the IBIS v2.1 specification, to provide meaningful message reporting, and to provide for relatively painless future expansion. We estimate that we have put 7 man-weeks into the coding so far. We have completed the output code, parts of the analysis code (thanks to Steve Lipa for his trailblazing efforts here), and are currently addressing some initial deficiencies in our command grammar. We expect to have a beta version of the software (including documentation and a cut-and-paste command file template) within four weeks. The prototype will allow for all features contained in the IBIS v2.1 specification, with the exception of the Package Modeling capabilities. While our converter will handle the [Package Model] keyword correctly, it will not handle any of the information that can be contained in a .pkg file. The converter currently is compatible with the following flavors of Spice: HSpice, PSpice, Berkeley Spice 2 and Berkeley Spice 3. Support for Cadence's Spectre is conditioned on availability of the software for testing; this issue is currently being resolved. Michael Steer Alan Glaser From uunet!qdt.com!jonp@uunet.uu.net Fri Jul 21 08:19:18 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09843; Fri, 21 Jul 95 08:19:18 PDT Received: from uucp4.UU.NET by relay3.UU.NET with SMTP id QQyziy19242; Fri, 21 Jul 1995 11:12:49 -0400 Received: from qdt.UUCP by uucp4.UU.NET with UUCP/RMAIL ; Fri, 21 Jul 1995 11:12:49 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00357; Fri, 21 Jul 95 07:38:27 PDT Received: from qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA21655; Fri, 21 Jul 95 07:46:57 PDT Received: from uucp6.UU.NET by relay3.UU.NET with SMTP id QQyziw10506; Fri, 21 Jul 1995 10:42:34 -0400 Received: from qdt.UUCP by uucp6.UU.NET with UUCP/RMAIL ; Fri, 21 Jul 1995 10:42:34 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00330; Fri, 21 Jul 95 07:22:22 PDT Received: from f14.qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA21611; Fri, 21 Jul 95 07:30:52 PDT Date: Fri, 21 Jul 95 07:30:52 PDT From: uunet!qdt.com!jonp@uunet.uu.net (Jon Powell) Message-Id: <9507211430.AA21611@hal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA03857; Fri, 21 Jul 95 07:25:42 PDT To: uunet!uunet!medtronic.com!hsin-huei.lin@uunet.uu.net Cc: uunet!uunet!vhdl.org!ibis@uunet.uu.net In-Reply-To: (uunet!medtronic.com!hsin-huei.lin) Subject: Re: How to model the L and C of bondwire Inductance usually ranges from 4-12 nh and capacitance from 3-8pf for normal packages. You would have to tell us more about the Hybrid packaging for better data. Pin package capacitance is usually a standard part of a chip databook. jon From jonp@qdt.com Fri Jul 21 08:19:20 1995 Return-Path: Received: from relay3.UU.NET by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09844; Fri, 21 Jul 95 08:19:20 PDT Received: from uucp4.UU.NET by relay3.UU.NET with SMTP id QQyziy19267; Fri, 21 Jul 1995 11:12:52 -0400 Received: from qdt.UUCP by uucp4.UU.NET with UUCP/RMAIL ; Fri, 21 Jul 1995 11:12:52 -0400 Received: from hal.qdt.com by qdt.com (4.1/SMI-4.1) id AA00372; Fri, 21 Jul 95 07:44:30 PDT Received: from f14.qdt.com by hal.qdt.com (4.1/SMI-4.1) id AA21666; Fri, 21 Jul 95 07:53:00 PDT Date: Fri, 21 Jul 95 07:53:00 PDT From: jonp@qdt.com (Jon Powell) Message-Id: <9507211453.AA21666@hal.qdt.com> Received: by f14.qdt.com (4.1/SMI-4.1) id AA03862; Fri, 21 Jul 95 07:47:50 PDT To: ibis@vhdl.org Subject: New Egg Germinating I have been told by my engineer implementing the IBIS spec here at Quad that it is virtually impossible to tell if a given output model is CMOS or TTL. We consider this important because the manner in which a CMOS and TTL gate switch on and off (as far as IV curve tracking) is very different. I am considering proposing a new keyword that gives more specification to output transistor type. I am missing something? jon From mellitz@eagle.ColumbiaSC.NCR.COM Fri Jul 21 14:49:12 1995 Return-Path: Received: from eagle.ColumbiaSC.NCR.COM ([153.78.178.8]) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12618; Fri, 21 Jul 95 14:49:12 PDT From: mellitz@eagle.ColumbiaSC.NCR.COM >From: mellitz@eagle (Richard.Mellitz) Message-Id: <9507211748.ZM8916@eagle> Date: Fri, 21 Jul 1995 17:48:07 -0400 X-Mailer: Z-Mail (2.1.4 02apr93) To: ibis@vhdl.org Subject: SPICE to IBIS Content-Type: text Content-Length: 1355 Hi All, I'm a having a bit of difficulty with my understanding of the syntax for s2ibis. I don't seem to understand how the [pin] syntax ties into the SPICE model. Its not in the docs I have. Take a simple example. For a single transceiver (I/O). I would have 2 pins, power, ground and one spice model. Lets ignore package parasitics for now. Say my SPICE subcircuit looks like .SUBCIRCUIT MYIO internal_data_out_pin io_pin VDD VSS ... i.e. |\ ____| \_____ | / |/ internal_data_out_pin io_pin How do I tell s2ibis that the internal_data_out_pin is used for controlling Vol pull up data and Voh pull down data when io_pin is an output? How can I tell s2ibis to use a particular CMOS model (representative of process) to be associated with a certain temperature at a specified voltage. It would seem I would need to do this to get accurate min/max numbers. --------------------------------------------------------------------- Richard Mellitz | AT&T | Global Information Solutions | richard.mellitz@columbiasc.attgis.com 3325 Platt Spring Road | Phone: (803)-939-6240 West Columbia, SC 29170 | Fax: (803)-939-7317 --------------------------------------------------------------------- From bob@icx.com Mon Jul 24 09:04:19 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00703; Mon, 24 Jul 95 09:04:19 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Mon, 24 Jul 95 08:57 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Mon, 24 Jul 95 09:00 PDT Message-Id: Date: Mon, 24 Jul 95 09:00 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: ROSTER UPDATE REQUEST IBIS Participants: Please review attached roster and send me updates/additions for your company. Thank you Bob Ross bob@icx.com Interconnectix, Inc. ============================================================================ EIA IBIS Committee Participation Roster As of 5/23/95 (updated periodically) 32 company/organizations listed Submit changes/updates to: bob@icx.com (503) 603-2523, Fax (503) 639-3469 ============================================================================ NOTE: This roster lists companies and organizations that have either participated in creating the IBIS spec or are creating/distributing IBIS models. Other than the specific statements of support under each organization's name, no support nor endorsement of the specification is implied. ============================================================================ Anacad EES Contact: Steffen Rochel Email: steffen@anacad.com Phone: (408) 954 0600 Fax: (408) 954 8884 Address: 1900 McCarthy Blvd. #310 Milpitas, CA 95035 Support: Anacad can translate IBIS descriptions into models using their analog behavioral modeling language HDL-A. Together with Eldo and a VHDL simulator, highly accurate investigations of mixed signal designs are possible. Tag-line: Ansoft Corporation Contact: Henri Maramis Email: maramis@ansoft.com Phone: (412) 261-3200, Fax: (412) 471-9427 Address: 4 Station Square, Suite 660 Pittsburgh, PA. 15219 Support: The Ansoft Maxwell SI product will support IBIS models/library in native format. Tag-line: Ansoft is a dedicated provider of electromagnetic field simulation software and integrated solutions for signal integrity and EMC/EMI. AT&T Global Information Solutions Contact: Dave Moxley Email: David.Moxley@columbiasc.ncr.com Phone: Address: Support: Tag-line: Atmel Corporation Contact: Dan Terry Email: No internet address -- Pls Fax notices Phone: (408) 436-4346, Fax: (408) 436-4200 Address: Support: Tag-line: Cadence Design Systems, Inc. Contact: C. Kumar Email: cpk@cadence.com Phone: (508) 262-6488, Fax: 508-262-6600 Address: 270 Billerica Rd, Chelmsford, MA 01824 Support: Cadence fully supports IBIS models. Cadence's DF/SigNoise product family offers a vendor-specific, IBIS compatible signal integrity library of over 7000 components. Cadence also provides a translator program enabling the conversion of IBIS 1.1 and 2.1 files to Cadence library format. Tag-line: Cadence, the worldwide leader in electronic design automation, combines leading-edge technology and a complementary set of services to accelerate and advance the overall performance engineering of high-speed electronic systems. Contec Microelectronics USA, Inc. Contact: Dileep Divekar, Clark Cochran Email: dileep@contec.com Phone: (408) 434-6767, Fax: (408) 434-6884 Address: 2188 Bering Drive San Jose, CA 95131 Support: A Contec product will support IBIS models in native mode. Tag-line: Digital Equipment Corp. Contact: Stephen C. Thierauf Email: thierauf@pasta.enet.dec.com Phone: (508) 568-4475, Fax: (508) 568-4367 Address: 77 Reed Road, HLO2-3/G13 Hudson, MA 01749 Support: Digital will generate IBIS models for its own chip products, including the line of ALPHA AXP microprocessors, as needed, and support IBIS models in in-house simulation tools. Tag-line: Digital, maker of the world's fastest microprocessor, is also a leading developer of computer systems, and networking and communication products, including PCI. Hewlett-Packard/HP EEsof Division Contact: Karl Kachigan Email: karlk@sr.hp.com Phone: (707) 577-3949, Fax: (707) 577-5260 Address: 1400 Fountaingrove Parkway Santa Rosa, CA 94503 Support: None at this time Tag-line: HP EEsof is a leading supplier of high frequency analog (RF/Microwave) design and modeling tools. High Design Technology Contact: Maria Teresia Cosso (HDT,Italy), Wence Coron (Anacad EES,US) Email: wence@anacad.com Phone: +39 11 33 84 34 (408) 954-0600 Fax: +39 11 385 99 67 Fax: (408) 954-8884 Address: HDT Anacad EES Via Beaulard, 64 1900 McCarthy Blvd. #310 10139 Torino, Italy Milpitas, CA 95035 Support: An interface to IBIS is in preparation and will be available Q2/95. Tag-line: HDT offers a sophisticated toolset for signal integrity analysis and EMI investigation. In connection with a TDR based modeling technique, accurate and fast analysis of complete PCB's is provided. HyperLynx Contact: Kellee Crisafulli Email: 71436.1314@compuserve.com Phone: (206) 869-2320, Fax: (206) 881-1008 Address: P.O. Box 3578 Redmond, WA 98073-3578 Support: Several signal integrity analysis tools are available: LineSim: A simulator using schematic data input, reads IBIS files as part of its native library support. Ships with a set of IBIS libraries. BoardSim: A simulator using PCB geometry data input from numerous PCB layout packages, also natively supports IBIS files. Ships with a set of IBIS libraries. Additional model libraries are available free of charge to customers on HyperLynx's BBS. Tag line: HyperLynx, Inc. is the industry's leading supplier of affordable, accurate, PC-based signal-integrity software. IBM Corp. (unofficially) Contact: Joseph C. (Jay) Diepenbrock Email: jayd@ralvm29.vnet.ibm.com Phone: (919) 543-8804 Address: IBM Network Hdwe. Div. Transceiver Technology Dev't, D63/061 P. O. Box 12195 Research Triangle Park, NC 27709 Support: No formal declaration of support. Tag-line: INCASES Contact: Werner Rissiek, Olaf Rethmeier Email: wr@cadlab.cadlab.de, olaf@cadlab.cadlab.de Phone: ++49-5251-284-155, ++49-5251-284-222, Fax: ++49-5251-284-105 Address: INCASES Engineering GmbH Vattmannstrasse 3 D-33100 Paderborn, Germany Support: INCASES uses the simulation program FREACS (Fast REflection And Crosstalk Simulator) for signal integrity analysis within the EMC-Workbench. INCASES can read IBIS Version 1.1 files and translate the IBIS models into FREACS models. INCASES uses an IBIS parser and an automatic process for the parametrization of the FREACS macromodels. Additionally, so called 'reference lists' are set-up that are used by the interface (XLIN) between the EMC-Workbench and the FREACS macromodel library. These reference lists consist of circuit information in a special language named HINAC (Hierachical Naming Convention), where macromodel data is assigned to pins of a component using IBIS-information, as well. In this way a controlled set-up of a library is possible using IBIS-files as basis. Detailed information is available on request. Tag-line: INCASES Engineering, GmbH, Germany, founded on November 1, 1994, is a supplier of design automation software and consulting services to the electronic design automation (EDA) market, focusing on EMC and 'Design for Manufacturability'. INCASES develops, sells, and supports two major product lines: THEDA, acquired from Computervision Corporation and EMC-Workbench, acquired from Siemens Nixdorf Informationssysteme AG. Intel Corporation Contact: Will Hobbs Email: Will_Hobbs@ccm2.jf.intel.com Phone: (503) 696-4369, Fax: (503) 696-4210 Address: 5200 NE Elam Young Pkwy, JF1-57 Hillsboro, OR 97124 Support: Intel provides IBIS models for some of its components. For a list of supported components, send the following message to archive@vhdl.org: path send pub/ibis/models/intel readme index /pub/ibis/models/intel Tag-line: Intel, the world's largest chip maker, is also a leading manufacturer of personal computer networking and communications products. Interconnectix, Inc. Contact: Bob Ross Email: bob@icx.com Phone: (503) 684-6641, Fax: (503) 639-3469 Address: 10220 S.W. Nimbus Ave., K4 Portland, Oregon 97223 Support: The Interconnect Synthesis (IS) product supports the major extensions of IBIS Version 2.1. Interface extensions for component and model selection and termination generation allow IBIS formatted data to be used in "what if" investigations and automatic synthesis operations. Tag-line: The leading Interconnect Synthesis Company Intergraph Corp. Contact: Rob Kelley Email: rkelley@ingr.com Phone: (205) 730-8978 Address: One Madison Industrial Park Huntsville, AL 35894-0001 Support: Intergraph Electronics fully supports the activities of the IBIS open forum and as such, is ensuring that all signal integrity development is aligned so that our customers will be able to take advantage of IBIS as the standard stabilizes. Tag-line: Intergraph Corporation, a Fortune 500 company, is the world's largest independent NT development site and the world's largest company dedicated to supplying interactive computer graphics systems. Integrated Silicon Systems, Inc. Contact: Eric Bracken Email: bracken@isscad.com Phone: (412) 832-9627 Address: One Northgate Square Greensburg, PA 15601-1341 Support: PSIBoards accepts IBIS model files directly. The IBIS files can contain any number of models or components. Instances of these models can be declared in the program's input deck, along with interconnections, to describe a complete design. Tag-line: Integrated Silicon Systems, Inc. is a leading supplier of hierarchical layout verification products. IntuSoft Contact: Charles Hymowitz Email: Phone: (303) 833-0710 Address: Support: IntuSoft takes a customer's netlist or model and translates it into a Spice model, free of charge. IntuSoft has the Golden Parser source but hasn't, as of yet, automated the process. IntuSoft is waiting until there are more IBIS models available. Tag-line: Mentor Graphics Corp. Contact: Greg Seltzer, Greg Doyle Email: Greg_Seltzer@mentororg.com, Greg_Doyle@mentororg.com Phone: (503) 685-1198, Fax: (503) 685-7991 Address: 8005 SW Boeckman Rd. Wilsonville, OR 97070-7777 Support: Mentor supports IBIS by using Quad Design and Intel IBIS models. Tag-line: Meta-Software Contact: John Sliney, Mei Wong Email: johns@metasw.com, mei@metasw.com Phone: (408) 369-5446, Fax: (408) 371-5100 Address: 1300 White Oaks Rd. Campbell, CA 95008 Support: Tag-line: MicroSim Corp. Contact: Arthur Wong Email: Phone: (714) 770-3022, FAX: (714) 455-0554 Address: 20 Fairbanks Irvine, CA 92718 Support: MicroSim can automatically generate PSpice models for vendors who provide data in a file format conforming to the IBIS Ver 1.1 specification. The models can then be simulated with PSpice. MicroSim has made IBIS models for Intel's Pentium processor 82430 PCIset available to customers. Tag-line: MicroSim Corp. - The Desktop EDA Company - provides technically sophisticated software for schematic entry, simulation, programmable logic synthesis, and signal integrity analysis. National Semiconductor Corp. Contact: Syed B.Huq Email: huq@rockie.nsc.com Phone: (408) 721-4874, Fax:(408)721-4785 Address: 2900 Semiconductor Drive, M/S A-2595 Santa Clara, CA 95052 Support: The Advanced Systems & Interface Product Group(ASIP) of National Semiconductor is willing to create IBIS model files and provide IBIS model support to customers. Tag-line: National Semiconductor provides technologies for moving and shaping information. The company focuses on communications, analog, and personal systems markets, and is the fourth largest U.S semiconductor merchant. NEC Corporation Contact: Hiroshi Matsumoto Email: mat@lsi.tmg.nec.co.jp Phone: +81 -44-435-1501(DIR), Fax: +81 -44-435-1887 Address: Design Sys. Dept., System ASIC Div., NEC Corp. 1753 Shimonumabe, Nakahara-ku Kawasaki Japan 211 Support: NEC is willing to write some IBIS models and a model generator for some of its LSI components. Tag-line: North Carolina State University Contact: Michael Steer, Paul Franzon, Steve Lipa Email: mbs@ncsu.edu paulf@ncsu.edu slipa@eos.ncsu.edu Phone: 919-515-5191 919-515-7351 919-515-3947 FAX for all three: 919-515-5523 Address: ECE Dept. Box 7911 NC State Univ. Raleigh, NC 27695-7911 Support: (as of 2/94) A Spice to IBIS converter is being developed. A measurement based procedure is being developed for extracting IBIS models. A yacc/lex parser for IBIS models is being develped. All software and techniques will be put in the public domain. Tag-line: Quad Design Technology, Inc. Contact: Jon Powell Email: jonp@qdt.com Phone: (805) 988-8250, Fax: (805) 988-8259 Address: 1385 Del Norte Rd. Camarillo, CA 93010 Support: Quad Design has a translation program that translates from IBIS format to Quad Design .mod format. This translator uses the Golden Parser code with enhancements to warn of malformed (yet legal) models. The translator supports user input to be able to select from the min-typ-max range of IBIS data. This program (IBIS2XTK) is available now and is distributed with XTK Crosstalk and transmission line simulation tool kit. Tag-line: Quad Desgin is a leading supplier of Signal Integrity and Timing tools for high speed digital designs. Quantic Laboratories, Inc. Contact: Mike Ventham Email: ventham@quantic.mb.ca Phone: (204) 942-4000, Fax: (204) 957-1158 Address: 12th Floor, 191 Lombard Ave Winnipeg, Manitoba, R3B 0X1 Canada Support: Quantic provides an IBIS reader (based on the Golden Parser) that will read IBIS models and automatically generate data files for Phidias (our graphical VI curve device modellor) and database files that associate the component definitions with the pin models. From Phidias, both SPICE models for PCB Greenfield (our pre and post layout transmission line simulator) and models for BoardScan, (our PC board screener for signal integrity and crosstalk problems) can be created. This is available now for Quantic customers. Tag-line: Quantic Laboratories Ltd has been the leading supplier of field solvers and signal integrity tools since 1983. This expertise has now been extended to Electromagnetic Compatibility (EMC) tools. Symmetry Design Systems, Inc. Contact: Andy Hughes Email: andy@symmetry.com Phone: (415) 949-9600, Fax: (415)-949-0831 Address: 477 S. San Antonio Rd. #200 Los Altos, Ca. 94022 Support: Symmetry provides IBIS modeling tools and services. Symmetry's modeling tool MODPEX can create IBIS models based on measured device characteristics or data sheet information. MODPEX can translate IBIS models to SPICE descriptions for testing and documentation or translate SPICE models to IBIS. Tag-line: Symmetry is a dedicated supplier of tools and services for creating, testing, and documenting SPICE and IBIS component models for electronic system design. Synopsys Inc. (Logic Modeling Group) Contact: Bill Lattin Email: billl@lmc.synopsys.com Phone: (503) 690-6900, Fax (503) 690-6906 Address: 19500 NW Gibbs Dr. Beaverton, OR 97075 Support: None at this time Tag-line: Texas Instruments Contact: Bob Ward Email: bward@neosoft.com Phone: (713) 274-4146, Fax (713) 274-3911 Address: P.O. Box 1443, M/S 631 Houston, TX 77251 Support: TI has a three-pronged attack on IBIS support. TI is working on a scheme to automatically generate IBIS models from TI Spice simulations (TI's proprietary Spice dialect), on an automatic means to generate C code to be linked in to TI Spice as a User Defined Element from an IBIS model, and an automatic means to create the Spice equivalent of the IBIS model from the IBIS model specification. The latter method differs from the second in that it uses skeletonized Spice primitive elements in the form of a subcircuit, while the second actually generates C code and compiles it for dynamic linking. Tag-line: Thomson-CSF/SCTF Contact: Jean Lebrun Email: Phone: Address: Support: Tag-line: UniCAD Canada Ltd. Contact: Stephen Lum Email: lum@unicad.com Phone: (613) 596-9091 Ext. 321 Address: 2745 Iris Street Pinecrest Office Park Ottawa, Ontario K2C 3V5 Support: UniSolve, a concurrent engineering workbench currently supports IBIS v1.1 model files in native mode for signal integrity analysis. Support for IBIS v2.1 is planned for early 1995. Tag-line: UniCAD, INC. provides software used in the layout and analysis of printed circuits and multichip modules. It provides the only available concurrent Computer Aided Analysis (CAA) environment used to simultaneously monitor Emissions, Digital Signal Integrity, Analog Signal Integrity, Thermal, and Reliability throughout the design layout process. Zeelan Technology, Inc. Contact: Hiro Moriyasu, George Opsahl Email: zeelan@netcom.com Phone: (503) 520-1000 Address: 10550 SW Allen Blvd. Beaverton, OR 97005 Support: Zeelan Tech. provides a modeling service that characterize and creates models conforming to the IBIS format. Zeelan Tech. MasterModel(TM) models are created from measurements of physical devices using a tightly controlled high-frequency fixture and modeling system. These models closely represent actual device behaviour when used in simulation. Tag-line: Zuken-Redac Contact: John Berrie Email: johnb@redact.co.uk Phone: +44 684 294161, Fax: +44 684 299754 Address: Tewkesbury Gloucestershire GL20 8QL, England Support: Work is in progress to enable use of IBIS models in native format for Redac High-Performance Engineering and EMC Adviser products. In addition, integration with Quad Design and Quantic products provides the stated level of support provided by these companies. Tag-line: Zuken-Redac is a world leader in design automation, providing open, leading technology, standards-based CADCAM solutions. ============================================================================ EIA/Electronic Information Group Contact: Patti Rusher Email: Prusher@eia.org Phone: (703) 907-7545. Fax: (703) 907-7501 Address: 2500 Wilson Blvd. Arlington, VA 22201 From bob@icx.com Tue Jul 25 12:42:40 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA15108; Tue, 25 Jul 95 12:42:40 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 25 Jul 95 12:35 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 25 Jul 95 12:38 PDT Message-Id: Date: Tue, 25 Jul 95 12:38 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org, mellitz@eagle.ColumbiaSC.NCR.COM Subject: Re: SPICE to IBIS Richard: I am not sure I understand fully the problem, but here is an attempt at some answers. Regarding the I/O pin in output mode, controlled by an "input" which itself is an internal output, you somehow may have to break the connection for the internal_data_out_pin inside the subcircuit so that this node is just an input connection. Then a phantom input can be created, but would not show up in the IBIS model if the "**NoModel" option is used with an artifical pin number. The "**NoModel" option was created for this type of problem where the external pin modeled by a Spice circuit is controlled by an internal input. The syntax for the I/O pin would reference this internal pin number as the "input_pin". Regarding the second point where min (or weak, slow) and max (or strong, fast) process models are available, s2ibis to was not set up to deal with this very practical problem. IBIS itself does not put constraints on the stategy. Currently s2ibis could be used in a cumbersome manner by using the **Iterate option. First the deck would be set up with the "typ" models and executed. Then the "min" *.spi files would be edited by substituting the "min" models. Similarly for the "max" *.spi files. These modified files would be executed manually to produce *.out files. Then s2ibis is reinvoked to generate the IBIS file. The **Iterate option prevents generating new *.spi and *.out files where *.out files already exist. An updated version of s2ibis for version 1.1 is planned to have an option that will support separate "min", "typ" and "max" Spice models. When this is implemented, you will not need to do any manual execution. Bob Ross, Interconnectix, Inc. > Hi All, > I'm a having a bit of difficulty with my understanding of the syntax for s2ibis. > I don't seem to understand how the [pin] syntax ties into the SPICE > model. Its not in the docs I have. > Take a simple example. > For a single transceiver (I/O). I would have 2 pins, power, ground and one > spice model. Lets ignore package parasitics for now. > Say my SPICE subcircuit looks like > .SUBCIRCUIT MYIO internal_data_out_pin io_pin VDD VSS > ... > i.e. > |\ > ____| \_____ > | / > |/ > internal_data_out_pin io_pin > How do I tell s2ibis that the internal_data_out_pin is used for controlling > Vol pull up data and Voh pull down data when io_pin is an output? > How can I tell s2ibis to use a particular CMOS model (representative of > process) to be associated with a certain temperature at a specified > voltage. It would seem I would need to do this to get accurate min/max > numbers. > --------------------------------------------------------------------- > Richard Mellitz | > AT&T | > Global Information Solutions | richard.mellitz@columbiasc.attgis.com > 3325 Platt Spring Road | Phone: (803)-939-6240 > West Columbia, SC 29170 | Fax: (803)-939-7317 > --------------------------------------------------------------------- From hoang@msai.com Tue Jul 25 19:38:51 1995 Return-Path: Received: from reggae.ncren.net by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17712; Tue, 25 Jul 95 19:38:51 PDT Received: from msaifw.UUCP by reggae.ncren.net (5.65/tas-reggae/may94) id AA19004; Tue, 25 Jul 95 22:31:37 -0400 Received: from sbedrock.msai.com (shared) by msaifw.msai.com (4.1/fw-version 2.7) id AA29281; Tue, 25 Jul 95 15:55:58 EDT Received: from roadrunner.msaiasic by sbedrock.msai.com (4.1/mh-version 2.4) id AA26630; Tue, 25 Jul 95 15:55:57 EDT Date: Tue, 25 Jul 95 15:55:57 EDT From: hoang@msai.com (Hoang Nguyen) Message-Id: <9507251955.AA26630@sbedrock.msai.com> To: ibis@vhdl.org Subject: s2ibis Hello, We're trying to interface s2ibis with our internal Spice simulator. However, we got DC conversion failure at low temp. The pull-up, pull-down spice model is temperature specific, i.e., for each pull-up and pull-down, we have three different models at min, typ, and max temp. Can the current s2ibis associate each temp model in its translation ? Will the new s2ibis version include this? Or do we have to obtain a temp-independent model? Thanks in advance for all your responses. Regards, Hoang Nguyen hoang@msai.com Mitsubishi Semiconductor America, Inc. Three Diamond Lane Durham NC 27704 From bob@icx.com Wed Jul 26 08:27:22 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA28846; Wed, 26 Jul 95 08:27:22 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 26 Jul 95 08:20 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 26 Jul 95 08:23 PDT Message-Id: Date: Wed, 26 Jul 95 08:23 PDT From: bob@icx.com ( Bob Ross) To: hoang@msai.com, ibis@vhdl.org Subject: Re: s2ibis Hoang: Because devices are often characterized using separate "min", "typ", and "max" models in Spice, and because this request is a common one, I think that s2ibis for Version 2.1 should have the mechanisms for accepting separate models for the "min", "typ" and "max" columns. This would solve your problem because the "min" model would be the low corner model (low temperature model for TTL, high temperature model for CMOS), and the "max" model would be the opposite. An update to s2ibis for Version 1.1 being considered may also to allow seperate Spice models for the different columns. Currently, however, the way to get what you want is hand edit the Spice decks for the min and max models and execute them separately to create new *.out files. Then, using the **Iterate option, create the IBIS model. Bob Ross, Interconnectix, Inc. > Hello, > We're trying to interface s2ibis with our internal Spice simulator. However, > we got DC conversion failure at low temp. The pull-up, pull-down spice model > is temperature specific, i.e., for each pull-up and pull-down, we have three > different models at min, typ, and max temp. Can the current s2ibis associate > each temp model in its translation ? Will the new s2ibis version include this? > Or do we have to obtain a temp-independent model? > Thanks in advance for all your responses. > Regards, > Hoang Nguyen > hoang@msai.com > Mitsubishi Semiconductor America, Inc. > Three Diamond Lane > Durham NC 27704 From sung.oh@tempe.vlsi.com Wed Jul 26 09:06:58 1995 Return-Path: Received: from relayhost.vlsi.com (tweety.vlsi.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29142; Wed, 26 Jul 95 09:06:58 PDT Received: from relayhost.tempe.vlsi.com ([180.0.26.63]) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id JAA19533; Wed, 26 Jul 1995 09:04:05 -0700 From: sung.oh@tempe.vlsi.com Received: from pcdmail.tempe.vlsi.com (hole.tempe.vlsi.com [134.27.89.15]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/032095) with ESMTP id JAA12038; Wed, 26 Jul 1995 09:06:18 -0700 Received: from sedona (sedona.tempe.vlsi.com [134.27.89.68]) by pcdmail.tempe.vlsi.com (8.6.9/Hub-Perlotto/032095) with SMTP id JAA01983; Wed, 26 Jul 1995 09:04:58 -0700 Received: by sedona id AA03022; Wed, 26 Jul 95 09:06:13 MST Date: Wed, 26 Jul 95 09:06:13 MST Message-Id: <9507261606.AA03022@sedona> To: hoang@msai.coom Subject: Re: s2ibis Cc: ibis@vhdl.org Hoang: You can change s2ibis source program so that the TEMP cards are set at different temperature. In the source code, models.c, there are statements which set the spice TEMP card. Regards, Sung Oh VLSI Technology, Inc. ----- Begin Included Message ----- From hoang@msai.com Tue Jul 25 19:53 MST 1995 Date: Tue, 25 Jul 95 15:55:57 EDT From: hoang@msai.com (Hoang Nguyen) To: ibis@vhdl.org Subject: s2ibis Content-Type: text Content-Length: 605 X-Lines: 18 Hello, We're trying to interface s2ibis with our internal Spice simulator. However, we got DC conversion failure at low temp. The pull-up, pull-down spice model is temperature specific, i.e., for each pull-up and pull-down, we have three different models at min, typ, and max temp. Can the current s2ibis associate each temp model in its translation ? Will the new s2ibis version include this? Or do we have to obtain a temp-independent model? Thanks in advance for all your responses. Regards, Hoang Nguyen hoang@msai.com Mitsubishi Semiconductor America, Inc. Three Diamond Lane Durham NC 27704 ----- End Included Message ----- From bob@icx.com Wed Jul 26 09:07:26 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29143; Wed, 26 Jul 95 09:07:26 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 26 Jul 95 09:00 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 26 Jul 95 09:03 PDT Message-Id: Date: Wed, 26 Jul 95 09:03 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: EIA IBIS MINUTES JULY 21, 1995 DATE: July 26, 1995 SUBJECT: 7/21/95 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS: AT&T Global Info Solutions Dave Moxley Cadence Design Sandeep Khanna, C. Kumar* Contec CAE, Ltd. Dileep Divekar* HyperLynx Kellee Crisafulli* INCASES Werner Rissiek, Olaf Rethmeier Intel Corporation Stephen Peters*, Will Hobbs, Arpad Muranyi*, Derrick Duehren Interconnectix, Inc. Bob Ross* Meta-Software Les Spruiell, Mei Wong, You-Pang Wei, John Sliney Motorola Ron Werner National Semiconductor Syed Huq*, Atul Agarwal, Cheng-Yang Kao NEC Hiroshi Matsumoto Quad Design Jon Powell* Quantic Labs Mike Ventham Texas Instruments Bob Ward Thomson-CSF/SCTF Jean LeBrun UniCAD Canada Ltd. Stephen Lum Zuken-Redac John Berrie OTHER PARTICIPANTS: ARPA Randy Harr Anacad Steffen Rochel Ansoft Henri Maramis Atmel Corporation Dan Terry Cadlab Ralf Bruning Digital Equipment Corp. Barry Katz EIA Patti Rusher High Design Technology Michael Smith, Dr. Ing. Cosso Hewlett Packard Tom Langdorf, Karl Kachigan, Henry Wu IBM Jay Diepenbrock Integrated Silicon Systems Eric Bracken Intergraph Ian Dodd, David Wiens, Walter Katz IntuSoft Charles Hymowitz LSI Logic Corp. Satish Pratadneni Mentor Graphics Ravender Goyal, Greg Doyle MicroSim Arthur Wong North Carolina State U. Steve Lipa, Michael Steer* OptEM Engineering, Inc. Benny Leveille, Ken Ehn Pacific Numerix Paul K. U. Wang Symmetry Martin Walker Synopsys, Logic Modeling G. Bill Lattin VLSI Dick Ulmer*, Sung Oh* Zeelan Technology George Opsahl, Hiro Moriyasu In the list above, attendees at the meeting are indicated by *. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 8/11/95 (916) 356-9999 1-3150 8492193 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS, ANNOUNCEMENTS Bob Ward has left TI, so a new representative is needed. AR - TI supply a new representative. MINUTES REPORT, MISC. Minutes of 6/30/95 have these corrections: correction of spelling of Sung Oh of VLSI, correction of VLSI division name to Personal Computer Division, and change of Contec to Contec CAE, Ltd. AR - Bob Ross will make roster change for Contec CAE and request Roster update information from VLSI - [DONE] OPENS FOR NEW ISSUES Standardizing on Unix convention on vhdl.org text files was raised by Arpad Muranyi. Michael Steer indicated that that was the convention used for all models, but not all files have been converted in other subdirectories such as those for the IBIS 2.1 manual. AR - Michael Steer make a pass at converting vhdl.org text files to Unix convention. (AR taken by Bob Ross below) (AR - Bob Ross will take the AR and convert all *.txt files encountered with DOS convention to Unix Convention - [DONE] for Ver2_1.txt and ver2.0 and ver2.1 directories) PRESS UPDATES IBIS mention by Savantage product highlights in Electronic Products, July 1995 pg. 61. IBIS mention in "Delivering the High-Speed Clock: It's Not Easy To Be On Time," EDN, July 6, 1995, pg 44. Extensive IBIS mention and EIA IBIS discussion by Meta-Software in Design Software Section of Electronic News, July 17, 1995, pg. 46 which included a Meta I/O announcement of a product which provides IBIS translations to/ from Spice. NEW MODELS Two new models previously submitted by National for DRAM controllers have been put in vhdl.org Kellee Crissafulli reported that Xilinx is still considering putting their IBIS models on vhdl.org. They are available by direct contact at this time. Dick Ulmer reported that VLSI has not made a decision regarding putting models under development on vhdl.org. They may want to control the availability on a selective basis. MODEL TRACKING Tracking of model usage by companies such as National who have submitted models was continued from last meetings discussion. Michael Steer said he would work with Steve Lipa to investigate an set up a method to gather access statistics and report back to the model provider on a monthly basis. Who uses the models may not be clear since the anonymous password entry may not give full information. AR - Michael Steer (with Steve Lipa) work with systems administrators on vhdl.org to set up a model access usage system for reporting back statistics of model access to the model providers. MODELS UNDER NDA Syed Huq wants to post the availability of some IBIS models that are available on a restricted basis or by NDA. Michael Steer indicated that the process could done by E-mail rather than the more formal process as documented in PROTOCOL.TXT under /pub/ibis/models in vhdl.org. Jon Powell suggested that the information be contained in a file such as .txt or .nda so that one can list all the models in a directory by extension. The .ibs would remain as actual IBIS models. All information will be presented in the 00Readme file and and also will be in the text information file(s). AR - Michael Steer will post a process for submitting information on models that are available on a restricted basis. As a reminder, the best method to submit models to vhdl.org is to submit them directly to Michael Steer (mbs@ncsu.edu). ibis-librarian@vhdl.org mails the file to Michael. EIA IBIS Status Dick Ulmer indicated that VLSI sent a Purchase Order for EIA for membership and parser. [Received by EIA, so VLSI is now a Voting Member] There was no Treasurer's report or Ballot update. AR - Jon Powell work with Patti Rusher concerning permission letter for company logos. EIA World Wide Web is running. Syed Huq is testing using the EIA IBIS logo used for the IBIS Spoken Here signs to test the Home Page. The committee approved using the logo and also using the EDN article for Web. AR - Stephen Peters will work with Will Hobbs (when he returns from vacation) to get the text of the IBIS article to Syed Huq. Also, Syed is collecting FAQ (Frequently Asked Questions) for the Web and will be putting them on the reflector. Michael indicated information on posting models would be an appropriate FAQ. Kellee suggested a listing of models. Some information should be stored at one source and referenced by pointers rather than duplicated several places for maintainability and accuracy. One link would be to source material in /pub/ibis on vhdl.org. The EIA web site is up and is www.eia.org/eng Under this is a list of different standards. IBIS will be accessed by searching for IBIS or by selecting EIA 656 when fully functional. All information will be approved by the IBIS Forum prior to adding to the Web and also must pass through EIA legal review. AR - Syed Huq post FAQ so that they can be approved at Forum meetings. Syed will provide html translation and submit the information to EIA system administration who have write access to be put on the EIA Web. GOLDEN PARSER UPDATE Bob Ross indicated that additional work has been agreed upon and is progressing toward finishing the ibischk2 parser. The Beta 7.1 release is very clean and does not fail on ibis compliant syntax. The additions are for completeness on error checking. No estimated date for completion and redistribution is available at this time. [Update - estimate Aug 1 for completion.] S2IBIS 2.1 Michael Steer reported on the s2ibis version 2.0 progress. It is command command language based (versus interpreter) and is using the *.h files of ibischk2. So it parses initially the s2ibis input file first and writes to the data structure. The complexity IBIS Version 2.1 dictates this approach. The analysis routines of Version 1.1 parser are planned to be included. A working prototype is expected in several weeks with a Beta version available in about 4 weeks. Full *.pkg modeling will not be supported. Arpad Muranyi raised the question of aligning the VT curves. This may not be an issue if they are all aligned with respect to a time = 0 reference. We would have to review this to see if there is a problem. S2IBIS 1.1 Bob Ross mentioned a problem that exists in the [Pullup] data in the region below ground due to what appears to be an incorrect implementation of the planned extrapolation region. He has been in communication with Steve Lipa. The plan is to ask for a correction release S2IBIS 1.2 and also have the correct algorithm in S2IBIS 2.1. The forum appeared in agreement in this approach. AR - Bob Ross communicate desired action to Steve Lipa - [Done]. COOKBOOK AND OVERVIEW UPDATE Kellee Chrisafulli stated little response on requests, but has been capturing tidbits of information off the reflector. His view is that some Semiconductor companies which have been producing models might pick up the project. Syed Huq of National said he could work with Kellee on measurement based issues. Stephen Peters may be available in several months to help since he will be working on an internal Intel document on IBIS. The cookbook could use Version 1.1 as a basis. One section might address FAQ. BIRD29.2, BANDED MATRICES BIRD29.1 was approved by the Forum at last meeting. BIRD29.2 was proposed as a minor addition to resolve an IBISCHK2 error checking issue that was raised by Ron Neville. It introduces a maximum band size limit for cases where the band is wrapped around to prevent the possibility of specifying the same entry in two locations and possibly differently. This addition is by just 4 additional clarification lines. BIRD29.2 was approved by vote by the Forum. AR - Bob Ross sends to EIA this BIRD as a comment to the EIA IBIS ballot from the committee. Also, Bob Ross confirm with Ron Neville that this BIRD has been approved for implementation into IBISCHK2. [DONE] BIRD27 NEW KEYWORD FOR DIFFERENTIAL I/O This was deferred since Bob Ward is no longer at TI as indicated above. AR - Bob Ross submit BIRD27.1 BIRD28.1 PACKAGE MODEL EXTENSION / PHYSICAL EXTENSIONS The discusson was opened by Stephen Peters, and based on the consideration of example sent out and commented upon. One concludion was that the syntax of grouped lengths had problems. The original variable length syntax or some other approach has more promise as an approximation approach. This is still an open issue and one of practical concern. AR - Stephen Peters will develop and post an updated BIRD28.2 reflecting some additional insites. The discussion merged with the physical discription approach as one way to give a more detailed description. Action items are: AR - Kellee Crissfulli create and post an example of a physical description. AR - Arpad Muranyi contact Raj Mitra at U of Illinois for possible format input and present any useful results. AR - Jon Powell investigate and report on EDIF formats and field solver data bases and consideration with respect to geometric descriptions. DIODE MODELING This issue has been put on hold and was raised here to see what progress has been made. Jon Powell (may) have some work that he can share and will report it or make it available. There was brief discussion of measurement and of whether the turn off or turn on time were the major factors. AR - Stephen Peter talk to Tim Schreyer for progress since the issue is becoming visible again. PIN PROGRAMMABLE BUFFER STRENGTHS Arpad Muranyi opened this issue for discussion and Dick Ulmer of VLSI indicated this is an important issue with them. A typical part may have buffer selections at two strengths and for 5V and 3.3V supplies giving four choices. Currently the customer needs to edit in the name of the buffer being used in IBIS files. Arpad listed several approaches and several more were presented during the discussion: (1) Include all buffers, and use an editor to insert the name into the [Pin] list for the strength desired - a tedious editing process. (2) List all acceptable buffers for each pin - this enlarges the [Pin] file, and there has to be a selection mechanism. (3) Introduce a new keyword which supports a model with multiple VI curves and Ramp (or VT) curves in the model - need a selection method. (4) Use #Define syntax to compile the IBIS model beforehand with the proper buffers based on a model with multiple choices. There are various C tools that can do this. One issue is if models can be changed dynamically such as might be done to optimize a driver for a certain net. (5) Use a "[Multiple Model]" syntax under which several fully defined [Models] can be used to define for a particular name the available model strengths (or even different models) - There is a model selection issue. One question/concern by Dick is if one of the models is the default model. AR - Arpad Muranyi write up a proposal (EGG) reflecting further thoughts. TTL DRIVERS Jon Powell raised as a new issue that CMOS and TTL drivers may need to be processed differently to reach the half-on/half-off state using VI data. This may requiring keywords for identifying the different technology. AR - Jon Powell supply more information and possibly an egg for discussion. NEXT MEETING: It is set on Friday, August 11, 1995 with Will Hobbs moderating. ============================================================================== NOTES IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210 will_hobbs@ccm.jf.intel.com Modeling Manager, Intel Corp. 2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Bob Ross (503) 603-2523, fax (503) 639-3469 bob@icx.com 10220 SW Nimbus Ave, K4, Portland, OR 97223 To become a voting member of the EIA IBIS Open Forum, send email to ibis-info@vhdl.org for instructions. If you want to join the e-mail reflector (ibis@vhdl.org), send e-mail to the IBIS secretary at ibis-request@vhdl.org. Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an email request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From huq@rockie.nsc.com Wed Jul 26 11:24:30 1995 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04120; Wed, 26 Jul 95 11:24:30 PDT Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA20157 for ibis@vhdl.org; Wed, 26 Jul 95 11:17:59 -0700 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA02475 for ibis@vhdl.org; Wed, 26 Jul 95 11:17:58 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA18207; Wed, 26 Jul 95 11:20:15 PDT Date: Wed, 26 Jul 95 11:20:15 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9507261820.AA18207@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS FAQ for the homepage Cc: huq@rockie.nsc.com IBISgurus, As discussed earlier, we are in the process of putting together a listing of IBIS FAQ's for the EIA IBIS homepage. I am attaching the initial listing of Q's and A's and I will need feedback, comments and approval. We can change the order or the contents of each FAQ and we may also add more to this list. Please post your comments, changes to the reflector so it can be approved. I would like to receive all feedbacks/comments/changes BEFORE the Aug11th IBIS teleconference so we can vote on this. Best Regards, Syed National Semiconductor. ------------------------------------------------------------------- A compilation of IBIS related FAQ(Frequently Asked Questions). Issues related to Modeling, Simulations, Support, Features and others are addressed here. 1.0 What is this IBIS stuff anyhow ? IBIS(Input Output Buffer Information Specification) is a method of providing the Input/Output device characteristics through V/I data without disclosing any circuit/process information. It can be thought of as an Analog Behavioral Modeling Specification that can be used to model almost 99% of any semiconductor in the Industry today. IBIS is mostly used for transmission line analysis as well as Signal Integrity analysis. 2.0 What is the "Golden Parser" ? The "Golden Parser" is a shareware used to parse the model file to check if the file conforms to the IBIS specification. All model files need to pass the parser before a model can be released on the Internet. 3.0 Where can I find the IBIS Golden Parser ? You may download a copy of the executable directly from vhdl.org(anonymous ftp site) under /pub/ibis/ibis_chk. To obtain a copy of the source code, send E-mail to: ?? 4.0 Where can I find available IBIS models ? All IBIS models released today resides in an anonymous ftp site at vhdl.org. You may ftp to this site and change directory to /pub/ibis/models to find all models. There are multiple ways of downloading these models from the Internet: Using Mosaic: URL: http://www/vhdl.org/pub/ibis click on 'models' Using FTP: ftp to vhdl.org or ftp to 198.31.14.3 and login as anonymous password can be your E-mail id change dir using cd to /pub/ibis/models use ftp command 'get' to copy files. Using Dial-up Modem: Use any communication software on your PC (Ex. QuikLink, Procomm, LapLink. Terminal(Windows) etc) Dial: (415)335-0110 Login as guest Password: just hit return You will see the Welcome message from VHDL and it will prompt for password again. Enter your E-mail id this time Typical Modem setup: Baudrate=upto 14.4 Databit=8 Stop=1 Parity=None Flow=Xon/Xoff You can download files using "kermit","zmodem" or "sz" etc 5.0 Can IBIS model best case, worst case models ? Yes, by using the min, max current with the proper min, max ramp rates, the Best, Typical and Worst case can be modeled. 6.0 Can IBIS model SSO(Simultaneous Switching Output) ? IBIS as a model, has all the parameters required to model an SSO event. These are mainly the package inductance parameters and other associated parasitics. Modeling an SSO event is more of a simulator issue than IBIS. 7.0 Why do we need to sweep to 2Vcc ? IBIS models are meant to work on any simulator platform, SPICE or non-SPICE. But on a SPICE platform, the simulation might not converge if the end points are not specified. Most non-SPICE based simulators will do their own extrapolation to get to the end point. So, to make the IBIS model function on all platforms, that data needs to sweep to the full IBIS range, for example 2Vcc. 8.0 Can IBIS model GTO(Gradual Turn On) or Slew rate controlled outputs ? IBISv2.1 can model RTC(Rise Time Controlled), GTO(Gradual Turn on) or Slew rate controlled outputs. These are defined under [Rising Waveform] and [Falling Waveform] keywords. See IBISv2.1 specification for more details. 9.0 Can IBIS model ground bounce ? Yes, IBIS contains the the package parasitic information necessary to simulate ground bounce. Even though the data is available within the model file, not all simulators may be able to use it to simulate ground bounce. Refer to your respective simulator for support. 10.0 Can IBIS provide timing information ? ex.propdelays, skew etc No, the present IBISv2.1 does not provide timing information. 11.0 Can IBIS model be used to measure propagation delays ? IBISv2.1 does not support measurement of propagation delays. IBIS is mainly used to simulate transmission lines and analyze signal integrity issues. 12.0 What type of Input/output structures are supported by IBIS ? Following is a list of the output model types supported by IBISv2.1: Input, Input_ECL, Output_ECL, I/O_ECL, I/O, I/O_open_drain, I/O_open_sink, I/O_open_source,Input_ECL, I/O_ECL, Terminator, Output, 3-state, Open_sink, Open_drain, Open_source Refer to IBISv2.1 for a full explanation of the Input/Output structures. 13.0 How do I release an IBIS model to the Internet ? North Carolina State University handles all IBIS model releases to the Internet. Follow the procedure described below to release a model: PROCEDURE FOR SUBMITTING A MODEL TO THE IBIS MODEL LIBRARY January 6, 1994 Michael Steer IBIS Model Librarian Department of Electrical and Computer Engineering North Carolina State University Raleigh, NC 27695-7911 phone: +1-919-515-5191 fax: +1-919-515-3027 email: mbs@ncsu.edu (preferred means of communication) Vendors and others are encouraged to submit IBIS models to the IBIS model library. The IBIS librarian maintains the IBIS models stored on vhdl.org in the directory /pub/ibis/models . 1. Before submission models must be readable by the Golden Parser with out errors or warning messages being generated. 2. A submission should consist of the following: a. A readme file ( named README.TXT ) including the following Name of Person Submitting: XXXXXXXXXXXX Address: XXXXXXXXXXXXXXXXXXXXXXXXXXXX Affiliation: XXXXXXXXXXXXXXXXXXXXXXXXXXXX E-Mail: XXXXXXXXXXXXXXX Telephone Number: XXXXXXXXXXXXXXXXXXXXXXX Fax Number: XXXXXXXXXXXXXXXXXXXXXXX Suggested Directory Structure XXXXXXXXXXX Structure for models b. A Model Transfer Agreement Use the sample below) must be signed and mailed to the IBIS librarian < mbs@ncsu.edu >. The model transfer agreement must be MAILED to Dr. Michael Steer Attn: IBIS Department of Electrical and Computer Engineering North Carolina State University Raleigh, NC 27696-7911 The above address is good for the post-office, Federal Express, Airborne, UPS etc. even though there is no street address. The model check-in procedure will not be finalized until this agreement has been received by the IBIS librarian. c. All files should be in a single file before emailing to the IBIS librarian. Use one of the following four methods: 1. [ gnu tar AND ( uuencode OR mmencode ) ] 2. [ tar AND compressed AND ( uuencode OR mmencode ) ] 3. [ zip AND ( uuencoded OR mmencode'd ) ] 4. [ zip ] Note that zip'ing alone may result in problems due to non-ascii characters. You can obtain suitable programs for DOS as follows: ftp oak.oakland.edu login as anonymous binary // to put in binary transfer mode cd /pub/msdos/zip get pkz204g.exe // the zip archive create/extract program. Run this program to generate the required utilities cd /pub/msdos/compress get comp430d.zip // Unix-compatible 16bit compress/uncompress utility cd /pub/msdos/decode get qux01_91.zip // UUencode/UUdecode quit // finish up Expect an acknowledgement within two days. 3. When models are received: a. The following will be added to each IBIS file if not already present: [Disclaimer] IBIS Open Forum disclaims all warranties. See DISCLAIM.TXT in vhdl.org:/pub/IBIS/models for the full disclaimer. b. The IBIS models will be checked with the Golden Parser and if they parse successfully they will be accepted. 4. The IBIS models will be treated as confidential until they are publically released. When new models are added an announcement will be made. ============================================================================== IBIS Model Transfer Agreement The under-signed submitter has submitted the following models to the IBIS library (list model filenames) ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ The submitter authorizes inclusion of the submitted models in the model library. The model files will be provided as is except for the addition of the following statement to each file: [Disclaimer] IBIS Open Forum disclaims all warranties. See DISCLAIM.TXT in vhdl.org:/pub/IBIS/models for the full disclaimer. If the models were written as a work made for hire in the course of employment, the Work is owned by the company/employer which must sign this agreement in the space provided below. Submitter's Signature and Date _______________________________ Typed or Printed Name and Title _______________________________ Institution or Company _____________________________________________ Authorization (if required) _______________________________ Typed or Printed Name and Title _______________________________ Please Check ___________ ___ Submitter's Own Work | | |__| ___ Work done for Hire | | |__| 14.0 It is rightly pointed out that the pulldown and pullup characteristic for tristate outputs may be non-monotonic. The standard says that this can happen in at most one place. The i-v characteristic may then locally have a negative resistance. Will this not pose a problem to simulators ? The IBIS standard specifies that the pullup and pulldown curves contain pullup and pulldown data ONLY, i.e. in the region where the clamp diodes are active the current due to the clamp diodes must be subtracted from the pullup/pulldown current. This is where the non-monotonic curves come from -- at the extremes of the I/V curves where you are subtracting a large diode current from the combined diode/on-state-IV curve. In practice, a simulator sums the two currents together (power clamp and pullup or gnd clamp and pulldown) thereby making the result monotonic. 15.0 Is there a provision for specifying a pad or die resistance i.e R_comp in addition to C_comp? No. The effects of a pad or die resistance are accounted for in the I/V curves. 16.0 The standard does not explicity specify the nature of the input ramp in obtaining ramp rates. What should be the input rise time as well as the high and low values of the input pulse? IBIS does not provide an Input pulse specification for deriving Ramp rates (and Waveform Tables). A reasonable guideline is to mimic actual conditions for which the device would be used. Therefore it is probably better not to mandate a specific condition. The voltage swing should be appropriate for the technology, e.g., 0 to 5V for CMOS and about 0 to 3V for TTL. A signal faster than the expected Ramp rates is my preference, although a case could be made to provide a response that mimics the data book input ramps specified for timing tests.Possibly a 50 Ohm series resistance approximating the pulser source impedance and trace environment to the device input should be included. However, since the actual thresholds are narrow (several 100 mV), the Ramp rates and Waveform tables should not differ significantly for any reasonable, appropriate Input. END From jeffbatt@mdhost.cse.TEK.COM Thu Jul 27 09:48:25 1995 Return-Path: Received: from inet1.tek.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA21420; Thu, 27 Jul 95 09:48:25 PDT Received: by inet1.tek.com id ; Thu, 27 Jul 1995 09:42:07 -0700 Received: from tektronix.tek.com(134.62.48.24) by inet1 via smap (V1.3) id sma017991; Thu Jul 27 09:41:48 1995 Received: from mdhost.cse.tek.com (tekadm1.cse.tek.com) by tektronix.TEK.COM (4.1/8.2) id AA13584; Thu, 27 Jul 95 09:41:04 PDT Received: from tekgp4.CSE.TEK.COM by mdhost.cse.tek.com (4.1/8.0) id AA06560; Thu, 27 Jul 95 09:41:26 PDT Received: by tekgp4.CSE.TEK.COM (4.1/8.0) id AA07618; Thu, 27 Jul 95 09:41:25 PDT Date: Thu, 27 Jul 95 09:41:25 PDT From: jeffbatt@mdhost.cse.TEK.COM Message-Id: <9507271641.AA07618@tekgp4.CSE.TEK.COM> To: ibis@vhdl.org Subject: SUBSCRIBE jeffbatt@mdhost.CSE.tek.com From jeffbatt@mdhost.cse.TEK.COM Thu Jul 27 10:26:40 1995 Return-Path: Received: from inet1.tek.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA21675; Thu, 27 Jul 95 10:26:40 PDT Received: by inet1.tek.com id ; Thu, 27 Jul 1995 10:20:28 -0700 Received: from tektronix.tek.com(134.62.48.24) by inet1 via smap (V1.3) id sma026917; Thu Jul 27 10:20:16 1995 Received: from mdhost.cse.tek.com (tekadm1.cse.tek.com) by tektronix.TEK.COM (4.1/8.2) id AA17408; Thu, 27 Jul 95 10:19:32 PDT Received: from tekgp4.CSE.TEK.COM by mdhost.cse.tek.com (4.1/8.0) id AA08964; Thu, 27 Jul 95 10:19:55 PDT Received: from localhost.TEK by tekgp4.CSE.TEK.COM (4.1/8.0) id AA09128; Thu, 27 Jul 95 10:19:54 PDT Message-Id: <9507271719.AA09128@tekgp4.CSE.TEK.COM> From: jeffbatt@mdhost.cse.TEK.COM To: ibis@vhdl.org Subject: SUBSCRIBE Date: Thu, 27 Jul 95 10:19:54 PDT Sender: jeffbatt@mdhost.cse.TEK.COM battlej@holmes.ece.orst.edu From bob@icx.com Thu Jul 27 18:37:46 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA25215; Thu, 27 Jul 95 18:37:46 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 27 Jul 95 18:31 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 27 Jul 95 18:33 PDT Message-Id: Date: Thu, 27 Jul 95 18:33 PDT From: bob@icx.com ( Bob Ross) To: huq@rockie.nsc.com, ibis@vhdl.org Subject: Re: IBIS FAQ for the homepage Syed: Great start on the Home page. Regarding Question 2, I think "shareware" is the wrong word and may even imply some privately developed code for which a voluntary contribution is requested. Rather, it is free, publically available executable code developed by contractors for the IBIS Open Forum. Bob Ross, Interconnectix, Inc. --------------- > 2.0 What is the "Golden Parser" ? > The "Golden Parser" is a shareware used to parse the model file to check if the > file conforms to the IBIS specification. All model files need to pass the parser > before a model can be released on the Internet. From slipa@eos.ncsu.edu Fri Jul 28 10:04:54 1995 Return-Path: Received: from mw7.ece.ncsu.edu (c11049-336dan.ece.ncsu.edu) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05488; Fri, 28 Jul 95 10:04:54 PDT Received: by mw7.ece.ncsu.edu (5.65/Eos/C-U-09Sep93) id AA20857; Fri, 28 Jul 1995 12:58:21 -0400 From: slipa@eos.ncsu.edu Message-Id: <9507281658.AA20857@mw7.ece.ncsu.edu> To: ibis@vhdl.org Cc: slipa@eos.ncsu.edu Subject: s2ibis v1.2 Date: Fri, 28 Jul 95 12:58:20 EDT Ibis Folks: I have placed an updated version of s2ibis, version 1.2 into the /pub/ibis/s2ibis directory at vhdl.org. The main reason for the new version is to fix a sign error (sorry about that) that was causing several points in each [Pullup] table to come out wrong. The new version also provides a simple mechanism for including different .MODELS for the typ, min, and max SPICE runs used to generate tables. Steve slipa@eos.ncsu.edu From 75131.1474@compuserve.com Fri Jul 28 10:08:47 1995 Return-Path: <75131.1474@compuserve.com> Received: from dub-img-2.compuserve.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05504; Fri, 28 Jul 95 10:08:47 PDT Received: by dub-img-2.compuserve.com (8.6.10/5.950515) id NAA00292; Fri, 28 Jul 1995 13:02:15 -0400 Date: 28 Jul 95 12:57:29 EDT From: "Tedd K. Stickel" <75131.1474@compuserve.com> To: IBIS reflector Subject: email list Message-Id: <950728165729_75131.1474_FHI62-1@CompuServe.COM> please add my name to your subscriber list. my address is 75131.1474@compuserve.com thanks, tedd From Lyndell_L_Asbenson@ccm.fm.intel.com Fri Jul 28 10:35:29 1995 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05682; Fri, 28 Jul 95 10:35:29 PDT Received: from relay.jf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #7) id m0sbtDW-000Ui4C; Fri, 28 Jul 95 10:28 PDT Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0sbtDW-000txMC; Fri, 28 Jul 95 10:28 PDT Received: by ccm.hf.intel.com (ccmgate 3.2 #2) Fri, 28 Jul 95 10:28:58 PDT Date: Fri, 28 Jul 95 10:25:00 PDT From: Lyndell L Asbenson Message-Id: To: ibis@vhdl.org Subject: Please corrent I am getting all kinds of requests to SUBSCRIBE people, Please correct this problem. Lyndell Lee Asbenson From huq@rockie.nsc.com Fri Jul 28 13:13:40 1995 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06701; Fri, 28 Jul 95 13:13:40 PDT Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA29152 for ibis@vhdl.org; Fri, 28 Jul 95 13:07:02 -0700 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA09125 for ibis@vhdl.org; Fri, 28 Jul 95 13:07:01 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA26826; Fri, 28 Jul 95 13:09:20 PDT Date: Fri, 28 Jul 95 13:09:20 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9507282009.AA26826@rockie.nsc.com> To: ibis@vhdl.org Subject: bidirec-3state model Hi, How do I define the model type for a bi-directional 3-state pin. I could use I/O but there is no defination for a I/O pin that can be tri-statable. Any suggestions.. Regards, Syed National Semiconductor From speters@ichips.intel.com Fri Jul 28 14:00:23 1995 Return-Path: Received: from hermes.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07040; Fri, 28 Jul 95 14:00:23 PDT Received: from ichips.intel.com by hermes.intel.com (5.65/10.0i); Fri, 28 Jul 95 13:52:53 -0700 Received: from xtg801 by ichips.intel.com (5.64+/10.0i); Fri, 28 Jul 95 13:52:47 -0700 Received: from localhost by xtg801.intel.com (4.1/10.0i); Fri, 28 Jul 95 13:52:47 PDT Message-Id: <9507282052.AA16879@xtg801.intel.com> To: huq@rockie.nsc.com Cc: ibis@vhdl.org Subject: bidirec-3state model Date: Fri, 28 Jul 1995 13:52:44 -0700 From: Stephen Peters Hello Syed: The a bi-directional pin is, by it's nature and function, assumed to be tri-stateable. The model type to use is 'I/O'. Regards, Stephen Peters Intel Corp. ------ Hi, How do I define the model type for a bi-directional 3-state pin. I could use I/O but there is no defination for a I/O pin that can be tri-statable. Any suggestions.. Regards, Syed National Semiconductor From Arpad_Muranyi@ccm.fm.intel.com Fri Jul 28 14:21:38 1995 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07169; Fri, 28 Jul 95 14:21:38 PDT Received: from relay.jf.intel.com by ormail.intel.com with smtp (Smail3.1.28.1 #7) id m0sbwfX-000UhOC; Fri, 28 Jul 95 14:10 PDT Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0sbwfW-000txWC; Fri, 28 Jul 95 14:10 PDT Received: by ccm.hf.intel.com (ccmgate 3.2 #2) Fri, 28 Jul 95 14:10:06 PDT Date: Fri, 28 Jul 95 14:03:00 PDT From: Arpad Muranyi Message-Id: To: huq@rockie.nsc.com, ibis@vhdl.org Subject: Re: bidirec-3state model Text item: Syed, As far as I understand, I/O is what you need to use. Input means there is only a receiver on that pin. Output means that there is only a driver on that pin, which is constantly driving either high or low. I/O means that there is a receiver and a driver on that pin, which only makes sense if the driver can be disabled or 3-stated so that the receiver can receive signals from other chips on the bus and not just from its own driver. 3-state means that there is only a driver on that pin, but because the device is used on a bus, where other devices are also driving, it must be able to float also, even though it never "receives" signals. What you are asking: "bi-directional 3-state" does not make sense to me in the above context. Am I missing something, or is my answer what you needed to know? Arpad Muranyi Intel Corporation ------------------------------------------------------------------------------- Hi, How do I define the model type for a bi-directional 3-state pin. I could use I/O but there is no defination for a I/O pin that can be tri-statable. Any suggestions.. Regards, Syed National Semiconductor Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: bidirec-3state model To: ibis@vhdl.org Message-Id: <9507282009.AA26826@rockie.nsc.com> From: huq@rockie.nsc.com (Syed Huq) Date: Fri, 28 Jul 95 13:09:20 PDT Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA26826; Fri, 28 Jul 95 13:09:20 PDT Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA09125 for ibis@vhdl.org; Fri, 28 Jul 95 13:07:01 -0700 Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA29152 for ibis@vhdl.org; Fri, 28 Jul 95 13:07:02 -0700 Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06701; Fri, 28 Jul 95 13:13:40 PDT Received: from vhdl.vhdl.org by hermes.intel.com (5.65/10.0i); Fri, 28 Jul 95 13 :12:10 -0700 Received: from hermes.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0sbvlT-000twhC; Fri, 28 Jul 95 13:12 PDT From jeffbatt@mdhost.cse.TEK.COM Fri Jul 28 16:36:52 1995 Return-Path: Received: from inet1.tek.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07997; Fri, 28 Jul 95 16:36:52 PDT Received: by inet1.tek.com id ; Fri, 28 Jul 1995 16:30:39 -0700 Received: from tektronix.tek.com(134.62.48.24) by inet1 via smap (V1.3) id sma021959; Fri Jul 28 16:30:31 1995 Received: from mdhost.cse.tek.com (tekadm1.cse.tek.com) by tektronix.TEK.COM (4.1/8.2) id AA17852; Fri, 28 Jul 95 16:29:36 PDT Received: from tekgp4.CSE.TEK.COM by mdhost.cse.tek.com (4.1/8.1) id AA09591; Fri, 28 Jul 95 16:30:09 PDT Received: from localhost.TEK by tekgp4.CSE.TEK.COM (4.1/8.0) id AA15667; Fri, 28 Jul 95 16:30:08 PDT Message-Id: <9507282330.AA15667@tekgp4.CSE.TEK.COM> From: jeffbatt@mdhost.cse.TEK.COM To: ibis@vhdl.org Subject: The Golden Parser Date: Fri, 28 Jul 95 16:30:08 PDT Sender: jeffbatt@mdhost.cse.TEK.COM I recently got a hold of the golden parser to check some ibis models. It would appear from the error statement that indeed the parser only works for version 1.1. Is this correct? If so, will there be an update? ---***Error Message Included***--- ibis_chk opad.ibs Checking opad.ibs for IBIS 1.1 Compatibility... ERROR (line 1) - Invalid IBIS Version ("2.1"). ABORTING!!! Errors : 1 File Failed: opad.ibs ---***End of Error Message***--- Jeff Battles jeffbatt@mdhost.CSE.TEK.COM battlej@holmes.ece.orst.edu Tektronix, Inc. / From scott@icx.com Fri Jul 28 16:49:02 1995 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA08062; Fri, 28 Jul 95 16:49:02 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 28 Jul 95 16:42 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 28 Jul 95 16:45 PDT Message-Id: To: jeffbatt@mdhost.cse.tek.com Cc: ibis@vhdl.org, scott@icx.com Subject: Re: The Golden Parser In-Reply-To: Your message of "Fri, 28 Jul 1995 16:30:08 PDT." <9507282330.AA15667@tekgp4.CSE.TEK.COM> Date: Fri, 28 Jul 1995 16:45:48 -0700 From: Scott Aron Bloom The 2.1 release is in final beta testing now. It should be any day now. Scott > > I recently got a hold of the golden parser > to check some ibis models. It would > appear from the error statement that indeed > the parser only works for version 1.1. > > Is this correct? > > If so, will there be an update? > > ---***Error Message Included***--- > ibis_chk opad.ibs > > Checking opad.ibs for IBIS 1.1 Compatibility... > > ERROR (line 1) - Invalid IBIS Version ("2.1"). ABORTING!!! > > Errors : 1 > > File Failed: opad.ibs > ---***End of Error Message***--- > > > Jeff Battles > jeffbatt@mdhost.CSE.TEK.COM > battlej@holmes.ece.orst.edu > Tektronix, Inc. > / From huq@rockie.nsc.com Mon Jul 31 09:01:44 1995 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12957; Mon, 31 Jul 95 09:01:44 PDT Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA26443 for ibis@vhdl.org; Mon, 31 Jul 95 08:54:57 -0700 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA14073 for Arpad_Muranyi@ccm.fm.intel.com; Mon, 31 Jul 95 08:54:55 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA21072; Mon, 31 Jul 95 08:57:16 PDT Date: Mon, 31 Jul 95 08:57:16 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9507311557.AA21072@rockie.nsc.com> To: Arpad_Muranyi@ccm.fm.intel.com Subject: Re: bidirec-3state model Cc: ibis@vhdl.org Arpad/Stephen, Thanks for your responses. An I/O type should work for my model. This device is a bi-directional transceiver and both ports can be disabled from the bus. Regards, Syed National Semiconductor