From owner-ibis  Fri Aug  9 14:44:36 1996
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Date: Fri, 09 Aug 1996 13:44:36 -0700
From: Jon Powell <jonp@qdt.com>
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Subject: 
        IBIS Meeting 8/16/96 
  Date: 
        Fri, 09 Aug 1996 11:30:12 -0700 
  From: 
        Jon Powell <jonp@qdt.com>
    To: 
        ibis@vhdl.org


IBIS Open Forum Meeting Agenda
                                for 8/16/96
 
                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   2-88344         6838524
 
 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into
the
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 

 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Ross
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell,
All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions
 
      IEC Express Funding Progress                            Rusher

      EE Times Article                                        Ross

      New Administrative Issues                               All

 8:35 Technical Discussion

      BIRD34.1 - STORED CHARGE EFFECT                         Ross

      BIRD35.1 - MULTI-STAGED OUTPUTS                         Ross
             
      BIRD36 - ELECTRICAL BOARD DESCRIPTION                   Peters

      BIRD37.1 - ENHANCEMENT TO THE PACKAGE MODEL SPEC.       Peters
                 (Vote)

      BIRD38 -  ABSOLUTE MAXIMUM VOLTAGE
Fitzpatrick

      EGG12 - SPECIFICATION ADDITIONS                         Ross, All

      EGG10 -  PARSER TESTS  1-5                              Rokusek

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off

From owner-ibis  Fri Aug  9 16:31:17 1996
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Date: Fri, 9 Aug 1996 18:23:29 -0500
From: omera@trailblazer.sps.mot.com (Ahmed Omer)
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To: ibis@vhdl.org
Subject: Dynamic Noise Immunity Spec.
X-Sun-Charset: US-ASCII

Hello Everyone
Below is my AR from the last meeting.
...

STATEMENT OF THE ISSUE
     
Currently, IBIS specifies input logic "low/high" DC voltages for 
input and I/O model-types (i.e. Vinl and Vinh).
  
This information does not specify the required time for a signal to 
stay at Vinl or Vinh before an input is sufficiently disturbed to 
cause a level switch.  Therefore, pulse amplitude Vs pulse width data is 
needed to complete the specification.  Figure 1 shows a generic plot of 
such data.

   
               ^
 	PULSE  |  *                      
	       |                                
	 A     |     
	 M     |    *
 	 P     |       
 	 L     |     *     Sufficient                              
 	 I     |              Energy                              
	 T     |       *
	 U     |        *
         D     |                         
	 E     |           *                        
	       |               *                      
	(V)    |                   *                   
	       |   Insufficient         *  * * * *  <- DC value
	       |                                         
	       |                                        
	       |-----+-----+-----+-----+-----+--------->    
               0    Tr    2Tr   3Tr   4Tr   5Tr

                          PULSE WIDTH (ns)               

                      Figure 1: Receiver Noise Tolerance
                      ----------------------------------

This is also referred to as dynamic noise immunity curve. To summarize the plot:
- Pulses with widths of 5 rise times (Tr) or more, DC value will causes 
  a receiver switch.
- Pulses with widths of less than 5Tr, amplitudes of larger than DC value 
  are necessary to cause switch.
- In the region below the curve, the receiver will not switch.
- In the region above the curve, the receiver will switch.


SUGGESTED SPECIFICATION

SUGGESTION A - Combine with Vinl and Vinh
A table of at least five data points should be provided with each Vinl and 
with each Vinh.  Each point is a pair of time and voltage values in the form
(t, v) where  Tr < t < 5Tr. Suggested format is shown below.

Vinl= xx.xx; Table: (tl1, vl1) (tl2, vl2) (tl3, vl3) (tl4, vl4) (tl5, vl5)
Vinh= xx.xx; Table: (th1, vh1) (th2, vh2) (th3, vh3) (th4, vh4) (th5, vh5)

SUGGESTION B - Use separate keyword
Keyword: [Dynamic Noise Immunity]
This keyword defines a table of voltage versus time points. The table 
contains three columns:
    1- time
    2- low voltage rise (volts above Ground)      
    3- high voltage drop (Volts below Power)   

Regards, Ahmed
|---------------------------------------+------------------------------------|
|Ahmed Omer                             | Advanced Interconnect Systems Labs |
|E-MAIL: omera@trailblazer.sps.mot.com  | Semiconductor Products Sector      |
|      : R28450@email.sps.mot.com       | M O T O R O L A, Inc.              |
|Phone:	 512-933-2247                   | 3501 Ed Bluestein Blvd  MDrop: F36 |
|Fax:	 512-933-5845                   | Austin, TX 78721                   |
|---------------------------------------+------------------------------------|

From owner-ibis  Fri Aug  9 18:04:42 1996
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Date: Fri, 09 Aug 1996 17:54:08 -0700
From: "D.C. Sessions" <dc.sessions@tempe.vlsi.com>
Organization: VLSI Technology Inc.
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Subject: Lies wrt clamp currents
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Harish Patel (who is generating IBIS models for VLSI's standard
cell products) raised an interesting point.  The clamp currents
that we extact or extrapolate from lab data go to totally
irrelevant values at +2Vdd or -Vdd, and probably aren't very
accurate anyway.  Not that it really matters, since multi-amp
currents will never happen in a circuit that expects to remain
functional -- the actual maxima are more like Vdd/z0, or perhaps
100mA in most cases.

SO -- since we're engaging in fiction anyway it may as well
be a PLEASANT fiction.  What lies can we tell that will best
suit simulator convergence algorithms?  Presumably simulators
start out with the Thevenin voltages on the line and converge
to actual terminator currents; the shape of the clamp V/I
curve would affect convergence time.

How do we optimize this process outside of realistic operating
ranges?

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com

From owner-ibis  Sun Aug 11 12:22:35 1996
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Date: Sun, 11 Aug 1996 12:08:32 -0700
To: ibis@vhdl.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: lies wrt clamp currents

To IBIS and D.C. Sessions

>SO -- since we're engaging in fiction anyway it may as well
>be a PLEASANT fiction.  What lies can we tell that will best
>suit simulator convergence algorithms?  Presumably simulators
>start out with the Thevenin voltages on the line and converge
>to actual terminator currents; the shape of the clamp V/I
>curve would affect convergence time.

>How do we optimize this process outside of realistic operating
>ranges?

We have had this topic opened for debate at least 100 times.  It
really isn't that hard to extrapolate.  Just pick what you think
is the largest reasonable values and use them at 2Vdd and -Vdd.
You don't need to fill in any of the data between what you believe
the last reasonable point and 2Vdd or -Vdd.



---------------------------------------------------------------
Have a great day...Kellee Crisafulli, HyperLynx Inc.
---------------------------------------------------------------



From owner-ibis  Mon Aug 12 08:53:31 1996
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To: ibis@vhdl.org
Subject: Bird 37.1
Date: Mon, 12 Aug 1996 08:43:26 -0700
From: Stephen Peters <speters@ichips.intel.com>


Hello All:

   Here is the latest version of Bird 37, the enhancement
to the package description.  Specific changes are:

REVISIONS FOR 37.1:
   Based on comments received, removed backslash ("/") from the Fork and 
Endfork syntax, added a description of the package stub boundaries, and
added two examples.  I also added a recommendation that non-zero length
section descriptions be treated as distributed elements.

Please review and get your comments back to me by Thursday so we 
can discuss and vote on this bird Friday.

          Thanks,
          Stephen



 
=============================================================================

                 Buffer Issue Resolution Document  (BIRD)
BIRD ID#:        37.1
ISSUE TITLE:     Enhancement To The Package Model (.pak file) Specification
REQUESTER:       Stephen Peters
DATE SUBMITTED:  August 12, 1996
DATE ACCEPTED BY IBIS OPEN FORUM:  Pending

******************************************************************************
******************************************************************************
STATEMENT OF THE ISSUE:  The current package model electrical description,
(as proposed in Bird 28.3 and accepted by the forum) has the restriction
that all the sections of a package stub connect in a series fashion, with 
no branches or stubs allowed.  This limits the usefulness of the
description when trying to describe BGA or other packages where branches
or forks off the main package stub may be present.  This BIRD corrects
this deficiency by adding two new subparameters to the [Pin Numbers] keyword
called 'Fork' and 'Endfork'
******************************************************************************
STATEMENT OF THE RESOLVED SPECIFICATIONS:  Following are the specific changes
to the specification (spec as amended by Bird 28.3).

1.  The Sub-params list of the [Pin Numbers] keyword is changed to that
shown below

|Sub-Params: Len, L, R, C, Matrix, Fork, Endfork

2.  The text following the first paragraph of the Usage Rules section of the
[Pin Numbers] keyword is replaced by the following:
|
|             Subparameters:
|             The Len, L, R, and C subparameters specify the length, 
|             inductance, capacitance and resistance of each section of
|             each stub on a package. If a particular section 
|             exhibits coupling to an adjacent (same numbered) section of 
|             a different package stub then the Matrix subparameter is used.
|             The Fork and Endfork subparameters are used to denote branches
|             from the main package stub. 
|             Len     The of a package stub section.  Lengths are given
|                     in terms of arbitrary 'units'.
|             L       The inductance of a package stub section, in terms of
|                     'inductance/unit length'.  For example, if the total
|                     inductance of a section is 3.0nH and the
|                     length of the section is 2 'units', the inductance 
|                     would be listed as L = 1.5nH  (i.e. 3.0 / 2). 
|             C       The capacitance of a package stub section, in terms of
|                     capacitance per unit length.
|             R       The DC (ohmic) resistance of a package stub section, in
|                     terms of ohms per unit length.
|             Matrix  Use of this subparameter means that this package stub
|                     sections electrical parameters are presented as part of
|                     a coupling matrix.  The data for the matrix is included
|                     between the [Model Data]/[End Model Data] keyword pairs
|                     as described below.
|             Fork    This subparameter indicates that the sections
|                     following (up to the Endfork subparameter) are part
|                     of a branch off of the main package stub.  This 
|                     subparameter has no arguments.
|             Endfork This subparameter indicates the end point of a
|                     branch.  For every Fork subparameter there must be
|                     a corresponding Endfork subparameter.  As with the
|                     Fork subparameter, the Endfork subparameter has no
|                     arguments.
|
|             Specifying a Len or L/R/C value of zero is allowed.  If
|             Len = 0 is specified, then the L/R/C values are the total
|             for that section.  If a non-zero length is specified, then
|             the total L/R/C for a section is calculated by multiplying 
|             the value of the Len subparameter by the value of the L,
|             R or C subparameter. However, if a non-zero length section
|             is specified, the L and C for that section should be treated
|             as distributed elements.
|
|             Using The Subparameters to Describe Package Stub Sections:
|             A section description begins with the Len subparameter and
|             end with the backslash (/) character.  The value of the Len, L,
|             R and C subparameters and the subparameter itself are 
|             separated by an equals sign (=); whitespace around the equals 
|             sign is optional.  The Fork and Endfork subparameters
|             are placed between section descriptions (i.e. between the
|             concluding backslash of one section and the 'Len' parameters
|             that starts another).  All package stub descriptions must 
|             contain the same number of sections however, a particular 
|             section description can contain no data (i.e. the description 
|             is given as 'Len = 0 /').
|             
|             Legal Subparameter Combinations for Section Descriptions:
|             A) A single Len = 0 subparameter, followed by a slash.
|             The is used to describe a section with no data.
|
|             B)  Len and a single Matrix subparameter, followed by a
|             backslash. The Len subparameter specifies the length of that
|             section while the Matrix subparameter indicates that this
|             section of this package stub is electrically coupled to the
|             corresponding (same numbered) section of an adjacent package
|             stub (or stubs) and the coupling terms are listed in a matrix
|             format.  The matrix description must include both the 'self'
|             inductance/capacitance/resistance (as required) of a section
|             as well as the mutual coupling terms.  If one section is
|             described using the the Matrix subparameter then the
|             corresponding (same numbered) sections on ALL other package
|             stubs must use the Matrix subparameter.
|
|             C)  Len, and one or more of the L, R and C subparameters.  If
|             the Len subparameter is given as zero, then the L/R/C sub-
|             parameters represent lumped elements.  If the the Len sub-
|             parameter is non-zero, then the L/R/C subparameters represent
|             distributed elements.
|
|             D)  Single Fork or Endfork subparameter.  Normally, a package
|             stub is described as several sections, with the Fork and Endfork
|             subparameters surrounding a group of sections in the middle of
|             the complete package stub description.  However, it is legal
|             for the Fork/Endfork subparameters to appear at the end of a 
|             section description.  The package pin is connected to the 
|             last section of a package stub description not surrounded by
|             a Fork/Endfork statements.  See the examples below. 
|
|             Package Stub Boundaries:
|             A package stub description starts at the connection to 
|             the die and ends at the point at which the package pin 
|             interfaces with the board or substrate the IC package 
|             is mounted on.  Note that in the case of a component
|             with thru-hole pins, the package stub description should
|             include only the portion of the pin not physically 
|             inserted into the board or socket.  It is legal for
|             a package stub description to include both the component
|             and socket together if this is how the component is 
|             intended to be used.
|             

3.  The following examples are added to the examples for bird 28.3
|
|A section description using the Fork and Endfork subparameters.  Note
|that the indentation of the Fork and Enfork subparameters are for
|readability and are not required.
|
A1 Len=0 L=2.3n /        | bondwire
Len=1.2 L=1.0n C=2.5 /   | first section
 Fork                    | indicates the starting of a branch
 Len=1.0 L=2.0n C=1.5p / | section 
 Endfork                 | ending of the branch
Len=0.5 L=1.0 C=2.5/     | second section 
Len=0.0 L=1.5n /          | pin
|
|Here is an example where the Fork/Endfork subparameters are at the
|end of a package stub description
|
B13 Len=0 L=2.3n /       | bondwire
Len=1.2 L=1.0n C=2.5 /   | first section
Len=0.5 L=1.0 C=2.5/     | second section, pin connects here
Fork                     | indicates the starting of a branch
Len=1.0 L=2.0n C=1.5p /  | section 
Endfork                  | ending of the branch

******************************************************************************
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:
     This bird grew out of the need to describe a particular structure found
in BGA type packages.  In these packages, the trace that connects the die 
pad to the via for the 'ball' does not stop there.  For manufacturing
reasons the trace continues out to the edge of the board and thus forms
a 'stub' or branch off the main pad to ball (or pin) connection.  Because
of the need to stick with the existing section based description, the 
fork and Endfork subparameters were chosen.

REVISIONS FOR 37.1:
   Based on comments received, removed backslash ("/") from the Fork and 
Endfork syntax, added a description of the package stub boundaries, and
added two examples.  I also added a recommendation that non-zero length
section descriptions be treated as distributed elements.





From owner-ibis  Mon Aug 12 10:44:32 1996
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Date: Mon, 12 Aug 1996 13:30:56 -0400
From: Real Mongrain <mongrain@cae.ca>
To: ibis@vhdl.org
Subject: IBIS Specification
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Hi everybody,

 I was wondering if there's some documentation other than the "I/O
Buffer Information Specification (IBIS) Version x.x". I know that most
of people in this group are very familiar with IBIS, but i am not. Maybe
somebody has already created a more explicit documentation on IBIS?

Regards,
Real Mongrain.



From owner-ibis  Mon Aug 12 12:06:18 1996
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Message-Id: <199608121854.LAA06396@ichips.intel.com>
To: ibis@vhdl.org
Subject: IBIS Specification
Date: Mon, 12 Aug 1996 11:56:13 -0700
From: Stephen Peters <speters@ichips.intel.com>


Hello Real:

   I'm not sure exactly what you are looking for, but there is available
both an artical written for EDN magazine, and a cookbook for version 1.1 
models.  They are both available on the web page:

    http://www.eia.org/eig/ibis/ibis.htm

           Regards,
           Stephen Peters
           Intel Corp.




Hi everybody,

 I was wondering if there's some documentation other than the "I/O
Buffer Information Specification (IBIS) Version x.x". I know that most
of people in this group are very familiar with IBIS, but i am not. Maybe
somebody has already created a more explicit documentation on IBIS?

Regards,
Real Mongrain.



From owner-ibis  Mon Aug 12 12:24:14 1996
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From: Jon Powell <jonp@qdt.com>
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Ibisians,

There seem to be a lot of people (including Bob and Syed) who cannot
make the meeting this friday. We were scheduled to vote on some things
that were rather important. How do people feel about postponing the
meeting for 1 or 2 weeks?

Jon
(Please Respond).

From owner-ibis  Mon Aug 12 16:02:12 1996
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To: ibis@vhdl.org
Subject: Postpone Meeting?
Date: Mon, 12 Aug 1996 15:52:06 -0700
From: Stephen Peters <speters@ichips.intel.com>


Hello Jon:

     It's OK by me.

           Regards,
           Stephen



Ibisians,

There seem to be a lot of people (including Bob and Syed) who cannot
make the meeting this friday. We were scheduled to vote on some things
that were rather important. How do people feel about postponing the
meeting for 1 or 2 weeks?

Jon
(Please Respond).

From owner-ibis  Mon Aug 12 18:02:46 1996
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Subject: Re: Postpone Meeting?


Text item: 

It is OK with me, but watch out for the Labor-day weekend, many people 
(including me) might take off early.

Arpad
=========================================================================

Ibisians,

There seem to be a lot of people (including Bob and Syed) who cannot
make the meeting this friday. We were scheduled to vote on some things
that were rather important. How do people feel about postponing the
meeting for 1 or 2 weeks?

Jon
(Please Respond).

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From owner-ibis  Tue Aug 13 02:53:44 1996
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From: olaf@pad.incases.com
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Subject: Postpone Meeting?
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Hello Jon,

It's OK by me.

Best Regards,
Olaf


> Ibisians,
>
> There seem to be a lot of people (including Bob and Syed) who cannot
> make the meeting this friday. We were scheduled to vote on some things
> that were rather important. How do people feel about postponing the
> meeting for 1 or 2 weeks?
>
> Jon
> (Please Respond).

-- 

-------------------------------------------------------------------------------
INCASES Engineering GmbH * Vattmannstr. 3 * D-33100 Paderborn * Germany 
Olaf Rethmeier * Tel/Fax +49-5251-150-625/-700 * Email olaf@pad.incases.com 
-------------------------------------------------------------------------------

From owner-ibis  Tue Aug 13 08:28:59 1996
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Ibisans,

I guess the end of the summer is a bad time to try and get people
together. I got lots of responses saying that people were planning to
lay out by the pool that morning and not even think about diode
saturation curves. Oh Well.

From the responses and the untimely death of summer (ie. Labor Day
weekend). I hereby cancel this weeks meeting and tentatively re-schedule
for the 6th of September.

Bob and Syed should be back by then.


Have a nice vacation everyone.

Jon

From owner-ibis  Tue Aug 13 08:36:43 1996
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From: omera@trailblazer.sps.mot.com (Ahmed Omer)
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Jon, 

 8/23 is good for me.

Regards, Ahmed

From vhdl.vhdl.org!owner-ibis Tue Aug 13 12:39:01 1996
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From: hoang@msai.mea.com (Hoang Nguyen)
Message-Id: <9608131943.AA04243@sbedrock.msai.mea.com>
To: ibis@vhdl.org
Subject: process parameters
Status: RO

Hello All,

I have the following questions regarding process parameters.

1. If a process file supplies all three sets: TYP, BEST, WORST, should I
   provide in the model the process corner for typ, min, max according to
   the following conditions: (for rise, fall, pullup, pulldown tables) ?
	typ: typ VCC, TYPICAL process parameters
	min: min VCC, WORST process parameters
	max: max VCC, BEST process parameters

   The conditions above provide the best process corner information, without 
   having to generate three separate models, each for a TYP/BEST/WORST process.

2.  If a process file supplies only TYP parameters, then 
	typ: typ VCC, TYPICAL process parameters
	min: min VCC, TYPICAL process parameters
	max: max VCC, TYPICAL process parameters
    
    as recommended in the cookbook.

Even for item 1 above, I could use only TYPICAL process parameters as in item 2,
but I'm afraid this won't have as much accuracy.  Please comment.

Thanks,

Hoang Nguyen


From vhdl.vhdl.org!owner-ibis Wed Aug 14 09:26:03 1996
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Status: RO

A source of mine in Japan informs me that "EIA Japan" has established an
"IBIS Standarded working group" who are going to establish a standard
format for IO models.

Has anyone heard anything about this?

Patti??

regards,
jon

From vhdl.vhdl.org!owner-ibis Wed Aug 14 10:11:51 1996
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Message-ID: <Wed, 14 Aug 96 10:20:36 PDT_6@ccm.fm.intel.com>
To: ibis@vhdl.org
Subject: Re: EIA Japan
Status: RO


Text item: 

Jon,

What do you mean by "establish a standard format for IO models"?  Another 
standrad, different from IBIS, or are they working on making IBIS a standard in 
Japan?

Arpad
===========================================================================
A source of mine in Japan informs me that "EIA Japan" has established an
"IBIS Standarded working group" who are going to establish a standard
format for IO models.

Has anyone heard anything about this?

Patti??

regards,
jon

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From vhdl.vhdl.org!owner-ibis Tue Aug 20 11:34:07 1996
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Date: Tue, 20 Aug 96 11:34 PDT
From: bob@icx.com ( Bob Ross)
To: hoang@msai.mea.com, ibis@vhdl.org
Subject: Re:  process parameters
Status: RO

Hoang:

This is in response to last weeks question.

The corner models should be based on best and
worst process conditions as outlined in "1.".  The
temperature should be varied as well.

You are correct that this may be inconsistent
with other corner models based on only typical 
processes.  IBIS allows further adjustment
of data based on factors "X%" and "Y%", but
I think this is rarely used.

Other inconsistencies also exist.  Some devices
are specified with lower Vcc tolerances (e.g. 5%
versus 10%) and different temperature ranges.
Bipolar min/max temperatures are low/high, whereas
CMOS technology temperatures are high/low.

The net effect is that the corner data models may
be further off and perhaps have larger temperature
based deviations from each other than would be
seen in practice.  So this all adds up to the
fact that corner analysis may serve as a valuable
indication of sensitivies in design, but should
not be relied upon as a predictor of preformance
without understanding the assumptions of all
models in the net and actual power supply and
temperature assumptions for the design.

Bob Ross
Interconnectix, Inc.

> Date: Tue, 13 Aug 96 15:43:09 EDT
> From: hoang@msai.mea.com (Hoang Nguyen)
> Message-Id: <9608131943.AA04243@sbedrock.msai.mea.com>
> To: ibis@vhdl.org
> Subject: process parameters
> Status: RO

> Hello All,

> I have the following questions regarding process parameters.

> 1. If a process file supplies all three sets: TYP, BEST, WORST, should I
>    provide in the model the process corner for typ, min, max according to
>    the following conditions: (for rise, fall, pullup, pulldown tables) ?
> 	typ: typ VCC, TYPICAL process parameters
> 	min: min VCC, WORST process parameters
> 	max: max VCC, BEST process parameters

>    The conditions above provide the best process corner information, without 
>    having to generate three separate models, each for a TYP/BEST/WORST process.

> 2.  If a process file supplies only TYP parameters, then 
> 	typ: typ VCC, TYPICAL process parameters
> 	min: min VCC, TYPICAL process parameters
> 	max: max VCC, TYPICAL process parameters
>     
>     as recommended in the cookbook.

> Even for item 1 above, I could use only TYPICAL process parameters as in item 2,
> but I'm afraid this won't have as much accuracy.  Please comment.

> Thanks,

> Hoang Nguyen




From owner-ibis  Wed Aug 28 18:04:33 1996
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From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: test message 1

Please Disregard

From owner-ibis  Wed Aug 28 18:04:30 1996
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Subject: test message

Please Disregard

From owner-ibis  Wed Aug 28 18:05:15 1996
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Date: Wed, 28 Aug 96 13:36 PDT
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: Forwarded: EDIF Version 4 0 0 changes

To IBIS Committee:

Does anyone have any comments or concerns about this?

Bob Ross
Interconnectix, Inc.

Date: Tue, 27 Aug 1996 13:39:51 +0100
From: Alan R Williams <alanrw@cs.man.ac.uk>
Message-Id: <199608271239.NAA04794@cheetah.cs.man.ac.uk>
To: bob@icx.com
Subject: EDIF Version 4 0 0 changes


Hello Bob,

As part of finishing the EIA balloting process, we are notifying all
reviewers of the changes which were made as a result of their
comments.  With regard to the interfacing with IBIS files, the main
change has been the introduction on pcbPartCharacteristic for EDIF
parts.  The pcbPartCharacteristic can be either a
pcbPassivePartCharacteristic (RLC values) or a
pcbIbisPartCharacteristic which specifies the IBIS file, the IBIS
component within that file and matches up the terminals of the EDIF
part to the pins of the IBIS component.

I am enclosing the changes in the syntax which were made as a result
of your comment.  Could you please confirm by c.o.b. Friday 31st
August that you are satisfied with the outcome?  If we do not hear
otherwise, we will assume that you are satisfied with the changes
which have been made.

Alan Williams

-- ---------------------------------------------------------------------------
Alan Williams, Room IT301, Department of Computer Science,
University of Manchester, Oxford Road, Manchester, M13 9PL, U.K.
Tel: +44 161 275 6270      Fax: +44 161 275 6280
e-mail: alanrw@cs.man.ac.uk


pcbIbisComponentIdentification ::= '(' 'pcbIbisComponentIdentification'
	stringToken
	')'

pcbIbisFileIdentification ::= '(' 'pcbIbisFileIdentification'
	stringToken
	')'

pcbIbisFileInformation ::= '(' 'pcbIbisFileInformation'
	pcbIbisFileInformationNameDef
	pcbIbisFileIdentification
	{  <nameInformation>  |  property  }
	')'

pcbIbisFileInformationNameCaseSensitive ::= '(' 
'pcbIbisFileInformationNameCaseSensitive'
	booleanToken
	')'

pcbIbisFileInformationNameDef ::= nameDef

pcbIbisPartCharacteristic ::= '(' 'pcbIbisPartCharacteristic'
	pcbIbisFileInformation
	pcbIbisComponentIdentification
	{  pcbIbisPinBinding  }
	')'

pcbIbisPinBinding ::= '(' 'pcbIbisPinBinding'
	pcbIbisPinBindingNameDef
	( pcbElectricalPartTerminalRef | pcbJumperPartTerminalRef | 
pcbConnectorPartTerminalRef )
	pcbIbisPinIdentification
	{  property  }
	')'

pcbIbisPinBindingNameDef ::= nameDef

pcbIbisPinIdentification ::= '(' 'pcbIbisPinIdentification'
	stringToken
	')'

pcbJumperPart ::= '(' 'pcbJumperPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	{  pcbJumperPartTerminal  |  <pcbPartCharacteristic>  }
	')'

pcbPackagedConnectorPart ::= '(' 'pcbPackagedConnectorPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	( pcbSocket | pcbDiscreteConnector )
	{  pcbPackagedConnectorPartTerminal  |  <pcbPartCharacteristic>  }
	')'

pcbPackagedElectricalPart ::= '(' 'pcbPackagedElectricalPart'
	libraryObjectNameDef
	pcbPartHeader
	( pcbPinPackageRef | pcbBallPackageRef | externalNoData )
	pcbPackagedElectricalPartType
	{  <pcbPartCharacteristic>  }
	')'

pcbPartCharacteristic ::= '(' 'pcbPartCharacteristic'
	( pcbPassivePartCharacteristic | pcbIbisPartCharacteristic )
	')'

pcbPassivePartCapacitance ::= '(' 'pcbPassivePartCapacitance'
	capacitanceValue
	')'

pcbPassivePartCharacteristic ::= '(' 'pcbPassivePartCharacteristic'
	{  <pcbPassivePartCapacitance>  |  <pcbPassivePartInductance>  |  
<pcbPassivePartResistance>  }
	')'

pcbPassivePartInductance ::= '(' 'pcbPassivePartInductance'
	tolerancedInductanceValue
	')'

pcbPassivePartResistance ::= '(' 'pcbPassivePartResistance'
	tolerancedResistanceValue
	')'

pcbPrintedConnectorPart ::= '(' 'pcbPrintedConnectorPart'
	libraryObjectNameDef
	pcbPartHeader
	{  <pcbPartCharacteristic>  |  pcbPrintedConnectorPartTerminal  |  
pcbPrintedPartSymbol  }
	')'

pcbPrintedElectricalPart ::= '(' 'pcbPrintedElectricalPart'
	libraryObjectNameDef
	pcbPartHeader
	pcbPrintedElectricalPartType
	{  <pcbPartCharacteristic>  |  pcbPrintedPartSymbol  }
	')'




-------- End of Forwarded Message

From owner-ibis  Fri Aug 30 14:57:52 1996
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Message-Id: <m0uwYHk-000GjSC@icx.com>
Date: Fri, 30 Aug 96 11:27 PDT
From: bob@icx.com ( Bob Ross)
To: ibis@vhdl.org
Subject: IBIS MEETING 9/6/96

(Resuming operation after a 6 week vacation!)

                       IBIS Open Forum Meeting Agenda 
                                for 9/6/96
 
                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   2-88345         4511183
 
 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 

 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Ross
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      EIA/Japan - IBIS Working Group?                         Powell/Rusher
 
      IEC Express Funding Progress                            Rusher

      EE Times Article                                        Ross

      New Administrative Issues                               All

 8:35 Technical Discussion

      s2ibis2 QUESTIONS                                       Huq

      BIRD34.1 - STORED CHARGE EFFECT                         Ross

      BIRD35.1 - MULTI-STAGED OUTPUTS                         Ross
             
      BIRD36 - ELECTRICAL BOARD DESCRIPTION                   Peters

      BIRD37.1 - ENHANCEMENT TO THE PACKAGE MODEL SPEC.       Peters
                 (Vote)

      BIRD38 -  ABSOLUTE MAXIMUM VOLTAGE                      Fitzpatrick

      EGG12 - SPECIFICATION ADDITIONS                         Ross, All

      EGG10 -  PARSER TESTS  1-5                              Rokusek        

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 





From owner-ibis  Sat Aug 31 21:26:31 1996
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Date: Sat, 31 Aug 1996 21:14:59 -0700 (PDT)
From: Zeelan Technology <zeelan@zeelan.com>
X-Sender: zeelan@linda.teleport.com
To: ibis@vhdl.org
Subject: Zeelan Technology's Email address
Message-ID: <Pine.SUN.3.92.960831210541.19389A-100000@linda.teleport.com>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII


Please change Zeelan Technology's information
to the new Email, phone numbers and address

george@zeelan.com

FAX: 503-685-1001
Telephone: 503-685-1000

Zeelan Technology
8005 SW Boeckman Road
Wilsonville, Oregon   97070


Thank you.

Sincerely,

George Opsahl





 |-----------------------------------------------------------|
 |   Zeelan Technology              Email: info@zeelan.com   |
 |   8005 SW Boeckman Road          FAX:   503-685-1001      |
 |   Wilsonville, Oregon   97070    Telephone:  503-685-1000 |
 |-----------------------------------------------------------|


