From huq@rockie.nsc.com Tue Jan 2 16:50:55 1996 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24747; Tue, 2 Jan 96 16:50:55 PST Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA27006 for ibis@vhdl.org; Tue, 2 Jan 96 16:42:56 -0800 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA08176 for ibis@vhdl.org; Tue, 2 Jan 96 16:42:54 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA17218; Tue, 2 Jan 96 16:44:05 PST Date: Tue, 2 Jan 96 16:44:05 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9601030044.AA17218@rockie.nsc.com> To: ibis@vhdl.org Subject: IBIS face-to-face meeting(Reminder & Infos) Cc: brockh@mdhost.cse.tek.com, d_snyder%spf@tevm2.nsc.com, peter@fc.hp.com, rbrennan@berlioz.nsc.com, jacko@altera.com, huq@rockie.nsc.com IBISgurus, Happy New Year! A reminder for you for the upcoming IBIS face-to-face meeting and more detailed information. Thanks to the many who have already confirmed attendance. You MUST RSVP by Friday the 5th for Lunch(need headcount).We will have an informal(pay your own)dinner to celebrate IBIS adoption into ANSI/EIA-656 and our journey to IEC. Place: Westin Hotel (Lafayette & San Thomas Room) 5101 Great America Parkway Santa Clara, California (408)986-0700 Date: Jan 29th Monday(one day) Time: 8am - 5pm Directions: ----------- From San Jose Airport: ---------------------- Take Guadalupe Expressway to '101 San Francisco' Exit 'Great America Parkway' (turn right on exit) Westin Hotel is at the corner of Tasman and Great America Parkway. Santa Clara Convention Center(Design SuperCon'96) and Westin Hotel are next to each other. From San Francisco Airport: --------------------------- Take '101 San Jose' Exit Great America Parkway Westin Hotel is at the corner of Tasman and Great America Parkway. Hotel Information: ------------------- Pls make your reservations as soon as possible. Certain Hotels tend to fill up due to various events going on. Wyndham Garden Hotel 1300 Chesapeake Terrace Sunnyvale (408)747-0999 Santa Clara Marriott Hotel 2700 Mission College Blvd Santa Clara (408)988-1500 Quality Suites 3100 Lakeside Drive Santa Clara (408)748-9800 Days Inn 4200 Great America Parkway Santa Clara (408)980-1525 Westin Hotel 5101 Great America Parkway Santa Clara (408)986-0700 Embassy Suites 2885 Lakeside Drive Santa Clara (408)496-6400 If you need any other assistance or questions you may have, let me know. Best Regards, Syed. National Semiconductor Corp. (408)721-4874 ----- Begin Included Message ----- From huq@rockie.nsc.com Mon Dec 4 10:35:04 1995 Date: Mon, 4 Dec 95 10:04:26 PST From: huq@rockie.nsc.com (Syed Huq) To: ibis@vhdl.org Subject: IBIS face-to-face meeting plans.. Content-Length: 1028 IBISfans, EIA/ANSI-656 IBIS Face to Face meeting-1996 (hosted by National Semiconductor Corp.) ------------------------------------------ Welcome to the upcoming IBIS face-to-face meeting January 1996. Place: Westin Hotel, Santa Clara, California Date: Jan 29th Monday(one day) Time: 8am - 5pm We are in the process of updating the meeting agenda and adding any additional topics as necessary. The meeting will be open for discussions on Semiconductor/EDA vendors issues regarding IBIS as well as various technical discussions. If you would like a particular item to be added to the agenda, pls send an E-mail to either one of the following: Will Hobbs(Will_Hobbs@ccm.jf.intel.com) Bob Ross (bob@icx.com) Syed Huq (huq@rockie.nsc.com) Breakfast, Lunch and Snacks will be provided so please RSVP to: huq@rockie.nsc.com There will also be a celebration dinner after the meeting. Details of Maps/directions/final agenda will be posted soon so stay tuned. Regards, Syed National Semiconductor Corp. ----- End Included Message ----- From mbs@eos.ncsu.edu Wed Jan 3 08:46:18 1996 Return-Path: Received: from c11142-343dan.ece.ncsu.edu by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06935; Wed, 3 Jan 96 08:46:18 PST Received: by c11142-343dan.ece.ncsu.edu (8.6.9/EC06jan95) id LAA01507; Wed, 3 Jan 1996 11:38:18 -0500 From: mbs@eos.ncsu.edu Message-Id: <199601031638.LAA01507@c11142-343dan.ece.ncsu.edu> To: ibis@vhdl.org Subject: New and Updated IBIS models Date: Wed, 03 Jan 96 11:38:17 EST From National Semiconductor Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- 90c031tm interface 9/20/95 2.0 2.1 LVDS Quad Diff Line Drvr 90c032tm interface 9/20/95 1.1 2.1 LVDS Quad Diff Line Rcvr These models were previously available only with a non disclosure agreement. From Intel Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- pentpro.ibs pentpro 12-5-95 R2.1 V2.1 Pentium Pro Processor ppromax.pkg pentpro 11-30-95 R0.1 package data for pentpro.ibs ppromin.pkg pentpro 11-30-95 R0.1 package data for pentpro.ibs The Pentium Pro model has been updated. The current library is as follows National Semiconductor Corporation Part/File vhdl.org rev. rev. IBIS name Directory date level ver. Notes -------------------------------------------------------------------------------- ds26c31.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Drvr ds26c32.ibs interface 2/09/95 1.0 2.1 RS-422 Quad Diff Line Recvr 90c031tm.ibs interface 9/20/95 2.0 2.1 LVDS Quad Diff Line Drvr 90c032tm.ibs interface 9/20/95 1.1 2.1 LVDS Quad Diff Line Rcvr 38c86av.ibs cbtl 9-18-95 1.0 1.1 CMOS BTL 9-Bit Latching Data Transceiver lct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524m.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr ct2524n.ibs cgs 04-05-95 1.0 1.1 1to4 Min. Skew 3V Clk Drvr c2525m.ibs cgs 04-05-85 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2525m.ibs cgs 03-10-95 2.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2525n.ibs cgs 03-10-95 2.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2525m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) b2525n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (Bipolar) c2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) c2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (CMOS) ct2526m.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2526n.ibs cgs 04-05-95 1.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) ct2527v.ibs cgs 03-23-95 2.0 1.1 1to8 Min. Skew Clk Drvr (TTL Compa) b2528m.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2528n.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2528v.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) b2529v.ibs cgs 04-05-95 1.0 1.1 1to10 Min. Skew Clk Drvr (Bipolar) 2534v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Commercial) 2535v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) 2536v.ibs cgs 04-05-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) b303m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b303v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b304v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305m.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305n.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr b305v.ibs cgs 04-05-95 1.0 1.1 Octal Div-by-2 Skew Clk Drvr 701v.ibs cgs 04-05-95 1.0 1.1 Low Skew PLL 1to8 CMOS Clk Drvr 2537v.ibs cgs 04-17-95 1.0 1.1 Quad Mem Array Clk Drvr (Industrial) pc87306.ibs superI_O 9-5-95 1.1 1.1 pc87306vul(SuperI/O) FDC,KBC,RTC,UARTs,IR,PP and IDE int g612mea.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL SSOP 56 Lead g612mtd.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL TSSOP 56 Lead gp612mea.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL SSOP 56 Lead gp612mtd.ibs gtl 6/30/95 1.1 1.1 18-Bit CMOS GTL TSSOP 56 Lead dp8440vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver dp8441vj dram_ctl 6/28/95 1.0 1.1 Prog. DRAM Controller/Driver Intel Corporation IBIS Files on vhdl.org as of 1/3/96 Part/File vhdl.org alpha rev. rev. IBIS name Directory name date level ver. Notes -------------------------------------------------------------------------------- 82371fb.ibs chipset PIIX 08-09-95 R1.21 V1.1 Triton (NDA only)** 82371mb.ibs chipset MPIIX 08-09-95 R1.01 V1.1 Mobile Triton (NDA only)** 82374eb.ibs chipset ESC 08-09-95 R2.13 V1.1 PCI-EISA Bridge** 82374sb.ibs chipset ESC 08-09-95 R1.03 V1.1 PCI-EISA Bridge** 82375eb.ibs chipset PCEB 08-09-95 R2.13 V1.1 PCI-EISA Bridge** 82375sb.ibs chipset PCEB 08-09-95 R1.01 V1.1 PCI-EISA Bridge** 82378ib.ibs chipset SIO 08-09-95 R2.13 V1.1 PCI-EISA Bridge** 82378zb.ibs chipset SIO 08-09-95 R0.96 V1.1 PCI-EISA Bridge** 82379ab.ibs chipset SIO.A 08-09-95 R0.96 V1.1 PCI-EISA Bridge** 82423tx.ibs chipset DPU 08-09-95 R2.13 V1.1 Saturn** 82424zx.ibs chipset CDC 08-09-95 R2.13 V1.1 Saturn** 82425ex.ibs chipset PSC 08-09-95 R0.94 V1.1 Aries** 82426ex.ibs chipset IB 08-09-95 R0.94 V1.1 Aries** 82433lx.ibs chipset LBX 08-09-95 R2.13 V1.1 Mercury** 82433nx.ibs chipset LBX 08-09-95 R2.01 V1.1 Neptune** 82434lx.ibs chipset PCMC 08-09-95 R2.13 V1.1 Mercury** 82434nx.ibs chipset PCMC 08-09-95 R2.01 V1.1 Neptune** 82437fx.ibs chipset TSC 08-09-95 R1.21 V1.1 Triton (NDA only)** 82437mx.ibs chipset MTSC 08-09-95 R1.01 V1.1 Mobile Triton (NDA only)** 82437vx.ibs chipset TVX 08-09-95 R1.00 V1.1 Triton VX (NDA only)** 82438fx.ibs chipset TDP 08-09-95 R1.21 V1.1 Triton (NDA only)** 82438mx.ibs chipset MTDP 08-09-95 R1.01 V1.1 Mobile Triton (NDA only)** 82438vx.ibs chipset TDX 08-09-95 R1.00 V1.1 Triton (NDA only)** dx4pga.ibs cpu DX4 05-04-94 R2.0 V1.1 IntelDX4(TM) uP pp66sem.ibs pentium PP66 10-16-94 R3.0 V1.1 66MHz Pentium* pp100sem.ibs pentium PP100 10-15-94 R3.0 V1.1 100MHz Pentium* pentpro.ibs pentpro 12-5-95 R2.1 V2.1 Pentium Pro Processor ppromax.pkg pentpro 11-30-95 R0.1 package data for pentpro.ibs ppromin.pkg pentpro 11-30-95 R0.1 package data for pentpro.ibs * Translated from an Intel Simplified Electrical Model. From mbs@eos.ncsu.edu Wed Jan 3 14:01:57 1996 Return-Path: Received: from c11142-343dan.ece.ncsu.edu by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09191; Wed, 3 Jan 96 14:01:57 PST Received: by c11142-343dan.ece.ncsu.edu (8.6.9/EC06jan95) id QAA02644; Wed, 3 Jan 1996 16:53:57 -0500 From: mbs@eos.ncsu.edu Message-Id: <199601032153.QAA02644@c11142-343dan.ece.ncsu.edu> To: ibis@vhdl.org Subject: New IBIS models Date: Wed, 03 Jan 96 16:53:57 EST INtel has made new models available under NDA. etails are as follows. Part/File vhdl.org alpha rev. rev. IBIS name Directory name date level ver. Notes -------------------------------------------------------------------------------- 82437fx.ibs TSC 08-09-95 R1.21 V1.1 Triton with NDA only** 82437mx.ibs MTSC 08-09-95 R1.01 V1.1 Mobile Triton with NDA only** 82437vx.ibs TVX 12-13-95 R1.50 V1.1 Triton VX with NDA only** 82438fx.ibs TDP 08-09-95 R1.21 V1.1 Triton with NDA only** 82438mx.ibs MTDP 08-09-95 R1.01 V1.1 Mobile Triton with NDA only** 82438vx.ibs TDX 12-13-95 R1.50 V1.1 Triton VX with NDA only** 82439hx.ibs TXC 12-13-95 R1.01 V1.1 Triton HX with NDA only** From bob@icx.com Fri Jan 5 18:15:49 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12600; Fri, 5 Jan 96 18:15:49 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 5 Jan 96 18:07 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 5 Jan 96 18:10 PST Message-Id: Date: Fri, 5 Jan 96 18:10 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS MEETING AGENDA 1/12/96 IBIS Open Forum Meeting Agenda for 1/12/96 Bridge Number Reservation # Passcode (916) 356-9200 2-41860 1918954 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Hobbs - Intros of New IBIS Participants, Meeting Quorum Hobbs - Membership Update and Treasurers Report Rusher/Hobbs - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Press & Web Page Updates All - New Models Available, Library Update All - Opens for New Issues All 8:15 EIA/IBIS Activities - 1996 Membership Rusher/Hobbs - DAC EDA Standards Booth Rusher/Hobbs - ANSI/EIA-656 Editorial Review Ross 8:25 Administrative and Project Discussions Web Project Update Huq January 29, 1996 Face-to-Face Meeting - Logistics/Details Huq - Call For, Summary of Presentations Hobbs/All - ANSI/EIA Celebration Dinner Details Huq Golden Parser 2.1 Status Powell/Ross S2IBIS 2.1 Status Ross/Steer New Administrative Issues All 9:00 Technical Discussion EGG8 - Physical Package Description Discussion Crisafulli BIRD31 - Connector Models Ross BIRD32 - Matrix Name Enhancement Proposal Kumar/Peters EGG6 - CMOS and TTL Data Powell New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Hobbs 9:55 Sign Off From Will_Hobbs@ccm.jf.intel.com Fri Jan 5 18:24:12 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12640; Fri, 5 Jan 96 18:24:12 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id SAA02998 for ; Fri, 5 Jan 1996 18:16:11 -0800 Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0tYOB1-000txZC; Fri, 5 Jan 96 18:16 PST Received: by ccm.jf.intel.com (ccmgate 3.2 #3) Fri, 05 Jan 96 18:16:11 PST Date: Fri, 05 Jan 96 18:12:00 PST From: Will Hobbs Message-Id: To: ibis@vhdl.org Subject: IBIS Summit Call for Presentations Greetings, fellow Ibisers! This is a call for presentations at the upcoming IBIS Summit. On Monday, January 29, 1996, there will be a general session (Summit) of the IBIS Open Forum, a.k.a. EIA IBIS Committee. This is an open meeting for anyone with an interest in the IBIS standard, ANSI EIA-656, to meet and share information, move the technology forward and define future goals. The primary focus of this meeting will be technical, rather than administrative. This meeting will be hosted by National Semiconductor in Santa Clara, with the details of time and place to be issued soon. In the summit, we plan to address experiences, technical challenges, success stories, current efforts, etc., among three major groups of IBIS participants: - Users, model consumers, signal integrity engineers - IC vendors - EDA vendors To make this summit a success, we need people to make presentations, which can be from 20 to 30 minutes in length. Possible topics for individual presentations include the following: * What your company is doing with IBIS, how it is tackling IBIS challenges * Where you think we need to go with IBIS for Version 3.0 * New technologies/areas you've tackled with IBIS (MCM, connectors, RFI/EMC, ...) * Customer input, feedback * Plans you would be willing to share * Areas of current exploration (e.g., improved diode modeling, complex packages) * Model development, validation methodologies * Model usage, shortcomings, strengths, wishes * Data derivation methodologies (measured and/or simulated) * Auto-extraction of V/I and other IBIS data from SPICE simulations, silicon * Models available * Other (Specify) ___________________ - Can you volunteer to present at the summit? - On what topic? - How much time do you need? We will also discuss pending Birds, and try to refine or resolve them, and generally have a good time. Please reply to Will Hobbs, will_hobbs@jf.ccm.intel.com before Friday, 1/12/96. I will be working with Syed Huq of National Semiconductor and Bob Ross of Interconnectix on an agenda based on responses I receive from this call for presentations. Help make the January, 1996 IBIS Summit the most successful one to date! Thanks, and Best Regards, Will Hobbs Chairman, EIA IBIS Committee, and Server Component System Validation Manager Intel Corp. From Will_Hobbs@ccm.jf.intel.com Mon Jan 8 08:41:10 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24687; Mon, 8 Jan 96 08:41:10 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id IAA07201 for ; Mon, 8 Jan 1996 08:33:08 -0800 Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0tZKVP-000twhC; Mon, 8 Jan 96 08:33 PST Received: by ccm.jf.intel.com (ccmgate 3.2 #3) Mon, 08 Jan 96 08:33:07 PST Date: Mon, 08 Jan 96 08:28:00 PST From: Will Hobbs Message-Id: To: ibis@vhdl.org Subject: IBIS Summit Call for Presentations, 2nd try ---------------------------- Forwarded with Changes --------------------------- From: Will Hobbs at JFCCM16 Date: 1/5/96 6:12PM To: ibis@vhdl.org at SMTPGATE Subject: IBIS Summit Call for Presentations ------------------------------------------------------------------------------- I sent this out on Friday, and it didn't echo back to me, so I'm assuming it didn't get out. Here's my second attempt. Will Greetings, fellow Ibisers! This is a call for presentations at the upcoming IBIS Summit. On Monday, January 29, 1996, there will be a general session (Summit) of the IBIS Open Forum, a.k.a. EIA IBIS Committee. This is an open meeting for anyone with an interest in the IBIS standard, ANSI EIA-656, to meet and share information, move the technology forward and define future goals. The primary focus of this meeting will be technical, rather than administrative. This meeting will be hosted by National Semiconductor in Santa Clara, with the details of time and place to be issued soon. In the summit, we plan to address experiences, technical challenges, success stories, current efforts, etc., among three major groups of IBIS participants: - Users, model consumers, signal integrity engineers - IC vendors - EDA vendors To make this summit a success, we need people to make presentations, which can be from 20 to 30 minutes in length. Possible topics for individual presentations include the following: * What your company is doing with IBIS, how it is tackling IBIS challenges * Where you think we need to go with IBIS for Version 3.0 * New technologies/areas you've tackled with IBIS (MCM, connectors, RFI/EMC, ...) * Customer input, feedback * Plans you would be willing to share * Areas of current exploration (e.g., improved diode modeling, complex packages) * Model development, validation methodologies * Model usage, shortcomings, strengths, wishes * Data derivation methodologies (measured and/or simulated) * Auto-extraction of V/I and other IBIS data from SPICE simulations, silicon * Models available * Other (Specify) ___________________ - Can you volunteer to present at the summit? - On what topic? - How much time do you need? We will also discuss pending Birds, and try to refine or resolve them, and generally have a good time. Please reply to Will Hobbs, will_hobbs@jf.ccm.intel.com before Friday, 1/12/96. I will be working with Syed Huq of National Semiconductor and Bob Ross of Interconnectix on an agenda based on responses I receive from this call for presentations. Help make the January, 1996 IBIS Summit the most successful one to date! Thanks, and Best Regards, Will Hobbs Chairman, EIA IBIS Committee, and Server Component System Validation Manager Intel Corp. From Arpad_Muranyi@ccm.fm.intel.com Mon Jan 8 09:36:46 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA25079; Mon, 8 Jan 96 09:36:46 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id JAA14257 for ; Mon, 8 Jan 1996 09:28:45 -0800 Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0tZLNE-000twlC; Mon, 8 Jan 96 09:28 PST Received: by ccm.hf.intel.com (ccmgate 3.2 #3) Mon, 08 Jan 96 09:28:44 PST Date: Mon, 08 Jan 96 09:23:00 PST From: Arpad Muranyi Message-Id: To: ibis@vhdl.org Subject: New EGG? Happy New Year! As I am working on enhacements to our internal IBIS tool we are using around here, I discovered something which might need correction in the IBIS specification. In the days of IBIS 1.1, it was assumed that the Ramp data was obtained with a 50 Ohm load. In the 2.1 specification, we decided to add the R_load sub-parameter to this keyword for devices needing a different load for the dV/dt measurements. Later, when we defined the sub-parameter R_fixture for the V-t curve keywords (Rising and Falling Waveform) we did it so that each Waveform could have their own set of sub-parameters. We also added the statement: "Note that for backwards compatibility, the existing [Ramp] keyword is still required." R_load and R_fixture refer to the same load resistor with which the dV/dt and Waveform measurements are made. The problem I see here is that each of the Waveform keywords could potentially have a different R_fixture value. If I derived my dV/dt_r and dV/dt_f numbers from these Waveforms (which is the simplest way of obtaining them), I would need two independent R_load values for the Ramp sub-parameters. Currently we have the option for only one. This forces the model maker to either make a totally different simulation/measurement for the Ramp numbers (using only one R_load value for both sub-parameters) or force the R_fixture numbers to be the same for each Waveform. I feel we should correct the IBIS specification and allow the use of two R_load values, one for each sub-parameter of the Ramp keyword. I am curious to hear any comments. If this topic turns serious, this might be considered an EGG and I will write a BIRD on it later. Sincerely, Arpad Muranyi Intel Corporation From cpk@Cadence.COM Tue Jan 9 08:02:01 1996 Return-Path: Received: from mailgate.Cadence.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11207; Tue, 9 Jan 96 08:02:01 PST Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id HAA12920 for ; Tue, 9 Jan 1996 07:53:59 -0800 Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via smap (V1.0mjr) id sma821202583.012189; Tue Jan 9 07:49:43 1996 Received: from hot by cadence.Cadence.COM (5.61/3.14) id AA19887; Tue, 9 Jan 96 07:49:38 -0800 Received: by hot (5.65+/1.5) id AA05184; Tue, 9 Jan 96 10:49:37 -0500 Date: Tue, 9 Jan 96 10:49:37 -0500 From: cpk@cadence.com (C. Kumar) Message-Id: <9601091549.AA05184@hot> To: ibis@vhdl.org Subject: new bird for enahnced packaging Hello Fellow IBISians: Here is BIrd on enhancemnet to package modelling. This builds on Stephen's BIRD 28. The major benefits of the bird are outlines in the first paragraph. Regards C. Kumar Cadence Design Systems Buffer Issue Resolution Document (BIRD) BIRD ID#: 32 ISSUE TITLE: Additional Enhancement To The Package Model (.pak file) Specification REQUESTER: C. Kumar DATE SUBMITTED: Dec 14, 1995 DATE ACCEPTED BY IBIS OPEN FORUM: Pending ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: BIRD 28.3 enhancement to package model addresses "large"packages which go beyond the realm of lumped circuit modelling. It also partly addresses etch to etch coupling. However it imposes restrictions on the number of sections and the requirement that only adjacent etches can be coupled. The current bird removes such restrictions. The key benefits of this bird are 1. Etches can have arbitrary amount of sections 2. The coupling is not restricted to adjacent etches 3. The coupling matrice are referenced by name . This achieves highly compact descriptions of coupling. It is well known that layouts are characterized by cross sections which occur repeatedly and one description per cross section should be sufficient. 4. A new matrix data section is proposed which contains the data for the matrices. This section differs from the package matrix sections in important ways. a). The matrix is referred to by a name and thus multiple instance of the matrix can be specified by just one description. b). The matrix section is ideally suited for trace cross section description. These cross sections are usually a SET of Resitance, Inductance, Conductance and Capacitances (RLGC matrices ) and the matrix section can optionally contain all of them. ******************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Following are the specific changes. These are changes over and above that of BIRD 28.3 1. The keyword [Number of Sections] is not required since variable number of sections for each pin is allowed 2. The Matrix key word is replaced by Matrix Name parameter and Matrix pin order parameter. 3. A new kwy words [MATRIX DATA] and [END MATRIX DATA] are introduced. This section should contain data for the matrices referenced in the [Pin Number] key word 4. The current [Pin Numbers] keyword (post BIRD 28.3) is modified |============================================================================= | Keyword: [Pin Numbers] | Required: Yes |Description: Tells the parser the set of names that are used for the package | pins and also defines pin ordering. Each pin number should | start as the first character in a new line. | | Sub-Params: Len, L, R, C, Matrix, MxPinOrder | | The Matrix now just identified the name of the matrix and MxPinOrder shows how | the rows of the matrix is mapped to etches emanating from the pins | | In the example below the first section is a lumped inductor, | the second section is described using a 3-line matrix, and | the third | section is modeled using distributed elements. Pin A3 shows | an example of sections with no data. Pin A3 also shows a | 2line matrix section coupled to A5! Pins A4 and A5 illustrate | how a section description can be broken across multiple lines | and how each section description is delimited by the slash. |----------------------------------------------------------------------------- [Pin Number] A1 Len = 0 L=1.2n / Len = 1.3 Matrix=3line MxPinOrder=(A1 A2 A3) / Len=0.47 L=8.35n C=3.34p R=0.01 / A2 Len = 0 L=1.4n / Len = 1.2 Matrix=3line MxPinOrder=(A1 A2 A3)/ Len=0.47 L=6.21n C=3.34p R=0.01 / A3 Len = 0 / Len = 1.1 Matrix=3line MxPinOrder=(A1 A2 A3) / Len = 0 Matrix=2line MxPinOrder=(A3 A5) / A4 Len = 0 L=1.2n / Len = 1.0 L=2nH / Len=0.47 L=8.35n C=3.34p R=0.01/ A5 Len = 0 L=1.2n / Len=1.2 Matrix=2line MxPinOrder=(A3 A5) / Len=0.47 L= 8.35n C=3.34p R=0.01 / | | Note that the actual length for each section is reported, even for | those sections that use the Matrix subparameter. | 3. A new section [MATRIX DATA] is introduced | |============================================================================= | Keywords: [MATRIX DATA] [END MATRIX DATA] | Required: Yes , if the [Pin Number] contains references to matrices | 3. The key word Matrix is modified |============================================================================= | Keyword: [Matrix] [END MATRIX] | Required: Yes if used in the [Pin Numbers] section |Description: Identifies the per unit length RLGC matrices of the cross section | Sub-Params: SIZE, TYPE, RMatrix, LMatrix, GMatrix, CMatrix, ROW, | [END RMATRIX], [UNIT] | [END LMATRIX] [END CMATRIX] [END GMATRIX] | | | The following example shows 2line matrix | The end sections explicitly identifies each of the sections | | [UNIT] is a sub parameter which specifies the per length unit | Sub parameter like [UNIT] cna be specified at the [MATRIX] level | and/or specified at the lower levels like [RMATRIX] etc. The | specification at the lowest level is the one which will be used. | For example if the unit is specified both at the [MATRIX] level and | at teh [RMATRIX] level, the specification at the [RMATRIX] will be the | one which will be used for the Rmatrices. If [UNIT] is not specified | a default of per meter will be assumed | | If [TYPE} is not specified a default of Full_matrix will be assumed | |============================================================================ [MATRIX DATA] [MATRIX] 2line {SIZE] 2 [UNIT] Meter [RMATRIX] [UNIT] Meter [TYPE] Full_Matrix [ROW] 1 3.29 0 [ROW] 2 0 3.29 [END RMATRIX] | Note : unit and type for CMATRIX is defaulted [CMATRIX] [ROW] 1 1.5e-11 -0.2e-13 [ROW] 2 -0.2e-13 1.5e-11 [END CMATRIX] [END MATRIX] [MATRIX] 3line ..... .... ... [END MATRIX] ... .. [END MATRIX DATA] ----- End Included Message ----- From bob@icx.com Wed Jan 10 15:17:16 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18646; Wed, 10 Jan 96 15:17:16 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 10 Jan 96 15:09 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 10 Jan 96 15:11 PST Message-Id: Date: Wed, 10 Jan 96 15:11 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: New EGG? RESENT MESSAGE Date: Mon, 08 Jan 96 09:23:00 PST From: Arpad Muranyi To: ibis@vhdl.org Subject: New EGG? Happy New Year! As I am working on enhacements to our internal IBIS tool we are using around here, I discovered something which might need correction in the IBIS specification. In the days of IBIS 1.1, it was assumed that the Ramp data was obtained with a 50 Ohm load. In the 2.1 specification, we decided to add the R_load sub-parameter to this keyword for devices needing a different load for the dV/dt measurements. Later, when we defined the sub-parameter R_fixture for the V-t curve keywords (Rising and Falling Waveform) we did it so that each Waveform could have their own set of sub-parameters. We also added the statement: "Note that for backwards compatibility, the existing [Ramp] keyword is still required." R_load and R_fixture refer to the same load resistor with which the dV/dt and Waveform measurements are made. The problem I see here is that each of the Waveform keywords could potentially have a different R_fixture value. If I derived my dV/dt_r and dV/dt_f numbers from these Waveforms (which is the simplest way of obtaining them), I would need two independent R_load values for the Ramp sub-parameters. Currently we have the option for only one. This forces the model maker to either make a totally different simulation/measurement for the Ramp numbers (using only one R_load value for both sub-parameters) or force the R_fixture numbers to be the same for each Waveform. I feel we should correct the IBIS specification and allow the use of two R_load values, one for each sub-parameter of the Ramp keyword. I am curious to hear any comments. If this topic turns serious, this might be considered an EGG and I will write a BIRD on it later. Sincerely, Arpad Muranyi Intel Corporation From huq@rockie.nsc.com Thu Jan 11 16:10:09 1996 Return-Path: Received: from gatekeeper.nsc.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA06776; Thu, 11 Jan 96 16:10:09 PST Received: from nsc.nsc.com by gatekeeper.nsc.com (5.65/fma-120691) with SMTP; id AA11746 for ibis@vhdl.org; Thu, 11 Jan 96 16:02:06 -0800 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA05198 for ibis@vhdl.org; Thu, 11 Jan 96 16:02:04 -0800 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA00923; Thu, 11 Jan 96 16:03:22 PST Date: Thu, 11 Jan 96 16:03:22 PST From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9601120003.AA00923@rockie.nsc.com> To: ibis@vhdl.org Subject: ANSI/EIA-656 IBIS Web Site is up ! Cc: huq@rockie.nsc.com IBISgurus, Finally we made it. The IBIS homepage is up and running. http://www.eia.org/eig/ibis/ibis.htm We intend to upgrade, add and fine tune the homepage and provide valuable IBIS related information in the coming months. Pls provide me with feedback/comments/suggestions you may have. Regards, Syed Huq National Semiconductor From bob@icx.com Fri Jan 12 15:32:07 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA22812; Fri, 12 Jan 96 15:32:07 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 12 Jan 96 15:23 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 12 Jan 96 15:26 PST Message-Id: Date: Fri, 12 Jan 96 15:26 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS REFLECTOR TEST To All: If you get this message, then the IBIS reflector is working again. Bob Ross, Interconnectix, Inc. From bob@icx.com Sat Jan 13 14:05:37 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07437; Sat, 13 Jan 96 14:05:37 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Sat, 13 Jan 96 13:57 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Sat, 13 Jan 96 14:00 PST Message-Id: Date: Sat, 13 Jan 96 14:00 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Re: NEW EGG? Subject: Re: NEW EGG? Several Comments Below: ************* 1/8/96 Bob Ross writes (private to Arpad): P.S., regarding your potential EGG, we presume only one R_load. There is a potential need for two R_loads, but we opted for the complete [Rising ...] description rather than add MANY other details to the [Ramp] - such as termination voltages with typ, low, high values, etc. We cover situations in our tool by a hierarchy of choices: If more than 2 [Rising Waveform]s, use FIRST two [Rising Waveform]s. If 2 [Rising Waveform]s - use both, unless mathematical convergence problem, then use FIRST [Rising Waveform] (Note, the R_fixtures can be different, but for convergence in our system, the V_fixtures usually also have to be different to avoid a singularity) If 1 [Rising Waveform] use it. If 0 [Rising Waveform] use [Ramp] and dV/dt_r Same for Falling Waveforms, treated independent of Rising Waveforms. Note, these sequences would apply independently for any column (typ, min, max). While Simulators which can process Version 2.1 models, but do not have the Waveform capability would be stuck with a single R_load per IBIS 1.1 as the best approximation. ************* 1/8/96 Arpad Muranyi writes (private to Bob): Thanks for your reply. You are right, I forgot about the other fixture parameters in this context. I am not proposing at all to expand the Ramp sub-parameters to that extent. Maybe another solution is needed, I just feel something is not quite right there. ************* 1/12/96 C. Kumar writes: For complete specification you will also need V-load which was absent in 1.1 ************* > > Date: Mon, 08 Jan 96 09:23:00 PST > From: Arpad Muranyi > To: ibis@vhdl.org > Subject: New EGG? > > Happy New Year! > > As I am working on enhacements to our internal IBIS tool we are using > around here, I discovered something which might need correction in the > IBIS specification. > > In the days of IBIS 1.1, it was assumed that the Ramp data was > obtained with a 50 Ohm load. In the 2.1 specification, we decided to > add the R_load sub-parameter to this keyword for devices needing a > different load for the dV/dt measurements. > > Later, when we defined the sub-parameter R_fixture for the V-t curve > keywords (Rising and Falling Waveform) we did it so that each Waveform > could have their own set of sub-parameters. We also added the > statement: "Note that for backwards compatibility, the existing > [Ramp] keyword is still required." > > R_load and R_fixture refer to the same load resistor with which the > dV/dt and Waveform measurements are made. The problem I see here is > that each of the Waveform keywords could potentially have a different > R_fixture value. If I derived my dV/dt_r and dV/dt_f numbers from > these Waveforms (which is the simplest way of obtaining them), I would > need two independent R_load values for the Ramp sub-parameters. > Currently we have the option for only one. This forces the model > maker to either make a totally different simulation/measurement for > the Ramp numbers (using only one R_load value for both sub-parameters) > or force the R_fixture numbers to be the same for each Waveform. > > I feel we should correct the IBIS specification and allow the use of > two R_load values, one for each sub-parameter of the Ramp keyword. > > I am curious to hear any comments. If this topic turns serious, this > might be considered an EGG and I will write a BIRD on it later. > Sincerely, > > Arpad Muranyi > Intel Corporation > From bob@icx.com Sat Jan 13 14:16:45 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07501; Sat, 13 Jan 96 14:16:45 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Sat, 13 Jan 96 14:08 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Sat, 13 Jan 96 14:11 PST Message-Id: Date: Sat, 13 Jan 96 14:11 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS REFLECTOR TEST To IBIS LIST: The reflector ibis@vhdl.org is working again if you receive this. Bob Ross Interconnectix, Inc. From bob@icx.com Mon Jan 15 15:06:51 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07362; Mon, 15 Jan 96 15:06:51 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Mon, 15 Jan 96 14:58 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Mon, 15 Jan 96 15:01 PST Message-Id: Date: Mon, 15 Jan 96 15:01 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: REVISED IBIS VERSION 2.1 To IBIS Reflector: In response to a very good editorial review, a revised IBIS Version 2.1 now resides in /pub/ibis/ver2.1/ver2_1.txt and also is accessable on the new Web page. The older version is saved in the aug95 subdirectory. Below is a letter documenting most of the editorial changes that were not covered by the review. Bob Ross Interconnectix, Inc. --------------------------------------------------------------------------- January 15, 1996 Jeanne Warner Electronic Industries Association 2500 Wilson Boulevard Arlington, VA 22201 Dear Jeanne: Enclosed is a copy of the reviewer's comments and a revised copy of the technical portion of Version 2.1 of ANSI/EIA-656. Both copies have changes below highlighted. Also enclosed is a DOS disk which includes: 00readme This document ver2_1.ibs SECTION 6 Version 2.1 Technical Portion of ANSI/EIA-656 We accept all of the suggestions except those which relate to separating the numbers from the scaling units (e.g., 5mV versus 5 mV) in the actual examples only. It is acceptable common practice in computer processing to allow no space. Furthermore, we suggest eliminating entirely annex A. Annex A was included for the formal letter ballot process only. The changes that were documented were included in the main text and are still included. We have attempted to make all of the changes in a consistent manner, even if they were not marked by the reviewer (in a few instances). We have also made a few additional corrections for consistency reasons, and have recorded them below for your reference. PRELIMINARY MATERIAL We accept All of the reviewers corrections. Page i: We suggest removing Appendix ... 35 entirely. Page 2, "5 Anomalies" section: We would delete the existing section entirely, and include a statement to say "Version 2.1 of the IBIS specification has no anomalies." SECTION 6 Changes on Version 2.1 of I/O Buffer .... Page 3: We have made a global change from August 22, 1995 to December 13, 1995 to capture the date of ANSI/EIA-656 acceptance. We have changed the wording to plural tense at the question: "... allowing simulation vendors to derive models compatible with their own products." Pages 4, 5: [Comment char] changed to [Comment Char] for consistency of presentation of keywords. Thys change is also made in one occurance in the PACKAGE MODELING section. [File name] changed to [File Name] also for consistency of presentation of keywords. Page 6: Copyright 1994 changed to Copyright 1995 to be consistent with the December 13, 1995 date. Page 7: The suggested global changes were NOT adopted because the existing syntax in the examples is consistent with acceptable computer processing formats and are required for correct operation. Page 11: Additional instances were discovered in the text: 0 V and 0 ns. In the [Diff Pin] example, the units in the comments were deleted in 3 locations because there was not room for separation and because they were not needed. Page 12: Additional instances for separations: 0 mA and 0 mA Page 14: Four additional instances for separations: 0 V Page 19: We changed all "Ohm" in the example to "ohm", but did not separate the units. Page 20: We corrected the unexpected line wrap of "the waveform" Note Pages 22-30 were missing in our review copy. We corrected (PGAs.) to (PGAs). Pages 32, 34: All instances of 50C, 0C and 100C were changed to 50 deg C, 0 deg C and 100 deg C as the closest approximation to the suggested change. The text fonts do not support the degree symbol. We also changed 2.2V ot 2.2 V. Page 33: We also changed -2V to -2 V. We inserted a missing blank line before section d. ANNEX SECTION We suggest deleting this entire section. It is not relevant for the final published version of ANSI/EIA-656 because all of the suggested changes are included in the body of the standard. Bob Ross EIA/IBIS Open Forum Secretary Interconnectix, Inc. (503) 603-2523 cc: Patti Rusher IBIS Reflector From bob@icx.com Tue Jan 16 16:24:28 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA23334; Tue, 16 Jan 96 16:24:28 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 16 Jan 96 16:16 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 16 Jan 96 16:18 PST Message-Id: Date: Tue, 16 Jan 96 16:18 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS MINUTES 1/12/96 DATE: January 16, 1996 SUBJECT: 1/12/96 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS: AT&T Global Info Solutions Dave Moxley* Cadence Design Sandeep Khanna, C. Kumar* Contec CAE, Ltd. Dileep Divekar Hewlett Packard Tom Langdorf, Karl Kachigan, Henry Wu HyperLynx Kellee Crisafulli* IBM Jay Diepenbrock INCASES Werner Rissiek, Olaf Rethmeier* Intel Corporation Stephen Peters*, Will Hobbs*, Arpad Muranyi*, Derrick Duehren Interconnectix, Inc. Bob Ross* Meta-Software Les Spruiell, Mei Wong, You-Pang Wei, John Sliney Motorola Ron Werner National Semiconductor Syed Huq*, Atul Agarwal, Cheng-Yang Kao NEC Hiroshi Matsumoto, Eldar Yazbashevz Quad Design Jon Powell*, Chris Myles, Chris Rokusek* Quantic Labs Mike Ventham Tanner Research, Inc. Scott Wedge, Ed Miller, Peter Parrish Texas Instruments Roger Cline*, Ben Andresen*, Sri Jandhyala*, Tareq Shahwan Thomson-CSF/SCTF Jean LeBrun UniCAD Canada Ltd. Stephen Lum VLSI Technology Dick Ulmer, Sung Oh Zuken-Redac John Berrie OTHER PARTICIPANTS: AMP Hank Herrmann* ARPA Randy Harr Anacad Steffen Rochel Ansoft Henri Maramis Atmel Corporation Dan Terry Cadlab Ralf Bruning CFI Ron Christopher, Don Cottrell Digital Equipment Corp. Barry Katz EIA Patti Rusher* High Design Technology Michael Smith, Dr. Ing. Cosso Integrated Silicon Systems Eric Bracken Intergraph Ian Dodd, David Wiens, Walter Katz IntuSoft Charles Hymowitz LSI Logic Corp. Satish Pratadneni Mentor Graphics Ravender Goyal, Greg Doyle Micron Technology Brian Johnson MicroSim Ralph Perez* North Carolina State U. Steve Lipa, Michael Steer OptEM Engineering, Inc. Benny Leveille, Ken Ehn Pacific Numerix Paul K. U. Wang Symmetry Martin Walker Synopsys, Logic Modeling G. Bill Lattin Univ. of Illinois, Urbana Raj Mittra Zeelan Technology George Opsahl, Hiro Moriyasu (Independent) Bob Ward In the list above, attendees at the meeting are indicated by *. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 1/29/96 NONE - IBIS SUMMIT 8 AM - 5 PM, SANTA CLARA, CA 2/16/96 (916) 356-9200 2-48992 5519538 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS Ralph Perez joined from MicroSim, replacing the previous representative. He is involved with libraries. EIA MEMBERSHIP AND TREASURER'S REPORT Hewlett-Packard - EEsof Division has officially joined for 1996 and has also purchased the IBISCHK2 Source code. Patti Rusher reported no change in the treasury. MINUTES REPORT, MISC. Spelling error of Sri Jandhyala's last name was corrected. The outstanding action item is to send out membership renewals. MISCELLANY/ANNOUNCEMENTS The IBIS mail reflector on vhdl.org has been down due to some unresolved problems. Bob Ross will use a script to do reflector mailings until the problem is resolved. If you want to mail something, you can still send it to the reflector where it will be archived. Bob will retransmit the unsent email.archive messages. PRESS AND WEB PAGE UPDATES Hyperlynx EM article in Electronic Engineering Times, December 18, 1995, pg. 72 mentions IBIS. NEW MODELS Stephen Peters reported that a new pentpro.pkg model has been submitted. Intel also has announced some new chipset models available under NDA. OPENS FOR NEW ISSUES ANSI review (already on agenda) R_load and R_fixture (not covered) EIA/IBIS 1996 MEMBERSHIP Patti Rusher will send out EIA/IBIS 1996 membership forms shortly. Bob Ross had reviewed the list. AR - Patti Rusher send out membership invoices for 1996. AR - All pay invoice within 45 days. The committee will keep existing members for 45 days after the receipt of the invoice to give time to go through corporation payment processes. ANSI/EIA-656 EDITORIAL REVIEW Bob Ross received a review copy of the above standard prior to formal publication as an ANSI Standard. Jon Powell and Will Hobbs reviewed the comments and agree with all of the editorial English text corrections. Only the global suggestion to separate numbers from the units multipliers in ACTUAL examples will be rejected for obvious reasons. We will suggest removing the two "ANNEX" BIRDS since they were relevant only in the voting process and not in the final version. This new version will carry the date "December 13, 1995" within reflecting the date of formal approval. Bob plans to supply the updated text of Version 2.1 to EIA and also to store it on vhdl.org when finished. This will form the technical portion of the complete standard that will be available from EIA. DAC STANDARDS BOOTH The Design Automation Conference (DAC) in June, 1996 will have a Standards booth in a prominant front location. EIA is invited to participate. The IBIS committee expressed support. The pro-rated fee of the $5K, 1000 sq. ft. booth to the IBIS committee is expected to be only several hundred dollars, depending upon whether the committee will have handouts only, or have demonstrations of IBIS. EDIF 4 0 0 is expected to have undergone final review and will be demonstrated at DAC. Patti Rusher reported that arrangement details will be decided at February 27, 1996 planning meeting. The scope of the IBIS participation will be put on the agenda for the IBIS Face to Face Meeting. EIA can take orders for ANSI/EIA-656 and other standards, but may not sell anything off the floor. They can have literature and demos. AR - Will Hobbs put on the Face to Face Agenda the level of IBIS involvement at DAC. EIA WEB UPDATE Syed Huq reported that the Web Page is up!! He requests feedback since there may be some minor problems. The full address needs to be entered: http://www.eia.org/eig/ibis/ibis.htm Otherwise an error will be issued. The higher level search utility does NOT point to this page. The web site links to vhdl.org and to company home pages for those who had requested it. This linkage is done from the IBIS Membership Poster page. Response during the meeting indicated that people were very pleased with the presentation and layout. Two final hand-scanned pictures in the EDN article have been sent to EIA and need to be included. AR - Will Hobbs check with Derrick Duehren regarding EDN article source. Texas Instruments still plans to send the logo file to Jon Powell (who will then forward it to Syed Huq) and the permission letter to Patti Rusher. TI will not link to its home page at this time. FACE TO FACE MEETING Syed Huq reported that the meeting will take place at the Westin Hotel (attached to the Conference Center where SuperCon96 will be held the next day) on January 29, 1996. Two rooms are reserved for the Summit. So far 34 people have signed up from about 20 different companies, and more local participation is expected. The ANSI/EIA-656 Celebration Dinner will be DUTCH TREAT at 6:00 p.m. at the Same Hotel. The early hour will allow those who need to fly home that evening to catch their flights. The same location eliminates the time lost traveling and gathering at another location. Reservations will be made during the morning of the Face to Face meeting for those who want to attend. Will Hobbs is requesting presentors to supply him with topics and estimated time by the end of the day. Will, Bob Ross, and Syed Huq will start drafting the agenda the following week. Several people expressed intentions of having presents on BIRD subjects and other topics. Semiconductor Vendor participation will probably include at least Texas Instruments on TI IBIS Activities, National Semiconductor on model provider experience, and Intel on bus keepers and on various modeling considerations. BIRD/Egg subjects that are being considered will probably each have presentations/discussions. The new RAIL (Rules Augmented Interconnect Layout) committee (chaired by Don Telian of Intel who also chaired the initial IBIS work leading to Version 1.0) has requested 45 minutes to introduce RAIL and also show how it relates to IBIS. AR - All Potential Presenters inform Will Hobbs by Friday, January 12. [Done] Presenters should bring several extra copies. National will collect a copy of each presentation and reproduce them for distribution during the meeting. Presentions provided in electronic form can be archived in an directory on vhdl.org. Bob Ross will handle this. GOLDEN PARSER UPDATE Bob Ross reported no activity yet. A bug fix release is expected early this year. Will Hobbs indicated the need for a PARSER Bug tracking System. Jon Powell volunteered to take charge since he has the ibischk2 source code for distribution. Kellee Crisafulli discovered, but did not record, some uninitialized variables which cause problems when ibischk2 is re-entered. This would be a problem when ibischk2 is re-entered, as occurs when used within the Hyperlynx winibis viewing/checking/editing utility. AR - Jon Powell send out draft form to Will Hobbs and Bob Ross for review. [DONE] SPICE TO IBIS VERSION 2.1 Bob Ross reported no further information. EGG8 - PHYSICAL PACKAGE DISCUSSION Kellee Crisafulli lead a long discussion on his approach to address MCM and SIMM layout repesentation. Stephen Peters supports the approach, and Jon Powell would like the see the proposal move forward somehow. An alternative approach is to consider EDIF 4 0 0. Do we need the added complexity. Or do we want something simple, easy, and not too powerful? This proposal is expected to help interface small PCB layout, SIMM and MCM layout information with IBIS electrical characterics. Kellee may want to get PCB layout vendors to partipate in the generation of the format. The format itself is intended to be SIMPLE. Translators to internal formats by (say, RSI) could be easily made available for sale. Jon Powell indicated that most "models" would usually be autogenerated. The format is very readable and understandable. This proposal would produce a separate ".pcb" file similar to the .pkg file associated with package models. The format of this file including stackup and physical dimensions is quite different from the IBIS format. AR - Kellee turn this into BIRD33, issued at the meeting. Further discussion involved speculating that RSI could be hired to create a writer or file generator for .pcb files and licence it to PC layout companies to offer. Kellee felt that RSI would do this for a few thousand dollars ($5-10K). Bob Ross recommends we explore its context and position it as a separate effort. Kellee indicates that it does not have the enough "umph" to to stand by itself, so it should tag along with another standard such as IBIS. Kellee expects to lead more discussion at the Face to Face Meeting. EGG9 - HANDLING STORED CHARGE Bob Ross has not pursued further some details on this proposal. This is planned to be a topic at the Face to Face Meeting. BIRD31 - CONNECTOR MODELS Bob Ross reported that the idea of spliting the connector onto each board has been abandoned. He is working on another proposal. Some additional considerations will be presented at the Face to Face Meeting. Jon Powell raised the concern that grounding (or lack of grounding) is a critical difference from package model considerations. Hank Herrmann indicated that AMP Spice models have the ground references supplied external to the unreference model based on connnections and based on actual signal/reference-voltage pin assignments. BIRD32 PACKAGE MODEL ENHANCEMENT C. Kumar has sent out BIRD32 which expands on BIRD28.3 to provide both a more comprehensive and a more compact electrical package description. Even vias could be modeled. A key enhancement is the naming of matrices, so matrices can be called out in many places. Smaller matrices would be extracted anyway through field solver analysis. One concern is the matrix capablility in IBIS 2.1 is not used. Kellee and Jon Powell would like to see IC vendors to comment on whether they would put models in that format. Kumar commented that coupled matrix considerations will be a requirement within a year as speed approach the 150 MHz and above range. Stephen Peters indicated that the new proposal has merit, but is not totally consistent with the proposals to date. It would be beneficial to look at the complete package picture and produce a totally consistent extension. One source it to review the BIRD28.3 proposal integrated in the /wip/ver3_0a file of IBIS unofficial drafts. Bob Ross, Kumar, and Stephen can work on this, but cannot commit to finishing this before the Face to Face Meeting. Bob Ross commented that BIRD32 might be the simplification necessary to enable such package models to be created. Hank Herrmann indicated that BIRD32 would help make connector models compact enough to be practical. The level of electrical description detail versus physical description detail (of Egg8) would be of concern, but the proposals are complimentary. This is expected to be discussed at the Face to Face Meeting. EGG6 - TTL and CMOS Jon Powell is convinced that the differences can be handled within the current IBIS Specification, but with a change in test loads to get the proper dynamic parameters. If permitted, he will report on this at the Face to Face Meeting. NEXT MEETING: The Face-to-Face Meeting is on Monday, January 29, 1996 in Santa Clara, CA. The next telephone meeting is set for Friday, February 16, 1996. ============================================================================== NOTES IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210 will_hobbs@ccm.jf.intel.com Server Chipset System Validation Manager, Intel Corp. 2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Bob Ross (503) 603-2523, fax (503) 639-3469 bob@icx.com 10220 SW Nimbus Ave, K4, Portland, OR 97223 The following email addresses are used: ibis-request@vhdl.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org) or both. State your request. ibis-info@vhdl.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@vhdl.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. ibis-users@vhdl.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page: http://www.eia.org/eig/ibis/ibis.htm Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an email request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From bob@icx.com Fri Jan 19 09:10:15 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA09986; Fri, 19 Jan 96 09:10:15 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 19 Jan 96 09:01 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 19 Jan 96 09:04 PST Message-Id: Date: Fri, 19 Jan 96 09:04 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Forwarded: Jan 12 '96 minutes clarification Cc: hank.herrmann@amp.com Hank: Thank you for your valuable clarifications. The minutes will be corrected to refect your comments. Bob Ross Interconnectix, Inc. From: Herrmann Hank To: "IBIS: Bob Ross" Cc: Millard Steve , Schroeder Jim Subject: Jan 12 '96 minutes clarification Date: Fri, 19 Jan 96 11:48:00 E Bob, I am afraid I may not have been clear enough in my comments about our multiline connector models. Under the discussion on BIRD31 - CONNECTOR MODELS, you recorded the following; "Hank Herrmann indicated that AMP Spice models have the ground references supplied external to the unreference model based on connnections and based on actual signal/reference-voltage pin assignments." That could be confusing to many people and I am not even sure what that means. I hope the following will be more clear. AMP Multiline SPICE Connector Models do not have any assumed ground connections. Each multiline model (MLM) provides a portion of the contacts of a complete connector. For example, a PCMCIA MLM might include 16 columns x 2 rows (or 32 contacts). Any of those 32 contacts can be used as ground, power or signal lines. You simply "connect to the model" the way you would connect to that portion of the actual connector. The model will perform like the connector would perform. I submit this to you as a correction to the minutes. You may forward it out to the reflector if you think that will be helpful. Regards, Hank Herrmann Technical Staff Member AMP Incorporated, Electro-Magnetic Technology M.S. 106-14 P.O. Box 3608 Harrisburg, PA 17105-3608 Phone: 717-986-5534 FAX: 717-986-5643 INTERNET: hank.herrmann@amp.com From Will_Hobbs@ccm.jf.intel.com Fri Jan 19 18:51:10 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA13766; Fri, 19 Jan 96 18:51:10 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id SAA20656 for ; Fri, 19 Jan 1996 18:43:02 -0800 Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0tdTGf-000twpC; Fri, 19 Jan 96 18:43 PST Received: by ccm.jf.intel.com (ccmgate 3.2 #3) Fri, 19 Jan 96 18:43:01 PST Date: Fri, 19 Jan 96 18:39:00 PST From: Will Hobbs Message-Id: To: ibis@vhdl.org Subject: Final call for presentations Hello, IBIS-folk! Two weeks ago, I issued a call for presentations. Events conspired against me in two ways: I listed the wrong address for my e-mail, and subsequently the reflector went down for a week. So, I am re-posting. We do have a number of folks who have committed to present, but I don't want anyone to be excluded by Murphy. On Monday, January 29, 1996, there will be a general session (Summit) of the IBIS Open Forum, a.k.a. EIA IBIS Committee. This is an open meeting for anyone with an interest in the IBIS standard, ANSI EIA-656, to meet and share information, move the technology forward and define future goals. The primary focus of this meeting will be technical, rather than administrative. This meeting will be hosted by National Semiconductor in Santa Clara, with the details of time and place to be issued soon. In the summit, we plan to address experiences, technical challenges, success stories, current efforts, etc., among three major groups of IBIS participants: - Users, model consumers, signal integrity engineers - IC vendors - EDA vendors To make this summit a success, we need people to make presentations, which can be from 20 to 30 minutes in length. Possible topics for individual presentations include the following: * What your company is doing with IBIS, how it is tackling IBIS challenges * Where you think we need to go with IBIS for Version 3.0 * New technologies/areas you've tackled with IBIS (MCM, connectors, RFI/EMC, ...) * Customer input, feedback * Plans you would be willing to share * Areas of current exploration (e.g., improved diode modeling, complex packages) * Model development, validation methodologies * Model usage, shortcomings, strengths, wishes * Data derivation methodologies (measured and/or simulated) * Auto-extraction of V/I and other IBIS data from SPICE simulations, silicon * Models available * Other (Specify) ___________________ - Can you volunteer to present at the summit? - On what topic? - How much time do you need? We will also discuss pending Birds, and try to refine or resolve them, and generally have a good time. Please reply to Will Hobbs, will_hobbs@ccm.jf.intel.com I will be working with Syed Huq of National Semiconductor and Bob Ross of Interconnectix on an agenda based on responses I receive from this call for presentations. Help make the January, 1996 IBIS Summit the most successful one to date! Thanks, and Best Regards, Will Hobbs Chairman, EIA IBIS Committee, and Server Component System Validation Manager Intel Corp. From munden Sat Jan 20 14:14:16 1996 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26723; Sat, 20 Jan 96 14:14:16 PST Date: Sat, 20 Jan 96 14:14:16 PST From: munden (Rich Munden) Message-Id: <9601202214.AA26723@vhdl.vhdl.org> To: ibis Subject: test meassage please ignore From Arpad_Muranyi@ccm.fm.intel.com Mon Jan 22 13:15:57 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26909; Mon, 22 Jan 96 13:15:57 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id NAA14229 for ; Mon, 22 Jan 1996 13:07:48 -0800 Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0teTSt-000twyC; Mon, 22 Jan 96 13:07 PST Received: by ccm.hf.intel.com (ccmgate 3.2 #3) Mon, 22 Jan 96 13:07:47 PST Date: Mon, 22 Jan 96 13:03:00 PST From: Arpad Muranyi Message-Id: To: John.Fitzpatrick@ln.cit.alcatel.fr_at_smtpgate@ccm.hf.intel.com, ibis@vhdl.org Subject: Re[2]: Interpretation of I/O data Text item: John, Sorry that I didn't respond for so long, but I was very busy the last few weeks. Here are my answers to your EMAIL: >OK. My question was to confirm that the static I/V curve >could be extracted from an IBIS file. >I think so, but two cases are unclear for me (due >to the lack of examples?): FAST-type inputs and Bus-hold inputs. What are you referring to when you say FAST-type? Shouldn't the Bus-hold circuit be modeled as an output rather than an input? >If there is more than one power-supply, and one supply fails, >it would be useful to predict the input impedance of an unpowered >input buffer. Inputs usually clamp below and above the supply rail. If the failing power supply shorts to GND, the input will clamp below -0.6 volts and above +0.6 volts. >Can a buffer which doesn't clamp when powered, clamp >when unpowered (for applied voltages in the range 0 to Vcc)? If the power on the input disables the clamping somehow, I can see that it could clamp when it is not powered. But it would be helpful if you would state what kind of input you are referring to. Regular CMOS, or something unusual, which I don't know about? CMOS DOES clamp ewen when it is powered (0.6 volts above Vdd). >Then I have misunderstood the use for "Vinh" and "Vinl". Are these not >used to decide if a simulated signal is acceptable or not? Specifying >the minimum hysteresis would correctly allow noisier signals to pass, >(this is often the reason for choosing a buffer with hysteresis). These two keywords are not there to define the hystereris. >I'd hope a simulator would warn me if any signals risk crossing >a threshold too slowly. Valid point, but there is no keyword in IBIS yet to base this warning on. If it is important to you, you might want to raise this (and the hysteresis) issue in the Open Forum Meeting. I brought it up last time, and people are open to these kinds of comments, requests. Sincerely, Arpad ================================================================================ Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii References: Subject: Re: Interpretation of I/O data To: Arpad Muranyi Mime-Version: 1.0 X-Mailer: Mozilla 2.0b3 (X11; I; SunOS 4.1.3_U1 sun4c) Organization: Alcatel CIT, 22304 Lannion, France From: FITZPATRICK John Date: Thu, 14 Dec 1995 19:59:27 +0100 Message-Id: <30D0740F.1CFBAE39@ln.cit.alcatel.fr> Sender: fitzpat1@ln.cit.alcatel.fr Received: from nsfhh1.ansf.alcatel.fr by relay1gw.alcatel.fr with SMTP (1.37.109.8/16.2) id AA20106; Thu, 14 Dec 1995 19:57:52 +0200 Received: from relay1gw.alcatel.fr by aurora.intel.com (8.7.1/10.0i); Thu, 14 De c 1995 15:37:57 GMT Received: from aurora.intel.com by fmmail.fm.intel.com with smtp (Smail3.1.28.1 #2) id m0tQIpp-000rHkC; Thu, 14 Dec 95 10:56 PST From ingraham@wrksys.ENET.dec.com Mon Jan 22 19:46:13 1996 Return-Path: Received: from mail13.digital.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29893; Mon, 22 Jan 96 19:46:13 PST Received: from us1rmc.bb.dec.com by mail13.digital.com (5.65v3.2/1.0/WV) id AA23271; Mon, 22 Jan 1996 22:32:19 -0500 Received: from wrksys.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA04534; Mon, 22 Jan 96 22:23:04 -0500 Message-Id: <9601230323.AA04534@us1rmc.bb.dec.com> Received: from wrksys.enet; by us1rmc.enet; Mon, 22 Jan 96 22:33:05 EST Date: Mon, 22 Jan 96 22:33:05 EST From: Andy Ingraham To: ibis@vhdl.org Cc: ingraham@wrksys.ENET.dec.com Apparently-To: ibis@vhdl.org Subject: Re[3]: Interpretation of I/O data I wasn't the one who asked the questions, but I'll throw in my two bits, if for no other reason than to give another opinion. > Shouldn't the Bus-hold circuit be modeled as an output rather than an input? Bus-hold circuits are typically used on bi-directs, but because they come into play when the output is disabled, one tends to think of them as being part of the input circuit rather than the output. It seems to make more sense to model them as input currents, since they are always there whether the output drives or not. Since IBIS is predicated on modeling static I/V characteristics, and since the I/V curves of bus-hold circuits depend on past history (a bi-stable state), there is a problem of how to model them. Anyway, they may be problematic because of their positive feedback. > Inputs usually clamp below and above the supply rail. If the failing power > supply shorts to GND, the input will clamp below -0.6 volts and above +0.6 > volts. Not necessarily. Many IC inputs do not clamp in the positive direction, or if they do, it is not at Vcc +0.6 volts. CMOS inputs need not clamp at all, in principle. Generally speaking, clamps are added for their protection. Some IC inputs are designed not to conduct when power is removed; important for hot-swapping boards or running independent units on a common bus. I think this is the question John Fitzpatrick is getting at. Will the clamp characteristics be the same (relative to Vcc) with the power removed as when it is present? I can't say, though I think there is a good likelihood that the gross behavior would be similar. It is probably best to contact the IC manufacturer or IBIS model writer to see under what conditions those parameters apply. Regards, Andy From Arpad_Muranyi@ccm.fm.intel.com Tue Jan 23 08:22:19 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA11259; Tue, 23 Jan 96 08:22:19 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id IAA12552; Tue, 23 Jan 1996 08:12:50 -0800 Received: from ccm.hf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0telKz-000tx9C; Tue, 23 Jan 96 08:12 PST Received: by ccm.hf.intel.com (ccmgate 3.2 #3) Tue, 23 Jan 96 08:12:49 PST Date: Tue, 23 Jan 96 08:02:00 PST From: Arpad Muranyi Message-Id: To: ibis@vhdl.org Cc: ingraham@wrksys.ENET.dec.com Subject: Re[4]: Interpretation of I/O data Text item: Andy, I agree with your response. The main problem I see in this discussion is that we are talking about something, but we don't really know what we are talking about. We need a definition what that "INPUT" really is. True CMOS input, a CMOS I/O in receiving mode, Bipolar, etc... The answer might be quite different. This kind of holds for the bus-hold circuits as well. Whether we can model it or not with IBIS depends on how it is built. Is there feedback or other fancy stuff in it? Is it just a static pullup or pulldown structure? etc... Arpad =============================================================================== I wasn't the one who asked the questions, but I'll throw in my two bits, if for no other reason than to give another opinion. > Shouldn't the Bus-hold circuit be modeled as an output rather than an input? Bus-hold circuits are typically used on bi-directs, but because they come into play when the output is disabled, one tends to think of them as being part of the input circuit rather than the output. It seems to make more sense to model them as input currents, since they are always there whether the output drives or not. Since IBIS is predicated on modeling static I/V characteristics, and since the I/V curves of bus-hold circuits depend on past history (a bi-stable state), there is a problem of how to model them. Anyway, they may be problematic because of their positive feedback. > Inputs usually clamp below and above the supply rail. If the failing power > supply shorts to GND, the input will clamp below -0.6 volts and above +0.6 > volts. Not necessarily. Many IC inputs do not clamp in the positive direction, or if they do, it is not at Vcc +0.6 volts. CMOS inputs need not clamp at all, in principle. Generally speaking, clamps are added for their protection. Some IC inputs are designed not to conduct when power is removed; important for hot-swapping boards or running independent units on a common bus. I think this is the question John Fitzpatrick is getting at. Will the clamp characteristics be the same (relative to Vcc) with the power removed as when it is present? I can't say, though I think there is a good likelihood that the gross behavior would be similar. It is probably best to contact the IC manufacturer or IBIS model writer to see under what conditions those parameters apply. Regards, Andy Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: Re[3]: Interpretation of I/O data Apparently-To: ibis@vhdl.org Cc: ingraham@wrksys.ENET.dec.com To: ibis@vhdl.org From: Andy Ingraham Date: Mon, 22 Jan 96 22:33:05 EST Received: from wrksys.enet; by us1rmc.enet; Mon, 22 Jan 96 22:33:05 EST Message-Id: <9601230323.AA04534@us1rmc.bb.dec.com> Received: from wrksys.enet by us1rmc.bb.dec.com (5.65/rmc-22feb94) id AA04534; Mon, 22 Jan 96 22:23:04 -0500 Received: from us1rmc.bb.dec.com by mail13.digital.com (5.65v3.2/1.0/WV) id AA23271; Mon, 22 Jan 1996 22:32:19 -0500 Received: from mail13.digital.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29893; Mon, 22 Jan 96 19:46:13 PST Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by ormail.intel.com ( 8.6.12/8.6.12) with SMTP id TAA29644; Mon, 22 Jan 1996 19:44:44 -0800 Received: from ormail.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0teZf4-000tx5C; Mon, 22 Jan 96 19:44 PST From Will_Hobbs@ccm.jf.intel.com Tue Jan 23 10:46:26 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA12314; Tue, 23 Jan 96 10:46:26 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id KAA03795; Tue, 23 Jan 1996 10:38:09 -0800 Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0tenbZ-000tyZC; Tue, 23 Jan 96 10:38 PST Received: by ccm.jf.intel.com (ccmgate 3.2 #3) Tue, 23 Jan 96 10:38:05 PST Date: Tue, 23 Jan 96 10:34:00 PST From: Will Hobbs Message-Id: To: ibis@vhdl.org, dkf@apteq.com Subject: Re: Open Forum Place and Registration, Text item: Dan, and the rest of the IBIS forum, I am putting the final touches on the agenda today, and confirming participation with all the presenters on the agenda. I intend to send it out before the end of the day, and so far this looks doable. Meanwhile, here is the vital info (what, where, when, etc.). What: IBIS Open Forum Summit (Hosted this year by National Semiconductor) Date: 1/29/96 Time: 8:00 AM - 5:00 PM PST Where: Westin Hotel, Lafayette & San Thomas Rooms 5101 Great America Parkway, Santa Clara, CA Phone: (408) 986-0700 I hope to see many of you there! Regards, Will Hobbs Intel Corp. > Hello Mr. Hobbs, > > I have been on the ibis reflector for a while, following the > activities, and have just recently gotten to the position that I would > like to see in more detail what is going on. Hence, I would like to > attend the IBIS Open Forum on the 29th of this month. However, being > somewhat out of the core loop, I do not recall seeing either an exact > time and place, as well as whether any type of registration would be > required. > > Thanks in advance for any guidance you can give in this regards, > > --Dan > > > Dan FitzPatrick, Apteq Design Systems, Inc. Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Cc: dkf@apteq.com Subject: Open Forum Place and Registration, To: will_hobbs@ccm.jf.intel.com Message-Id: <199601231658.IAA24270@apteq.com> From: Dan FitzPatrick Date: Tue, 23 Jan 1996 08:58:01 -0800 Received: (from dkf@localhost) by apteq.com (8.6.11/8.6.9) id IAA24270; Tue, 23 Jan 1996 08:58:01 -0800 Received: from apteq.com (apteq.com [205.186.204.254]) by ormail.intel.com (8.6. 12/8.6.12) with ESMTP id IAA18397 for ; Tue, 23 Jan 1996 08:52:03 -0800 Received: from ormail.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0telx4-000twZC; Tue, 23 Jan 96 08:52 PST From Will_Hobbs@ccm.jf.intel.com Tue Jan 23 18:07:24 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA16388; Tue, 23 Jan 96 18:07:24 PST Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.6.12/8.6.12) with SMTP id RAA29745 for ; Tue, 23 Jan 1996 17:59:14 -0800 Received: from ccm.jf.intel.com by relay.jf.intel.com (Smail3.1.28.1 #2) id m0teuUT-000twvC; Tue, 23 Jan 96 17:59 PST Received: by ccm.jf.intel.com (ccmgate 3.2 #3) Tue, 23 Jan 96 17:59:13 PST Date: Tue, 23 Jan 96 17:56:00 PST From: Will Hobbs Message-Id: To: ibis@vhdl.org Subject: IBIS Open Forum Summit Meeting Agenda Happy IBIS-campers, Here is the agenda for the upcoming Summit. There may be some minor last minute changes as we approach the actual date, but this should be a good guide to the day's events. I look forward to seeing the "old-timers" again, and meeting many of you for the first time. This should be an excellent meeting, representing a good cross-section of users and producers of models and simulators, and a good cross-section of technical topics. There is much more that could be presented in such a session, and we will undoubtedly wish we had more time. But I don't think anyone will be disappointed with the time they spend at this session. For those who are attending, please send an RSVP to Syed Huq (huq@rockie.nsc.com) so he has an idea of how many people will be attending so he can order appropriate amounts of food. If for some reason you don't RSVP, however (like last minute plans changing) and want to come, please join us anyway. For those who are presenting, bring a clean copy of your presentation to give to Syed at the beginning of the session so he can have copies made. Or, bring lots of extra copies so participants can take copies home with them. Please arrive promptly, as we have a very full schedule. See you in San Jose! Will Hobbs Chair, EIA IBIS Open Forum and Server Component SV Manager Intel Corp. ========================================================================== IBIS Open Forum Summit Meeting Agenda (Hosted by National Semiconductor) 1/29/96 8:00 AM - 5:00 PM Westin Hotel, Lafayette & San Thomas Rooms 5101 Great America Parkway, Santa Clara, CA Phone: (408)986-0700 8:00 Check-in, Intros, Announcements Hobbs - Introductions - Miscellany/announcements, minutes review - Dinner reservations (Sticks Restaurant at Westin Hotel) - Opens for additional topics 8:20 Administrative Stuff - Web page improvements, etc. Huq - `96 Membership, etc. Hobbs - DAC Standards booth participation - IBIS_CHK bug report process Powell 8:50 Brief Overview and History of IBIS Hobbs 9:10 National and the IBIS Experience Huq 9:35 IBIS at Intel: Buffer Architecture to Customer Models Peters 10:00 - 10:15 Break 10:15 Model Provider Experiences, The TI Experience Jandhyala 10:40 Using IBIS Models in System Design Moxley 11:05 Modeling Lossy Transmission Lines Kumar 11:30 Egg 8: Modeling Packages with Physical Descriptions Crisafulli Noon - 1:00 Lunch 1:00 BIRDs 28.3, 32: Modeling Packages with Elec. Descr. Peters, Kumar 1:30 BIRD 31: Connector Modeling Ross 1:50 Stored Charge Modeling, Diode Delay Discussion Ross, Powell 2:25 Egg 6: Detecting CMOS versus TTL Powell 2:40 Double Counting and Other Model Generation Issues Muranyi 3:00 - 3:15 Break 3:15 RAIL, Rules Augmented Interconnect Layout Spec Telian 3:55 Useful Non-Simulation Data Inclusion Powell 4:15 Bus Hold Circuits and EIA JEDEC JC40 Wenniger 4:30 Open Discussion: IBIS 3.0 Possibilities, Wish Lists Hobbs 4:55 Wrap-Up, Next Meeting Plans 5:00 End of Conference 6:00 Dinner to Celebrate ANSI EIA-656 adoption: Sticks Restaurant at Westin Hotel ===================================================================== From bob@icx.com Wed Jan 24 11:08:49 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA29695; Wed, 24 Jan 96 11:08:49 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 11:00 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 11:03 PST Message-Id: Date: Wed, 24 Jan 96 11:03 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: MEMBERSHIP To IBIS Members: Please DISREGARD the Invoices that were sent out for EIA/IBIS membership for 1996. An error that was discovered regarding the fees were NOT corrected prior to being sent. New Invoices are being sent. Bob Ross Inteconnectix, Inc. Secretary, EIA IBIS Open Forum From bob@icx.com Wed Jan 24 12:07:56 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00223; Wed, 24 Jan 96 12:07:56 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 11:59 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 12:02 PST Message-Id: Date: Wed, 24 Jan 96 12:02 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Please Disregard Test: Please Disregard From bob@icx.com Wed Jan 24 12:19:19 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00298; Wed, 24 Jan 96 12:19:19 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 12:11 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 24 Jan 96 12:13 PST Message-Id: Date: Wed, 24 Jan 96 12:13 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Please Disregard Test: Please Disregard This From bob@icx.com Thu Jan 25 10:57:19 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA05812; Thu, 25 Jan 96 10:57:19 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 25 Jan 96 10:48 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 25 Jan 96 10:51 PST Message-Id: Date: Thu, 25 Jan 96 10:51 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: MEMBERSHIP RETRANSMISSION To IBIS Members: Please DISREGARD the Invoices that were sent out for EIA/IBIS membership for 1996. An error that was discovered regarding the fees were NOT corrected prior to being sent. New Invoices are being sent. We are sorry for the inconvenience Bob Ross Inteconnectix, Inc. Secretary, EIA IBIS Open Forum From moxley@eagle.columbiasc.ncr.com Fri Jan 26 12:29:30 1996 Return-Path: Received: from chronos.synopsys.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA22906; Fri, 26 Jan 96 12:29:30 PST Received: from ncrhub5.attgis.com (h192-127-251-11.ATTGIS.COM) by chronos.synopsys.com with SMTP id AA19256 (5.65c/IDA-1.4.4 for ); Fri, 26 Jan 1996 10:17:35 -0800 Received: from ncrcae.UUCP (ncrcae@localhost) by ncrhub5.attgis.com (8.7.3/8.7.3) with UUCP id NAA17006 for vhdl.org!ibis; Fri, 26 Jan 1996 13:17:25 -0500 (EST) From: moxley@eagle.columbiasc.ncr.com Received: by ncrcae.ColumbiaSC.NCR.COM; 26 Jan 96 13:18:19 EST >From: moxley@eagle (David.Moxley) Content-Type: text Message-Id: <9601261316.ZM22861@eagle> Date: Fri, 26 Jan 1996 13:16:54 -0500 In-Reply-To: ccm.jf.intel.com!Will_Hobbs (Will Hobbs) "Final call for presentations" (Jan 19, 6:39pm) References: X-Mailer: Z-Mail (2.1.4 02apr93) To: ibis@vhdl.org Subject: IBIS Summit- Dress Code Please suggest IBIS attire. Feathers optional? Dave Moxley NCR From speters@ichips.intel.com Fri Jan 26 16:01:03 1996 Return-Path: Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24446; Fri, 26 Jan 96 16:01:03 PST Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.6.12/8.6.12) with ESMTP id PAA20093 for ; Fri, 26 Jan 1996 15:52:50 -0800 Received: from xtg801 by ichips.intel.com (8.7.1/jIII); Fri, 26 Jan 1996 15:52:47 -0800 (PST) Received: from localhost by xtg801 (4.1/10.0i); Fri, 26 Jan 96 15:52:47 PST Message-Id: <9601262352.AA08963@xtg801> To: ibis@vhdl.org Subject: Issue for electical packaging discussion Monday Date: Fri, 26 Jan 1996 15:52:46 -0800 From: Stephen Peters Hello Fellow IBISians: I think I've run across a limitation describing packages using sections. Take for example the following BGA (ball grid array) package construction bondwire trace "plating stub" driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------ZZZZZZ 0 0 ball Looking from the driver, the ball (the 'pin') is really in parellel with the plating stub - and our current description assumes that all elements are in series, with the last element being the package to board connection. That is clearly not the case. Even if one assumes that the plating stub could be modeled as a capacitor as follows: bondwire trace ball and plating stub A1 /Len=0 L=2n / Len=1.0 L=.. C=../ Len=0 L=xn C=yp / the way the spec reads it could come out as either bondwire trace pin driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------@@@@@@-- pin | --- plating stub cap --- | or bondwire trace pin driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------@@@@@@-- pin | --- --- plating stub cap | Is their some objection to explicitly stating that the order of C and L in the pin description specify the actual 'nodal' order of components in a section? Also, any idea how to describe the plating stub when the 'stub' length is as long as the trace itself and a cap model is not appropriate? Kumar and I will be discussing this at the face to face Monday Best Regards, Stephen Peters Intel Corp. From randyh Wed Jan 31 20:54:34 1996 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA00721; Wed, 31 Jan 96 20:54:34 PST Date: Wed, 31 Jan 96 20:54:34 PST From: randyh (Randy Harr) Message-Id: <9602010454.AA00721@vhdl.vhdl.org> To: ibis Subject: Sorry, another test, please ignore Test message From bob@icx.com Wed Jan 31 23:33:06 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA01894; Wed, 31 Jan 96 23:33:06 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:24 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:27 PST Message-Id: Date: Wed, 31 Jan 96 23:27 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Test Message Please Disregard this and Ignore some previous, OLD messages to fix the ibis reflector problem. From bob@icx.com Wed Jan 31 23:50:25 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02010; Wed, 31 Jan 96 23:50:25 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:42 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:44 PST Message-Id: Date: Wed, 31 Jan 96 23:44 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS REFLECTOR To IBIS reflector members The ibis@vhdl.org reflector is working again. The problem is still not fully understood, but seems to be related to how vhdl.org handles some compuserve addresses. They have been temporarily removed and will be handled privately. The ibis-users@vhdl.org may still be down. I get the messages, but no one else gets them. You will be advised when it is working. Bob Ross, Interconnectix, Inc. From bob@icx.com Wed Jan 31 23:56:48 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02027; Wed, 31 Jan 96 23:56:48 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:48 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:51 PST Message-Id: Date: Wed, 31 Jan 96 23:51 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: RESENT MESSAGE - PACKAGE MODEL ... RESENT MESSAGE To: ibis@vhdl.org Subject: Issue for electical packaging discussion Monday Date: Fri, 26 Jan 1996 15:52:46 -0800 From: Stephen Peters Hello Fellow IBISians: I think I've run across a limitation describing packages using sections. Take for example the following BGA (ball grid array) package construction bondwire trace "plating stub" driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------ZZZZZZ 0 0 ball Looking from the driver, the ball (the 'pin') is really in parellel with the plating stub - and our current description assumes that all elements are in series, with the last element being the package to board connection. That is clearly not the case. Even if one assumes that the plating stub could be modeled as a capacitor as follows: bondwire trace ball and plating stub A1 /Len=0 L=2n / Len=1.0 L=.. C=../ Len=0 L=xn C=yp / the way the spec reads it could come out as either bondwire trace pin driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------@@@@@@-- pin | --- plating stub cap --- | or bondwire trace pin driver @@@@@--ZZZZZZZZZZZZZZZZZZZ------@@@@@@-- pin | --- --- plating stub cap | Is their some objection to explicitly stating that the order of C and L in the pin description specify the actual 'nodal' order of components in a section? Also, any idea how to describe the plating stub when the 'stub' length is as long as the trace itself and a cap model is not appropriate? Kumar and I will be discussing this at the face to face Monday Best Regards, Stephen Peters Intel Corp. From bob@icx.com Wed Jan 31 23:58:59 1996 Return-Path: Received: from icx.com (icx.rain.com) by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02032; Wed, 31 Jan 96 23:58:59 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:50 PST Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jan 96 23:53 PST Message-Id: Date: Wed, 31 Jan 96 23:53 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Forwarded: MEMBERSHIP SECOND RETRANSMISSION (FIRST FAILED) Note, new invoices should have been sent. Date: Thu, 25 Jan 96 10:51 PST From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: MEMBERSHIP Status: RO RETRANSMISSION To IBIS Members: Please DISREGARD the Invoices that were sent out for EIA/IBIS membership for 1996. An error that was discovered regarding the fees were NOT corrected prior to being sent. New Invoices are being sent. We are sorry for the inconvenience Bob Ross Inteconnectix, Inc. Secretary, EIA IBIS Open Forum -------- End of Forwarded Message