From owner-ibis Mon Jul 1 07:16:19 1996 Received: from VNET.IBM.COM (vnet.ibm.com [199.171.26.4]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id HAA04833 for ; Mon, 1 Jul 1996 07:16:18 -0700 (PDT) Received: from RCHLAND by VNET.IBM.COM (IBM VM SMTP V2R3) with BSMTP id 1470; Mon, 01 Jul 96 10:06:47 EDT Reply-To: "Joe Cahill" Received: by po1 (AIX 3.2/UCB 5.64/4.7) id for ibis@vhdl.org; Mon, 1 Jul 1996 09:04:49 -0500 Received: via switchmail; Mon, 1 Jul 1996 09:04:49 -0500 (CDT) Received: from santana.rchland.ibm.com via qmail ID ; Mon, 1 Jul 1996 09:04:44 -0500 (CDT) Received: from santana.rchland.ibm.com via qmail ID ; Mon, 1 Jul 1996 09:04:40 -0500 (CDT) Received: from Messages.8.5.N.CUILIB.3.45.SNAP.NOT.LINKED.santana.rchland.ibm.com.rs.aix41 via MS.5.6.santana.rchland.ibm.com.rs_aix41; Mon, 1 Jul 1996 09:04:39 -0500 (CDT) Message-Id: Date: Mon, 1 Jul 1996 09:04:39 -0500 (CDT) From: Joe Cahill To: ibis@vhdl.org Subject: Closing the loop I am no expert at tieing test specifications with design specifications, but I would like to express some words of caution. In a nutshell testing implies to me some sort of guarantee, guarantees imply some additional inaccuracy, and some additional schedule time. I would rather have the design engineer's best guess as to the performance of their devices, when they have the design far enough along to make that determination. Testing to a specification means that you have to account for the tester tolerances, the noise in the tester environment, and if you have a sampled test scheme, some additional guardband for the non-sampled parts. All of this to prevent 'bad' parts from testing as good. In my experience, there is a fair amount of pressure to have the test specification guardband the desired device performance, and to have the published specification guardband the test specification. Users end up with published specifications that predict performance that is dramatically different from the performance of the delivered parts. The additional time in the schedule comes because you have to involve test organizations and some non-trivial sample of hardware before your test specification becomes firm. Invariably the test specification changes as the design engineer and the test organization learn about a particular part. To close the loop, I would suggest you consider the hardware your silicon modellers use to build the simulation models for the devices, and the prototype hardware you build. Joe Cahill - VLSI Development From owner-ibis Tue Jul 2 10:06:01 1996 Received: (from jonp@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id KAA05185 for ibis; Tue, 2 Jul 1996 10:06:01 -0700 (PDT) Date: Tue, 2 Jul 1996 10:06:01 -0700 (PDT) From: Jon Powell Message-Id: <199607021706.KAA05185@vhdl.vhdl.org> To: ibis Subject: new Pentium Pro Model INTEL has release an updated pentium pro model for 200Mghz Pentium Pro. New Ibis file is pent200.ibs. pentpro.ibs is now obsolete and has (on request) been removed from active IBIS release area. Additional .txt files describing packaging are also available. jon ibis librarian From owner-ibis Tue Jul 2 15:55:42 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id PAA08322 for ; Tue, 2 Jul 1996 15:55:38 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 2 Jul 96 15:45 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 2 Jul 96 15:45 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 2 Jul 96 15:48 PDT Message-Id: Date: Tue, 2 Jul 96 15:48 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS Minutes 6/28/96 DATE: July 2, 1996 SUBJECT: 6/28/96 EIA IBIS Open Forum Minutes VOTING MEMBERS AND 1996 PARTICIPANTS LIST: AMP Hank Herrmann*, Tim Minnick, Russ Moser Cadence Design C. Kumar Contec CAE, Ltd. Dileep Divekar*, Norio Matsui, Antonis Orphanou Cypress Bruce Wenniger Hewlett Packard, EEsof Karl Kachigan, Henry Wu HyperLynx Kellee Crisafulli* INCASES Olaf Rethmeier*, Ralf Bruening Intel Corporation Stephen Peters*, Will Hobbs*, Arpad Muranyi*, John Keifer, Aaron Tang, Duane Quiet, [Donald Telian], Jim Kruchowski Interconnectix, Inc. Bob Ross, Chris Reid* Meta-Software (Sanjay Gangal) Mitsubushi Tam Cao, Hoang Nguyen Motorola Ahmed Omer National Semiconductor Syed Huq*, Donald Snyder, Chune-Sin Yeh, Bill Aronson NCR (formerly ATT-GIS) Dave Moxley*, Richard Mellitz NEC (Hiroshi Matsumoto), Quad Design Jon Powell*, Chris Rokusek* Texas Instruments Roger Cline, Ben Andresen, Sri Jandhyala, Tareq Shahwan, Dan Phipps Thomson-CSF/SCTF (Jean LeBrun) UniCAD Canada Ltd. Celso Faia* VLSI Technology Dick Ulmer, Sung Oh, Swami Gangadharan, Daniel Kim, Tom Dockery, D.C. Sessions Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1996: Alcatel John Fitzpatrick* Altera Vadim von Brzeski Apteq Design System Dan FitzPatrick Compaq Mark Leonard Digital Equipment Corp. Jeff Chu* EIA Patti Rusher* IC Works Eric Chen Micron Technology Brian Johnson MicroSim Ralph Perez Molex Gus Panella North Carolina State U. (Michael Steer) Oki Semiconductor Tom Chao Philips Semiconductor Mike Magdaluyo Rockwell Collins Thomas Thurman S3, Inc. Sarathy Sribhashyam, Phap Duong Seimans Nixdorf Arnaud Lacariere Symmetry Andy Hughes Tektronix, Inc. Brock Hannibal TRW & Free Model Foundation Robert Harrison Veribest Ian Dodd, David Wiens VTC, Inc. Bob Ward Zeelan Technology George Opsahl In the list above, attendees at the meeting are indicated by *. Principle members or other active members who have not attended are in parentheses. Participants who have joined another organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 7/19/96 (916) 356-9200 2-78903 6186335 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS Syed Huq chaired the meeting, and Jon Powell served as secretary. (These minutes are based on Jon's and Will Hobb's notes and other inputs.) EIA MEMBERSHIP AND TREASURER'S REPORT Patti Rusher did not have updated figures, but estimates the treasury at about $6000 to $8000. The treasurer's report was garbled due to a bug in Patti's program. EIA will issue a new report soon. AMP's invoice situation has been taken care of for now. MINUTES REPORT, MISC. The spelling Peivand Tehrani's last name has been corrected, and the paper is on page 1009 of the conference proceedings. The last meetings 9 AM to 1 PM times and Las Vegas, Nevada location have been added to the minutes. All previous AR's were handled including issuing BIRD36 and BIRD37 and data related to multi-staged driver models. MISCELLANY/ANNOUNCEMENTS None. PRESS AND WEB PAGE UPDATES Electronic Design, June 10, 1996, page 64, a HyperLynx introduction references IBIS. Electrical Engineering Times, June 17, 1996, pg. 86, a Veribest introduction references IBIS. Electronic News, June 17, 1996, pg. 46, Symmetry Design Systems announces IBIS modeling service and future models. The 1996 National Interface Databook, Chapter 13 on Modeling Support is devoted entirely to IBIS models and provides "An Introduction to IBIS Modeling Section" by Syed Huq, and also references many of the participating IBIS Committee CAE vendors and their tools. VLSI IBIS models are now available on the Web: http://www.vlsi.com/vlsi/products/ibis/ibis.html The EIA/IBIS web page has been enhanced to add tools selection. Quad Design is adding a page with hot links to all free IBIS models available throughout industry. Patti Rusher reports that the IBIS page is the second most popular EIA page. NEW MODELS None reported. OPENS FOR NEW ISSUES Secretary Position Series Resistor INTERNATIONAL STANDARDIZATION Patti Rusher Indicated that there is a project underway to gain money from DARPA for modeling programs. The intention is to use the money to fill holes in the standards efforts, such as funding the Express Model. This is problematic since the University of Manchester can not receive US grant money directly. They would have to be sub-contracted through a US company or university. Some funding options exist and there may be some news in several weeks. Will Hobbs and Stephen Peters will give a presentation on modeling standards at an international conference in Prague in July, 1996. AR - Stephen Peters and Will Hobbs will discuss the money and time for Express Representation with Hilary Kahn in Prague at an international standards conference. Ron Waxman has introduced IBIS as a work item into the IEC process. So even without Express, the international standardization process is underway. SECRETARY Will Hobbs feels that the lack of a secretary needs resolution. For now we are sharing the duty from meeting to meeting. No one at the meeting indicated an interest in taking the post. This must be a person from a member company since it is an official EIA committee position. AR - Syed Huq post a request to ibis@vhdl.org requesting volunteers. EGG11 - ABSOLUTE MAXIMUM VOLTAGE John Fitzpatrick of Alcatel requested a field be added to the model to specify the maximum voltage that can be sustained without damage. Semiconductor suppliers do not generally want to give out this information. The issue is important for PCI interface components and components with split supplies. One use for this information would be to have the simulator pop out a warning if the maximum voltage limits (voltage versus time) is exceeded. This could be handled on a per-model basis, as an optional parameter or parameters. It might need to be a table. Jon Powell asked if it was a non-linear table. John indicated that it could be highly non-linear. This information could be tabulated like the other IBIS tables. It could also be a single value. Both positive and negative voltages would be tabulated. Kellee Chrisafulli pointed out that it may have to be power supply relative, such as one diode over Vcc. John plans to accept the comments and convert this into a BIRD. Several EDA vendors indicated that they would support issuing a message that indicates that the maximum safe levels have been exceeded. BIRD36 - ELECTRICAL BOARD DESCRIPTION Stephen Peters issued BIRD36 for an electrical board description. Hank Herrmann provided several comments: (1) Add a NC (No Connect) in the pin list for open sided connectors (2) Strike the word "mated" (for unmated models) (3) Change minimum "rise" time to minimum "edge" time. (4) Set a limit on the total number of externally accessible pins. (5) Set a 5 character limit for the total number of pins. (6) Change the maximum number of characters from 5 to 8 under [Pin List] (7) Under [Path Description] the for node, the subparameter could be a .ibs model. The discussion involved whether IBIS would allow an .ebd file to describe a populated SIMM, for example. There was a long discussion on whether this should be allowed to be embedded within a .ibs file, or visa-versa (making the IBIS Specification very complex), or to keep it as a separate file. The consensus was to keep it separate. The golden parser will still have to check .ebd files. It would be desirable to allow a .ebd file to contain a reference to another .ebd file, to support situations such as SIMMs that plug into SIMMs. Kellee Chrisafulli suggests we roll the BIRD such that the component can be either a .ibs or a .ebd file, and solicit further comments. Kellee was also concerned about the ambiguity of unit length. He feels it should be explicitly specified to be treated as distributed LRC elements in the section where the length is specified. Stephen will make this change. Chris Reid of Interconnectix noted that the pin number section has a potential problem with matrix creation when there is a mismatch between pin count and path count. If a 16 pin connector has 32 pins, how do you define the matrix? You would want a 16 X 16 matrix, not a 32 X 32 matrix. A few more examples would help. The specific changes were: (1) Add a keyword for reference designator mapping (ibs/ebd file and component). (2) Highlight that RLC are distributed. (3) Consider Hank's email comments. (4) Specify which pins are used in the matrix (or drop the matrix). The matrix issue needs to be reviewed. (5) What are the boundaries of the model. Where does one model end and another begin. It was suggested that Stephen roll in the suggested changes and issue BIRD36.1 for a possible vote next meeting. BIRD35.1 - MULTI-STAGED OUTPUTS Jon Powell described BIRD35.1 as a method for scheduling sequences of output buffer characteristics. The technical discussion was deferred until Bob Ross, author of BIRD35.1 can participate at the next meeting. Jon noted the primary problem with this type of output is that there is no way to create a model via measurement. Such buffers are usually implemented with internal delay lines to which measurements have no access. Only the chip manufacturer would have access to this information. However, the conclusion was that BIRD35.1 is ready for a vote. EGG10 - PARSER ADDITIONS FOR NUMERICAL CHECKING Chris Rokusek stated that EGG10 checks for reasonable values in IBIS files. Chris has extracted all of the parameters out of an IBIS file and found some out of range values. The raw data can be analyzed and discussed at the next meeting. Arpad Muranyi noted that the data format of the files that were sent out were inaccessible to him. (The data was retransmitted in ASCII form.) SERIES RESISTOR Arpad Muranyi suggested that we add support for series devices such as diodes and resistors to IBIS 3.0. Jon Powell felt this was OK as long as the component could be specified as a V/I curve. NEXT MEETING: The next meeting is on Friday, July 19, 1996, 8:00 A.M. to 10:00 A.M. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469 bob@icx.com Modeling Engineer, Interconnectix, Inc. 10220 SW Nimbus Ave, K4, Portland, OR 97223 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Transmission-Line Products Manager, Quad Design 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Vacant This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@vhdl.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org) or both. State your request. ibis-info@vhdl.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@vhdl.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. ibis-users@vhdl.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. ibischk-bug@vhdl.org To report ibischk2 parser bugs. The Bug Report Form Resides on vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an e-mail request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Thu Jul 4 11:26:14 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id LAA02459 for ; Thu, 4 Jul 1996 11:26:12 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Thu, 4 Jul 96 11:16 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 4 Jul 96 11:16 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Thu, 4 Jul 96 11:19 PDT Message-Id: Date: Thu, 4 Jul 96 11:19 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: BIRD38 Maximum Voltage Below is a proposal to include maximum input voltage specifications in an IBIS model. The key elements are: i) A new keyword [Maximum Voltage] is added per buffer model ii) Maximum inputed voltage tolerated as a function of time is given in a table Two examples are included to explain why this information might be useful to a board designer. *********************************************************************** BIRD ID#: 38 ISSUE TITLE: Maximum Voltage REQUESTER: John Fitzpatrick, Alcatel DATE SUBMITTED: July 03, 1996 DATE ACCEPTED BY IBIS OPEN FORUM: Pending *********************************************************************** STATEMENT OF THE ISSUE: IBIS can be extended to allow a component supplier specify maximum positive and negative voltages (or currents) that can safely be applied to an I/O buffer. These limits are expressible as a function of time to give maximum flexibility to board designers. Note: Because IBIS simulation data is provided from -Vcc to 2Vcc, a non-specialist might wrongly believe that these are the limits on the applied voltage. *********************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Add the following keyword after the [Model] keyword: |===================================================================== | | Keywords: [Maximum Voltage] | | Required: Yes, unless the component works for all simulation points | | Description: Defines the maximum positive and negative voltages | that can safely be applied to an I/O buffer. | | Sub-params: POWER_Clamp_Reference, Pullup_Reference | | Usage Rules: This keyword defines a table of voltage versus time points. | The table contains a minimum of three and a maximum of five | columns: | 1- time | 2- maximum positive voltage for hi-Z state (tri-state) | 3- maximum negative voltage for hi-Z state | 4- maximum positive voltage for lo-Z (active) state | 5- maximum negative voltage for lo-Z state | Entries for lo-Z (active) state are included only if the limits | are different than in hi-Z state (3-state). | | Negative voltage are referenced to GND. | | Positive voltages are referenced to either the positive supply | rail or to GND, according to the following rules: | | If POWER_Clamp_Reference=yes then the maximum positive | voltage for hi-Z state is referenced to [POWER Clamp | Reference]. | Otherwise it is referenced to GND. | | If maximum voltages are specified for the lo-Z (active) state: | If Pullup_Reference=yes, then the maximum positive voltage | for the active state is referenced to [Pullup Reference]. | Otherwise it is referenced to GND. | | The last entries in the table are the static absolute maximum | voltages. | | When a waveform exceeds a static voltage, the simulator will | set time=0, then check that the rest of the waveform is | within the dynamic limits given in the table. | | Other Notes: | | A) How to specify/calculate maximum current | | It is not possible to directly specify the maximum applied | current. However, as the [Pullup], [POWER Clamp], [Pulldown] | and [GND Clamp] are known, the input impedance (R) can be | calculated. Using Ohm's law, the maximum voltage which | correspond to a maximum current is easily found (I=V/R). | | B) What values to specify | | When specifying limits, the component supplier might take | into account the following situations where the static | maximum ratings will be exceeded: | | 1) Reflections: | - An over- or undershoot can last for less than 20ns. | - If there are no clamping diodes, the buffer should | tolerate applied voltages from -Vcc to 2Vcc (CMOS buffer) | - If there are clamping diodes, the buffer should tolerate | applied currents from -Vcc/Z to Vcc/Z (CMOS buffer), | where Z is the track impedance. Usually Z > 40 ohms. | | 2) Power supply failure | - In a multi-supply design (e.g. mixed 5V/3V bus), a | buffer should tolerate excess applied voltages(dV) | and currents(I) from the time its power supply fails until | all connected outputs are disabled (time Tfail later). | Tfail < 50us | I < 250mA | dV < 3.3V (e.g. 5V buffer on mixed 5V/3V bus) | | Note: The simulator will assume that the section of the | [POWER clamp] table above Vcc can be used (shifted?) for all | values of supply voltage from 0 to Vcc. | | C) Relationship with RAIL | | The RAIL standard allows for a single-value dynamic undershoot | and overshoot to be specified. A single value overshoot | value can be extracted from an IBIS file by averaging the | maximum voltage over a short timeframe e.g. 20 ns. | | D) Examples | | The example below could represent a CMOS output, with a | permanent clamping diode to GND, and a clamping diode to | Vcc in active state only: | [Maximum Voltage] | Pullup_reference=yes POWER_clamp_reference=no | | Time Vpos(3-state) Vneg(3-state) Vpos(active) Vneg(active) 0 7 -2 2 -2 20ns 7 -2 2 -2 30ns 5.5 -1.5 1.5 -1.5 50us NA -1 1 -1 100us 5.5 -0.5 0.5 -0.5 | *********************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: The manner in which absolute maximum ratings are given in paper databooks is extremely conservative. Typically, the board designer is expected to guarantee that the voltage V applied to a buffer be in the range -0.5V < V < Vcc+0.5V. (*) Most board designers know that these limits are often exceeded in their designs due to reflections, without any harm being done to the component. They would however like to have real risks flagged by a simulator. In multiple power supply designs (e.g. mixed 3.3V/5V), it is possible to have "5V tolerant" 3.3V buffers. But what happens if one of the power supply fails? The designer would like to know if it is sufficient to disable all output buffers, and if so, within what time-frame. Some suppliers specify the absolute max voltage as a function of Vcc, others tolerate any voltage up to a limit (usually 7V), even if Vcc is set to 0V. The sub-parameter POWER_Clamp_Reference allows this distinction to be taken into account. Some 3.3V CMOS components (e.g. 74LVCxxx, 74LCXxxx) have output clamping diodes in the active state only. Optional columns are included to allow this fact be taken into account. This proposal is simply an extension of the existing absolute maximum ratings, with the additional parameter: time. Any supplier who wishes to be "customer-unfriendly" by continuing to specify (*) can write: [Maximum Voltage] | POWER_clamp_reference=yes | | Time Vpos(3-state) Vneg(3-state) 0 0.5 -0.5 *********************************************************************** ANY OTHER BACKGROUND INFORMATION: This BIRD has been inspired by the PCI bus specification. The relevant references are (Rev 2.0): 4.2.1.3 Maximum AC ratings and Device Protection (5V) 4.2.2.3 Maximum AC ratings and Device Protection (3.3V) 4.3.2 Reset *********************************************************************** From owner-ibis Tue Jul 9 00:03:08 1996 Received: from montana.nwlink.com (kellee@montana.nwlink.com [199.242.23.13]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id AAA15908 for ; Tue, 9 Jul 1996 00:03:05 -0700 (PDT) Received: (from kellee@localhost) by montana.nwlink.com (8.7.4/8.7.3) id XAA13527; Mon, 8 Jul 1996 23:53:12 -0700 (PDT) Message-Id: <2.2.32.19960709065055.006dd940@mail.nwlink.com> X-Sender: kellee@mail.nwlink.com X-Mailer: Windows Eudora Pro Version 2.2 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Mon, 08 Jul 1996 23:50:55 -0700 To: ibis@vhdl.org From: Kellee Crisafulli Subject: How can an author get permission to use V1.1 IBIS Greetings, An author writing a book on signal integrity contacted me with interest in putting a copy of the IBIS V1.1 specification in his book and on a CD ROM with the BOOK. He is sending me a copy of an agreement to release the specification to his publisher. Could our newly elected Chairperson/ vice-chair authorize this? Please let me know and I will forward the release form to you. I know we can't release V2.1, but it is my understanding that V1.1 is still totally in the public domain. Have a great day...Kellee Crisafulli, HyperLynx Inc. From owner-ibis Tue Jul 9 08:29:58 1996 Received: from calliope.fm.intel.com (calliope.fm.intel.com [132.233.247.7]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id IAA04416 for ; Tue, 9 Jul 1996 08:29:57 -0700 (PDT) Received: from fmmail.fm.intel.com by calliope.fm.intel.com (8.7.4/10.0i); Tue, 9 Jul 1996 15:21:28 GMT Received: (from ccmgate@localhost) by fmmail.fm.intel.com (8.7.4/8.7.3) id IAA27290 for ibis@vhdl.org; Tue, 9 Jul 1996 08:16:45 -0700 (PDT) Received: by ccm.fm.intel.com (ccmgate 3.2 #2) Tue, 09 Jul 96 08:16:45 PDT Date: Tue, 09 Jul 96 08:05:00 PDT From: Arpad Muranyi Message-ID: To: ibis@vhdl.org Subject: Re: How can an author get permission to use V1.1 IBIS Text item: Kellee, It would be nice if he could get permission for the V2.1 for printing/publishing. I believe in promoting the latest and greatest, and not something that is old and/or outdated. By the time the book will appear, we might even have V3.0 ready... Is there a way to arrange for that? Arpad ============================================================================== Greetings, An author writing a book on signal integrity contacted me with interest in putting a copy of the IBIS V1.1 specification in his book and on a CD ROM with the BOOK. He is sending me a copy of an agreement to release the specification to his publisher. Could our newly elected Chairperson/ vice-chair authorize this? Please let me know and I will forward the release form to you. I know we can't release V2.1, but it is my understanding that V1.1 is still totally in the public domain. Have a great day...Kellee Crisafulli, HyperLynx Inc. Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: How can an author get permission to use V1.1 IBIS From: Kellee Crisafulli To: ibis@vhdl.org Date: Mon, 08 Jul 1996 23:50:55 -0700 Content-Type: text/plain; charset="us-ascii" Mime-Version: 1.0 X-Mailer: Windows Eudora Pro Version 2.2 (32) X-Sender: kellee@mail.nwlink.com Message-Id: <2.2.32.19960709065055.006dd940@mail.nwlink.com> Received: (from kellee@localhost) by montana.nwlink.com (8.7.4/8.7.3) id XAA1352 7; Mon, 8 Jul 1996 23:53:12 -0700 (PDT) Received: from montana.nwlink.com (kellee@montana.nwlink.com [199.242.23.13]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id AAA15908 for ; Tue, 9 Jul 1996 00:03:05 -0700 (PDT) Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by mailbag.jf.intel.c om (8.7.4/8.7.3) with ESMTP id XAA07034; Mon, 8 Jul 1996 23:57:43 -0700 (PDT) Received: from mailbag.jf.intel.com (root@mailbag.jf.intel.com [134.134.248.4]) by relay.jf.intel.com (8.7.4/8.7.3) with ESMTP id XAA19871; Mon, 8 Jul 1996 23:5 8:38 -0700 (PDT) Return-Path: owner-ibis@vhdl.vhdl.org From owner-ibis Tue Jul 9 09:28:16 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id JAA04997 for ; Tue, 9 Jul 1996 09:28:16 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 9 Jul 96 09:18 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 9 Jul 96 09:18 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 9 Jul 96 09:21 PDT Message-Id: Date: Tue, 9 Jul 96 09:21 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org, kellee@hyperlynx.com Subject: Re: How can an author get permission to use V1.1 IBIS Kellee: Please forward or have the author forward the release form to me. I and EIA will review it. As Arpad noted, Version 2.1 is the current ANSI/EIA-656 Standard and the most appropriate one to publish. EIA owns the copyright to this, but as a policy, will allow republication of this in various forms such as Vendor's manuals, books, etc. A nominal fee is required (which will go directly into the IBIS committee account). People who wish to republish ANSI/EIA-656 or portions of it can contact EIA directly: Patti Rusher, Director EIA/Electronic Information Group 2500 Wilson Blvd. Arlington, VA 22201 (703) 907-7545 We could allow republishing Version 1.1. While it was established as an official release, there have been text and other subtle changes which render it almost as a working draft status for the preparation of the official Version 2.1 release. We would require a disclaimer that the official ANSI/EIA-656 Standard contains substantial additions and changes over the Version 1.1 release. Bob Ross Chair, EIA/IBIS Committee Interconnectix, Inc. > Date: Mon, 08 Jul 1996 23:50:55 -0700 > To: ibis@vhdl.org > From: Kellee Crisafulli > Subject: How can an author get permission to use V1.1 IBIS > Status: R > Greetings, > An author writing a book on signal integrity contacted > me with interest in putting a copy of the IBIS V1.1 specification > in his book and on a CD ROM with the BOOK. > He is sending me a copy of an agreement to release the specification > to his publisher. > Could our newly elected Chairperson/ vice-chair authorize this? > Please let me know and I will forward the release form to you. > I know we can't release V2.1, but it is my understanding that V1.1 > is still totally in the public domain. > > Have a great day...Kellee Crisafulli, HyperLynx Inc. From owner-ibis Tue Jul 9 11:29:28 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id LAA06185 for ; Tue, 9 Jul 1996 11:29:27 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 9 Jul 96 11:19 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 9 Jul 96 11:19 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 9 Jul 96 11:22 PDT Message-Id: Date: Tue, 9 Jul 96 11:22 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS Model Contact People IBIS Committee: I have put a slightly updated version of contacts.txt under /pub/ibis/roster on vhdl.org to provide some direct contact names for IBIS models. Bob Ross Interconnectix, Inc. From owner-ibis Fri Jul 12 12:28:37 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id MAA20519 for ; Fri, 12 Jul 1996 12:28:36 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Fri, 12 Jul 96 12:18 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 12 Jul 96 12:18 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Fri, 12 Jul 96 12:21 PDT Message-Id: Date: Fri, 12 Jul 96 12:21 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS AGENDA 7/19/96 IBIS Open Forum Meeting Agenda for 7/19/96 Bridge Number Reservation # Passcode (916) 356-9200 2-78903 6186335 All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the Reservation Number and Passcode. 8:00 Check-In, Intros, Announcements Ross - Intros of New IBIS Participants, Meeting Quorum Ross - Membership Update and Treasurers Report Rusher - Review of Previous Meeting's Minutes (and ARs) Ross - Miscellany/Announcements All - Press & Web Page Updates Huq, All - New Models Available, Library Update Powell, All - Opens for New Issues All 8:25 Administrative and Project Discussions IEC Express Funding Progress Rusher EE Times Article Ross New Administrative Issues All 8:35 Technical Discussion BIRD34.1 - STORED CHARGE EFFECT Ross BIRD35.1 - MULTI-STAGED OUTPUTS Ross BIRD36 - ELECTRICAL BOARD DESCRIPTION All BIRD37 - ENHANCEMENT TO THE PACKAGE MODEL SPEC. All BIRD38 (EGG11) - ABSOLUTE MAXIMUM VOLTAGE Fitzpatrick SERIES RESISTANCE Muranyi EGG10 - PARSER TESTS 1-5 Rokusek New Technical Issues All 9:50 Wrap Up and Next Meetings Plans Ross 9:55 Sign Off From owner-ibis Tue Jul 16 08:14:01 1996 Received: from natsemi-bh.nsc.com (natsemi-bh.nsc.com [204.163.202.66]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id IAA25081 for ; Tue, 16 Jul 1996 08:14:01 -0700 (PDT) Received: (from uucp@localhost) by natsemi-bh.nsc.com (8.6.12/8.6.11) id IAA07672 for ; Tue, 16 Jul 1996 08:05:06 -0700 Received: from nsc.nsc.com by natsemi-bh.nsc.com via smap (V1.3) id sma007624; Tue Jul 16 08:05:04 1996 Received: from lightning-gw.nsc.com by nsc.nsc.com (5.65/1.34) with SMTP id AA18263 for ibis@vhdl.org; Tue, 16 Jul 96 08:04:03 -0700 Received: from kural by rockie.nsc.com (4.1/SMI-4.1) id AA03868; Tue, 16 Jul 96 08:07:49 PDT Date: Tue, 16 Jul 96 08:07:49 PDT From: huq@rockie.nsc.com (Syed Huq) Message-Id: <9607161507.AA03868@rockie.nsc.com> To: ibis@vhdl.org Subject: Officer wanted ! Cc: huq@rockie.nsc.com IBISfans: As you may know already, new officers for the ANSI/EIA-656 were elected in the last DAC(Las Vegas) IBIS summit. There was one position for 'secretary' that was not filled. This is an official position and we need a volunteer from a member company to fill this slot. A lot of exciting things are being planned to move the IBIS standard towards version 3.0 and International standardization too. Since we meet regularly through teleconferences, it is quite difficult to move along with this much needed 'vacant' officers slot. This is an open invitation for any member company to jump in and volunteer for this official ANSI/EIA-656 Secretary position. Bob Ross can fill in with responsibility issues under this position if you are curious to know. Join us for the July 19th meeting and let's take care of this issue. All out efforts are very much team oriented and we can all help each other out with tasks. Meeting are conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. See you .. Regards, Syed Huq Vice-Chair ANSI/EIA-656 National Semiconductor Corp. From owner-ibis Fri Jul 19 15:03:27 1996 Received: from bingnet1.cc.binghamton.edu (bingnet1.cc.binghamton.edu [128.226.1.11]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id PAA13225 for ; Fri, 19 Jul 1996 15:03:23 -0700 (PDT) Received: from ee1-gw.ee.binghamton.edu (ee1-gw.ee.binghamton.edu [128.226.171.73]) by bingnet1.cc.binghamton.edu (8.7.3/8.6.9) with SMTP id RAA00871; Fri, 19 Jul 1996 17:53:12 -0400 (EDT) Received: by ee1-gw.ee.binghamton.edu (AIX 3.2/UCB 5.64/4.03) id AA21360; Fri, 19 Jul 1996 17:50:11 -0400 Date: Fri, 19 Jul 1996 17:50:11 -0400 (EDT) From: "Peivand F. Tehrani" To: Bob Ross Cc: ibis@vhdl.org Subject: Stored Charge In-Reply-To: Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello IBIS fans, I was reviewing the stored charge BIRD 34.1 . I have observed the same glitch effect even with ESD diodes removed. So I think this glitch is not just created by the stored charge in the diodes. This glitch can easily be observed with a simple CMOS invertor with a fast (100 psec) ramp as the input of the invertor, I think this glitch is because of the stored charge in the depletion region of upper and lower devices. I will send a simple SPICE file that I have been using to simulate this effect. The SPICE version which I am using runs into convergence problems if I remove Cd1 capacitor. This capacitor presents the die capacitor in IBIS models. After the simulation the voltage at node 2 should be probed. Best Regards, Peivand Tehrani. **************************SPICE file************************ Driver Device Transitions For Gate Transition ************************************************************* VDD 3 0 5 ************************************************************* M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6 M2 2 1 3 3 QP L=1.5E-6 W=341E-6 ************************************************************* .MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 ) .MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200) ************************************************************* VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3) ************************************************************* Cd1 2 0 4p R11 2 0 50 ************************************************************* .tran .001n 1n .END From owner-ibis Tue Jul 23 08:42:52 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id IAA26431 for ; Tue, 23 Jul 1996 08:42:34 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 23 Jul 96 08:32 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 23 Jul 96 08:32 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 23 Jul 96 08:35 PDT Message-Id: Date: Tue, 23 Jul 96 08:35 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: IBIS Minutes 7/19/96 DATE: July 23, 1996 SUBJECT: 7/19/96 EIA IBIS Open Forum Minutes VOTING MEMBERS AND 1996 PARTICIPANTS LIST: AMP Hank Herrmann*, Tim Minnick*, Russ Moser Cadence Design C. Kumar Contec CAE, Ltd. Dileep Divekar*, Norio Matsui, Antonis Orphanou Cypress Bruce Wenniger Hewlett Packard, EEsof Karl Kachigan, Henry Wu HyperLynx Kellee Crisafulli INCASES Olaf Rethmeier, Ralf Bruening Intel Corporation Stephen Peters*, Will Hobbs, Arpad Muranyi*, John Keifer, Aaron Tang, Duane Quiet, [Donald Telian], Jim Kruchowski Interconnectix, Inc. Bob Ross*, Chris Reid Meta-Software (Sanjay Gangal) Mitsubushi Tam Cao, Hoang Nguyen Motorola Ahmed Omer* National Semiconductor Syed Huq*, Donald Snyder, Chune-Sin Yeh, Bill Aronson NCR (formerly ATT-GIS) Dave Moxley*, Richard Mellitz NEC (Hiroshi Matsumoto), Quad Design Jon Powell*, Chris Rokusek Texas Instruments Roger Cline, Ben Andresen, Sri Jandhyala, Tareq Shahwan, Dan Phipps Thomson-CSF/SCTF (Jean LeBrun) UniCAD Canada Ltd. Celso Faia* VLSI Technology Dick Ulmer, Sung Oh, Swami Gangadharan, Daniel Kim, Tom Dockery, D.C. Sessions*, Hrish Patel* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1996: Alcatel John Fitzpatrick Altera Vadim von Brzeski Apteq Design System Dan FitzPatrick Compaq Mark Leonard Digital Equipment Corp. Jeff Chu* EIA Patti Rusher* IC Works Eric Chen Micron Technology Brian Johnson MicroSim Ralph Perez Molex Gus Panella North Carolina State U. (Michael Steer) Oki Semiconductor Tom Chao Philips Semiconductor Mike Magdaluyo Rockwell Collins Thomas Thurman S3, Inc. Sarathy Sribhashyam, Phap Duong Seimans Nixdorf Arnaud Lacariere Symmetry Andy Hughes Tektronix, Inc. Brock Hannibal TRW & Free Model Foundation Robert Harrison Veribest Ian Dodd, David Wiens VTC, Inc. Bob Ward Zeelan Technology George Opsahl In the list above, attendees at the meeting are indicated by *. Principle members or other active members who have not attended are in parentheses. Participants who have joined another organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode 8/16/96 (916) 356-9200 2-88344 6838524 9/6/96 (916) 356-9200 2-88345 4511183 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each open forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS Hrish Patel joined for the first time from VLSI Technology to become familiar with IBIS, since he will be working on IBIS models. EIA MEMBERSHIP AND TREASURER'S REPORT Patti Rusher's June 30, 1996 report shows $10,468. Several thousand dollars of DAC meeting and other item expenses are expected to show up in the July 31, 1996 report. Invoices are still being tracked for DEC and Veribest memberships. MINUTES REPORT, MISC. No change. All AR's have been dealt with. MISCELLANY/ANNOUNCEMENTS Jon Powell has agreed to handle the system administrative aspect of the IBIS vhdl.org account (Membership additions, deletions, response to problems, questions, and posting material) while Bob Ross is on vacation August 1 through August 13. PRESS AND WEB PAGE UPDATES Syed Huq plans to add links in the EIA/IBIS home page to public IBIS model databases that Jon Powell provided. Jon has checked this out and they appear good. (Patti Rusher reports over 2500 hits on the EIA/IBIS home page.) AR - Syed Huq activate links to Jon Powell's page from EIA/IBIS Home page. Jon Powell has requested that anyone who knows of additional IBIS models available on Web sites to forward information to him. (Late news - Brian Johnson of Micron Technology reports that Micron models are available on http://www.micron.com/cgi-bin/model. A one-time registration is required; no password or username is needed.) NEW MODELS The new 200 MHz PentiumPro model files have been put in the Intel directory, replacing the previous models. Jon Powell reports receiving a pending Intel directory update from Michael Steer. Jon will work with Arpad on current contents. Anyone else who has updated information should work with Jon. OPENS FOR NEW ISSUES Stephen Peters - Prague Conference Report Bob Ross - Secretary Position Bob Ross - Specification Enhancements Discussion IEC EXPRESS FUNDING PROGRESS Patti Rusher reports further progress in helping fund an IBIS Express model needed for IEC progress. DARPA funding should go to US organizations. EIA itself cannot accept funding, but an auxiliary corporation "EIA Server Corporation" may be able to accept and distribute money. Patti needs to gather all of the standards funding requests including items from DIE into one comprehensive proposal. She plans to draft a proposal next week for legal review. EE TIMES ARTICLE EE Times has requested through Patti Rusher an IBIS article for the Sept. 2 issue signal-integrity special report. Bob Ross, Jon Powell and Syed Huq are working on the article. The article will be basic, but will provide more emphasis on IBIS model sources and utilities than in other overview articles. SECRETARY Bob Ross followed up on the need for the IBIS Secretary position to be filled. Stephen Peters suggested that the duties by split up. Bob stated that the primary need is still to produce the minutes. Several people already help out taking notes. Bob will handle this aspect of the Secretary position until someone else volunteers. PRAGUE CONFERENCE Stephen Peters and Will Hobbs attended a European CAD Standards Conference from July 6 - 12, 1996. They presented "Applying Standards to Increase Model Availability - Two Case Studies, IBIS and OMF". They took the model supplier point of view. HDL, AVHDL, Vital and OMF generated the most interest. They also had a opportunity to discuss Express funding with Hilary Kahn. The cost estimates remain the same. EDIF REVIEW Bob Ross reports he is working with Alan Williams of the University of Manchester concerning reporting passive R, L, C element values to simulators, per the IBIS Committee technical comment. BIRD34.1 - STORED CHARGE EFFECT Bob Ross summarized the primary assumptions that the proposed transit time format is similar to the Spice TT diode parameter and that the clamping diodes produce the major effect in the clamping regions. D.C. Sessions stated that many clamping diodes are MOS, not bipolar. He is investigating the significance of this difference. So the voltage dependent capacitor may be appropriate to support all technologies. Further discussion is expected on BIRD34.1. AR - Anyone with information on stored charge effects in MOS devices provide it to D.C. Sessions. BIRD35.1 - MULTI-STAGED OUTPUTS Bob Ross summarized the [Rising Sequence] and [Falling Sequence] tables. Jon Powell reviewed the revised syntax and suggests further simplification based on calling stages by Model name. This avoids introducing the numbered table extensions in Bob's proposal. One concern is to truly isolate those subparameters which apply for the combined model, versus those that apply to the individual stage. The "master driver" could still be used to capture all models and parameters and sequencing in one area to avoid scattering the information throughout a .ibs file. Stephen Peters suggested a composite [Rising Waveform] and [Falling Waveform] be provided. Jon stated, that if this were done, it would be for checking only since it contains less information than the detail needed by individual stages. AR - Bob Ross work with Jon Powell concerning syntax changes and produce BIRD35.2. BIRD36 - ELECTRICAL BOARD DESCRIPTION Since Stephen Peters had just returned, discussion on this was deferred. Bob Ross commented that he had talked with and agreed with Hank Herrmann on most of the points that Hank had raised. One point of disagreement regarded putting an actual (large) size limit on the number of external pins. BIRD37 - ENHANCEMENT OT THE PACKAGE MODEL SPECIFICATION Bob Ross asked whether it was ready for vote. Jon Powell suggested that votes on BIRDs be announced in the agenda since there are a number of technical issues to review. Bob wanted to check that new FORK term did not use the "/" terminator, reserved only for the "Len .... /" syntax. Hank Herrmann suggested the NC addition. However, same functionality is provided using "Len = 0 /" null element. Bob suggested that BIRD37 include the approved BIRD28.3 example and add the FORK subparameter to fully illustrate the syntax extension. AR - Stephen Peters provide an upgraded BIRD37.1 which addresses these concerns for vote at the next meeting. BIRD38 (EGG11) - ABSOLUTE MAXIMUM VOLTAGE Jon Fitzpatrick was not present, so discussion was deferred. Bob Ross felt that this is a very complex specification BIRD needing further discussion. The extensions would definitely be optional. EGG10 - PARSER ADDITIONS FOR NUMERICAL CHECKING Bob Ross acknowledged getting the statistical data from Chris Rokusek concerning IBIS parameters on models stored on vhdl.org. Chris now needs to examine this and provide proposed values for the parser tests 1-5. AR - Chris Rokusek propose tests and test limit values. Stephen Peters asked whether these tests would be for Version 3.0. Bob indicated that this has not been decided. They could also be an upgrade to ibischk2. Some comparison tests should be very easy. Others such as those that test compatibility of V/T table voltages with V/I tables could require computational work. SERIES RESISTOR Arpad Muranyi discussed further the series element ideas. It could be a controlled 3-terminal device with a set of tables, similar to transistor device characterizations. One of the major needs is for "Quick Switch" (e.g., CBT technology from Texas Instruments) devices which can connect or disconnect paths. The MOS on path may be 1 to 10 ohms, but there may be additional analog characteristics. Current electrical simulators do not include digital control logic, so Jon Powell felt the focus should be more on 2-terminal series elements with, perhaps, a 3.3 V and 5 V mode. Series elements can include diodes, resistors, EMI filters, etc. So, some form of I/V tables may still be needed. The devices could also be modeled with an off and an on state. Currently there is no IBIS support in this area. The only EDA vendor support uses their own syntax. While the Electrical Board Extensions could be used, a direct, simpler method is more appropriate. AR - Arpad Muranyi provide a proposal in order to continue this as an agenda item. SPECIFICATION PARAMETER ENHANCEMENTS Bob Ross indicated that BIRD38 dealt with Specification data similar to Vinh and Vinl and not electrical characterization data. There have been a number of requests for specification parameters, and such extensions are on the priority list for Version 3.0. Bob asked for ideas. Ahmed Omer stated that an input delta-time limit is needed for the input thresholds to assure maximum energy limits are not exceeded. AR - Ahmed Omer make a proposal for dealing with these energy limit. Bob added hystersis thresholds, CMOS style input thresholds that are a percentage of Vcc, and overshoot (high and low) limits are possible additions. On both the input and output sides, the reference points for signal integrity and timing measurements can be at the DIE or at the PAD for different applications. Also, timing references may be at the PAD, but signal integrity references may be at the DIE for standard devices, but at the PAD for ASICs. Jon Powell suggested that a committee similar to the package committee be formed off-line to collect the parameters. Bob Ross plans to initiate a proposal. NEXT MEETING: The next meeting is on Friday, August 16, 1996, 8:00 A.M. to 9:55 A.M., four weeks from now because of some conflicting commitments. BIRD37.1 is scheduled for vote. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469 bob@icx.com Modeling Engineer, Interconnectix, Inc. 10220 SW Nimbus Ave, K4, Portland, OR 97223 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Transmission-Line Products Manager, Quad Design 1385 Del Norte Rd., Camarillo, CA 93010 SECRETARY: Vacant This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@vhdl.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@vhdl.org), the IBIS Users' Group Reflector (ibis-users@vhdl.org) or both. State your request. ibis-info@vhdl.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@vhdl.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. ibis-users@vhdl.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. ibischk-bug@vhdl.org To report ibischk2 parser bugs. The Bug Report Form Resides on vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on vhdl.org for more information on previous discussions and results. You can get on via ftp anonymous, "guest" login from telnet or dial-in (415-335-0110), or send an e-mail request to the automatic archive server, archive@vhdl.org. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ============================================================================== From owner-ibis Tue Jul 23 10:50:46 1996 Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id KAA27646 for ; Tue, 23 Jul 1996 10:50:45 -0700 (PDT) Received: from relay.jf.intel.com (relay.jf.intel.com [134.134.131.6]) by ormail.intel.com (8.7.4/8.7.3) with ESMTP id KAA14798 for ; Tue, 23 Jul 1996 10:40:53 -0700 (PDT) Received: (from ccmgate@localhost) by relay.jf.intel.com (8.7.4/8.7.3) id KAA24706 for ibis@vhdl.org; Tue, 23 Jul 1996 10:40:50 -0700 (PDT) Received: by ccm.hf.intel.com (ccmgate 3.2 #7) Tue, 23 Jul 96 10:40:50 PDT Date: Tue, 23 Jul 96 10:34:00 PDT From: Arpad Muranyi Message-ID: To: ibis@vhdl.org Subject: Re: Stored Charge by Peivand Tehrani Peivand, I looked at your simulation example, and I think that you are referring to a phenomena as the "glitch" which is unrelated to the "kickback effect", commonly associated with the charge storage effects (discussed in BIRD34) of clamping diodes, ESD structures, etc. In my opinion the glitch you are observing is related to the parasitic capacitances between Drain-Source, Gate-Source, and Gate-Drain. When the gate voltage of the inverter begins to switch, there is a time period when none of the output transistors are (fully) on. The changing voltage on the gate bleeds through the parasitic capacitances to the output untill the transistor to be turned on gets turned on. Since we are talking about an inverter, this causes a glitch that goes the opposite direction of the intended edge. If you try to reproduce the same effect with a "voltage follower" circuit, you will see that the "glitch" will go in the same direction with the intended edge. Arpad Muranyi Intel Corporation ================================================================================ Author: owner-ibis@vhdl.vhdl.org at SMTPGATE Date: 7/19/96 5:50 PM Priority: Normal TO: bob@icx.com at SMTPGATE CC: ibis@vhdl.org at SMTPGATE BCC: Arpad Muranyi at FMCCM28 Subject: Stored Charge ------------------------------- Message Contents ------------------------------- Hello IBIS fans, I was reviewing the stored charge BIRD 34.1 . I have observed the same glitch effect even with ESD diodes removed. So I think this glitch is not just created by the stored charge in the diodes. This glitch can easily be observed with a simple CMOS invertor with a fast (100 psec) ramp as the input of the invertor, I think this glitch is because of the stored charge in the depletion region of upper and lower devices. I will send a simple SPICE file that I have been using to simulate this effect. The SPICE version which I am using runs into convergence problems if I remove Cd1 capacitor. This capacitor presents the die capacitor in IBIS models. After the simulation the voltage at node 2 should be probed. Best Regards, Peivand Tehrani. **************************SPICE file************************ Driver Device Transitions For Gate Transition ************************************************************* VDD 3 0 5 ************************************************************* M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6 M2 2 1 3 3 QP L=1.5E-6 W=341E-6 ************************************************************* .MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 ) .MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200) ************************************************************* VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3) ************************************************************* Cd1 2 0 4p R11 2 0 50 ************************************************************* .tran .001n 1n .END From owner-ibis Tue Jul 23 11:27:39 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id LAA28043 for ; Tue, 23 Jul 1996 11:27:39 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Tue, 23 Jul 96 11:17 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 23 Jul 96 11:17 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Tue, 23 Jul 96 11:20 PDT Message-Id: Date: Tue, 23 Jul 96 11:20 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: Stored Charge by Peivand Tehrani Peivand and IBIS Committee: I tried your sample MOS Spice model regarding stored charge. There is a small negative preshoot glitch below zero volts before the output rises to the high state. For several reasons I believe that these effects are related to the normal distribution of model elements. (Similar comment as Arpad's, which I just received.) Bob Ross Interconnectix, Inc. From owner-ibis Tue Jul 23 11:30:17 1996 Received: from relayhost.vlsi.com (tweety.vlsi.com [134.27.20.23]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id LAA28108 for ; Tue, 23 Jul 1996 11:30:16 -0700 (PDT) From: sung.oh@tempe.vlsi.com Received: from relayhost.tempe.vlsi.com (anubis.tempe.vlsi.com [134.27.128.1]) by relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id LAA24572 for ; Tue, 23 Jul 1996 11:19:39 -0700 Received: from pcdmail.tempe.vlsi.com (hole.tempe.vlsi.com [134.27.128.11]) by relayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id LAA11607 for ; Tue, 23 Jul 1996 11:19:38 -0700 Received: from sedona (sedona [134.27.133.167]) by pcdmail.tempe.vlsi.com (8.6.9/Hub-Perlotto/032095) with SMTP id LAA14745 for ; Tue, 23 Jul 1996 11:19:37 -0700 Received: by sedona id AA22245; Tue, 23 Jul 1996 11:19:36 -0700 Date: Tue, 23 Jul 1996 11:19:36 -0700 Message-Id: <9607231819.AA22245@sedona> To: ibis@vhdl.org Subject: Re: Stored Charge by Peivand Tehrani Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Md5: JidMHpIh+2bLnjk/FvhLeg== Arpad, I agree with you. I believe what Peivand saw is a well-known Miller effect, which is related to the gate to drain capacitance of the CMOS inverter. Sung >>From owner-ibis@vhdl.vhdl.org Tue Jul 23 11:03 MST 1996 >>Date: Tue, 23 Jul 96 10:34:00 PDT >>From: Arpad Muranyi >>To: ibis@vhdl.org >>Subject: Re: Stored Charge by Peivand Tehrani >> >>Peivand, >> >>I looked at your simulation example, and I think that you are referring to a >>phenomena as the "glitch" which is unrelated to the "kickback effect", commonly >>associated with the charge storage effects (discussed in BIRD34) of clamping >>diodes, ESD structures, etc. >> >>In my opinion the glitch you are observing is related to the parasitic >>capacitances between Drain-Source, Gate-Source, and Gate-Drain. When the gate >>voltage of the inverter begins to switch, there is a time period when none of >>the output transistors are (fully) on. The changing voltage on the gate bleeds >>through the parasitic capacitances to the output untill the transistor to be >>turned on gets turned on. Since we are talking about an inverter, this causes a >>glitch that goes the opposite direction of the intended edge. If you try to >>reproduce the same effect with a "voltage follower" circuit, you will see that >>the "glitch" will go in the same direction with the intended edge. >> >>Arpad Muranyi >>Intel Corporation >>============================================================================== == >> >> >> >>Author: owner-ibis@vhdl.vhdl.org at SMTPGATE >>Date: 7/19/96 5:50 PM >>Priority: Normal >>TO: bob@icx.com at SMTPGATE >>CC: ibis@vhdl.org at SMTPGATE >>BCC: Arpad Muranyi at FMCCM28 >>Subject: Stored Charge >>------------------------------- Message Contents ------------------------------- >>Hello IBIS fans, >> >> I was reviewing the stored charge BIRD 34.1 . I have observed the >>same glitch effect even with ESD diodes removed. So I think this glitch >>is not just created by the stored charge in the diodes. This glitch can >>easily be observed with a simple CMOS invertor with a fast (100 psec) >>ramp as the input of the invertor, I think this glitch is because of the >>stored charge in the depletion region of upper and lower devices. >> >> I will send a simple SPICE file that I have been using to simulate this >>effect. The SPICE version which I am using runs into convergence problems >>if I remove Cd1 capacitor. This capacitor presents the die capacitor in >>IBIS models. After the simulation the voltage at node 2 should be probed. >> >>Best Regards, >>Peivand Tehrani. >> >> >>**************************SPICE file************************ >> >> >> >>Driver Device Transitions For Gate Transition >>************************************************************* >>VDD 3 0 5 >>************************************************************* >>M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6 >>M2 2 1 3 3 QP L=1.5E-6 W=341E-6 >>************************************************************* >>.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 ) >>.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200) >>************************************************************* >>VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3) >>************************************************************* >>Cd1 2 0 4p >>R11 2 0 50 >>************************************************************* >>.tran .001n 1n >>.END >> From owner-ibis Tue Jul 23 14:02:49 1996 Received: from marceau.fm.intel.com (marceau.fm.intel.com [132.233.247.8]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id OAA29369 for ; Tue, 23 Jul 1996 14:02:47 -0700 (PDT) Received: from fmmail.fm.intel.com by marceau.fm.intel.com (8.7.4/10.0i); Tue, 23 Jul 1996 20:52:49 GMT Received: (from ccmgate@localhost) by fmmail.fm.intel.com (8.7.4/8.7.3) id NAA07640 for ibis@vhdl.org; Tue, 23 Jul 1996 13:53:16 -0700 (PDT) Received: by ccm.fm.intel.com (ccmgate 3.2 #2) Tue, 23 Jul 96 13:53:16 PDT Date: Tue, 23 Jul 96 13:38:00 PDT From: Arpad Muranyi Message-ID: To: ibis@vhdl.org Subject: Re[2]: Stored Charge by Peivand Tehrani Text item: Sung, Peivand, and IBIS fans, Here is a simulation example for what I wrote about in my previous EMAIL. I did two things to Peivand's original simulation example: 1) Added a voltage-follower circuit, which is an N-channed pullup. A 50 Ohm resistor is connected between its output and GND. Observe nodes 10 and 20 (Gate and Source). 2) Added a CAPOP parameter and a bunch of 0 values to turn of all (or most?) capacitance modeling that is given by HSPICE automatically. (I am using HSPICE here). To see the glitch with the non-inverting output, plot nodes 10 and 20. Notice that the glitch goes in the same direction as the output is switching, that is, rising edge output causes a positive glitch. (In Peivand's example the glitch goes negative while the output is going positive). However, in both cases, the glitches follow the direction of the input signal. This proves that the glitch is related the input signal through parasitic capacitances. To see that these glitches go away without parasitic capacitance, uncomment the lines starting with "+ CAPOP ... " in both .MODEL statements. The glitches should go away completely. Arpad Driver Device Transitions For Gate Transition ************************************************************* .tran .001n 3.0n .OPTIONS POST=1 VDD 3 0 DC=5.0V ************************************************************* VIN1 1 0 PULSE (5 0 1.0ns 0.01ns 0.01ns 100E-9 1E-3) M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6 M2 2 1 3 3 QP L=1.5E-6 W=341E-6 *Cd1 2 0 4p R11 2 0 50 *-----------------------------------------------------------* VIN10 10 0 PULSE (0 5 1.0ns 0.01ns 0.01ns 100E-9 1E-3) M10 3 10 20 0 QN L=1.5E-6 W=136.4E-6 R10 20 0 50 ************************************************************* .MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 ) *+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0 .MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200) *+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0 ************************************************************* ************************************************************* .END ---------------------------------------------------------------------- Arpad, I agree with you. I believe what Peivand saw is a well-known Miller effect, which is related to the gate to drain capacitance of the CMOS inverter. Sung ---------------------------------------------------------------------- >>Hello IBIS fans, >> >> I was reviewing the stored charge BIRD 34.1 . I have observed the >>same glitch effect even with ESD diodes removed. So I think this glitch >>is not just created by the stored charge in the diodes. This glitch can >>easily be observed with a simple CMOS invertor with a fast (100 psec) >>ramp as the input of the invertor, I think this glitch is because of the >>stored charge in the depletion region of upper and lower devices. >> >> I will send a simple SPICE file that I have been using to simulate this >>effect. The SPICE version which I am using runs into convergence problems >>if I remove Cd1 capacitor. This capacitor presents the die capacitor in >>IBIS models. After the simulation the voltage at node 2 should be probed. >> >>Best Regards, >>Peivand Tehrani. >> >> >>**************************SPICE file************************ >> >> >> >>Driver Device Transitions For Gate Transition >>************************************************************* >>VDD 3 0 5 >>************************************************************* >>M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6 >>M2 2 1 3 3 QP L=1.5E-6 W=341E-6 >>************************************************************* >>.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 ) >>.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200) >>************************************************************* >>VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3) >>************************************************************* >>Cd1 2 0 4p >>R11 2 0 50 >>************************************************************* >>.tran .001n 1n >>.END >> Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Content-Md5: JidMHpIh+2bLnjk/FvhLeg== Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 Subject: Re: Stored Charge by Peivand Tehrani To: ibis@vhdl.org Message-Id: <9607231819.AA22245@sedona> Date: Tue, 23 Jul 1996 11:19:36 -0700 Received: by sedona id AA22245; Tue, 23 Jul 1996 11:19:36 -0700 Received: from sedona (sedona [134.27.133.167]) by pcdmail.tempe.vlsi.com (8.6.9 /Hub-Perlotto/032095) with SMTP id LAA14745 for ; Tue, 23 Jul 199 6 11:19:37 -0700 Received: from pcdmail.tempe.vlsi.com (hole.tempe.vlsi.com [134.27.128.11]) by r elayhost.tempe.vlsi.com (8.6.9/Hub-Perlotto/101195) with ESMTP id LAA11607 for < ibis@vhdl.org>; Tue, 23 Jul 1996 11:19:38 -0700 Received: from relayhost.tempe.vlsi.com (anubis.tempe.vlsi.com [134.27.128.1]) b y relayhost.vlsi.com (8.6.12/Hub-Perlotto/050895) with ESMTP id LAA24572 for ; Tue, 23 Jul 1996 11:19:39 -0700 From: sung.oh@tempe.vlsi.com Received: from relayhost.vlsi.com (tweety.vlsi.com [134.27.20.23]) by vhdl.vhdl. org (8.7.3/8.7.3) with ESMTP id LAA28108 for ; Tue, 23 Jul 1996 1 1:30:16 -0700 (PDT) Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by ormail.intel.com ( 8.7.4/8.7.3) with ESMTP id LAA22609; Tue, 23 Jul 1996 11:24:11 -0700 (PDT) Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by relay.jf.i ntel.com (8.7.4/8.7.3) with ESMTP id LAA02587; Tue, 23 Jul 1996 11:24:11 -0700 ( PDT) Return-Path: owner-ibis@vhdl.vhdl.org From owner-ibis Wed Jul 24 08:49:18 1996 Received: from bingnet1.cc.binghamton.edu (bingnet1.cc.binghamton.edu [128.226.1.11]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id IAA24033 for ; Wed, 24 Jul 1996 08:49:16 -0700 (PDT) Received: from ee1-gw.ee.binghamton.edu (ee1-gw.ee.binghamton.edu [128.226.171.73]) by bingnet1.cc.binghamton.edu (8.7.3/8.6.9) with SMTP id LAA07999; Wed, 24 Jul 1996 11:39:03 -0400 (EDT) Received: by ee1-gw.ee.binghamton.edu (AIX 3.2/UCB 5.64/4.03) id AA19992; Wed, 24 Jul 1996 11:34:58 -0400 Date: Wed, 24 Jul 1996 11:34:58 -0400 (EDT) From: "Peivand F. Tehrani" To: Arpad Muranyi Cc: ibis@vhdl.org Subject: Re[3]: Stored Charge by Peivand Tehrani In-Reply-To: Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Arpad, Bob and Sung, This is a good observation, my point was that the "glitch" exists and may propagate along a signal line. As arpad has shown, depending on the value of the parasitic capacitors, the loading and the gate risetime, magnitude of this glitch will change. This effect is a device property and although it is small, in order to get accurate device simulation, it has to be modeled. The[xxxxing waveform]s can only provide the magnitude of this glitch under a certain loading condition. Note that in the invertor case, the glitch causes the buffer low to high transition trajectory (id(m1)-id(m2) vs. v(2)) to jump out of the device [pullup] and [pulldown] I/V characteristics. This is dynamic effect and without knowing the exact gate transition waveform (which is the case in IBIS), the values of the parasitic capacitors can not be extracted from the provided information. The glitch has a current associated with it which is provided by either one of upper and lower devices. Without knowing the value of the parasitic caps. it is hard to divide this current between the devices. Do you have any suggestions as to how I can approach this problem using the provided IBIS information? Best regards peivand From owner-ibis Thu Jul 25 12:09:01 1996 Received: from marceau.fm.intel.com (marceau.fm.intel.com [132.233.247.8]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id MAA20886 for ; Thu, 25 Jul 1996 12:08:58 -0700 (PDT) Received: from fmmail.fm.intel.com by marceau.fm.intel.com (8.7.4/10.0i); Thu, 25 Jul 1996 18:59:05 GMT Received: (from ccmgate@localhost) by fmmail.fm.intel.com (8.7.4/8.7.3) id LAA11737 for ibis@vhdl.org; Thu, 25 Jul 1996 11:59:33 -0700 (PDT) Received: by ccm.fm.intel.com (ccmgate 3.2 #2) Thu, 25 Jul 96 11:59:33 PDT Date: Thu, 25 Jul 96 11:53:00 PDT From: Arpad Muranyi Message-ID: cc: ibis@vhdl.org Subject: Re[4]: Stored Charge by Peivand Tehrani Text item: Peivand, Your observation is correct. The problem is that this is a difficult phenomena to model behaviorally (as far as I know). However, in my opinion, this effect is rather small, so I would not worry too much about it in system level simulations. If you think this an important issue and it needs to be addressed by the IBIS standard, bring it up for discussion in one of the future open forum meetings. If it turns out that many people would like to see a solution for it, we might work out a way to model it. Arpad ================================================================================ Arpad, Bob and Sung, This is a good observation, my point was that the "glitch" exists and may propagate along a signal line. As arpad has shown, depending on the value of the parasitic capacitors, the loading and the gate risetime, magnitude of this glitch will change. This effect is a device property and although it is small, in order to get accurate device simulation, it has to be modeled. The[xxxxing waveform]s can only provide the magnitude of this glitch under a certain loading condition. Note that in the invertor case, the glitch causes the buffer low to high transition trajectory (id(m1)-id(m2) vs. v(2)) to jump out of the device [pullup] and [pulldown] I/V characteristics. This is dynamic effect and without knowing the exact gate transition waveform (which is the case in IBIS), the values of the parasitic capacitors can not be extracted from the provided information. The glitch has a current associated with it which is provided by either one of upper and lower devices. Without knowing the value of the parasitic caps. it is hard to divide this current between the devices. Do you have any suggestions as to how I can approach this problem using the provided IBIS information? Best regards peivand Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Content-Type: TEXT/PLAIN; charset=US-ASCII Mime-Version: 1.0 Message-Id: In-Reply-To: Subject: Re[3]: Stored Charge by Peivand Tehrani Cc: ibis@vhdl.org To: Arpad Muranyi From: "Peivand F. Tehrani" Date: Wed, 24 Jul 1996 11:34:58 -0400 (EDT) Received: by ee1-gw.ee.binghamton.edu (AIX 3.2/UCB 5.64/4.03) id AA19992; Wed, 24 Jul 1996 11:34:58 -0400 Received: from ee1-gw.ee.binghamton.edu (ee1-gw.ee.binghamton.edu [128.226.171.7 3]) by bingnet1.cc.binghamton.edu (8.7.3/8.6.9) with SMTP id LAA07999; Wed, 24 J ul 1996 11:39:03 -0400 (EDT) Received: from bingnet1.cc.binghamton.edu (bingnet1.cc.binghamton.edu [128.226.1 .11]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id IAA24033 for ; Wed, 24 Jul 1996 08:49:16 -0700 (PDT) Received: from vhdl.vhdl.org (vhdl.vhdl.org [198.31.14.3]) by ormail.intel.com ( 8.7.4/8.7.3) with ESMTP id IAA02120; Wed, 24 Jul 1996 08:50:31 -0700 (PDT) Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by relay.jf.i ntel.com (8.7.4/8.7.3) with ESMTP id IAA10982; Wed, 24 Jul 1996 08:50:30 -0700 ( PDT) Return-Path: owner-ibis@vhdl.vhdl.org From owner-ibis Thu Jul 25 15:56:15 1996 Received: from netcomsv.netcom.com (uucp3.netcom.com [163.179.3.3]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id PAA22725 for ; Thu, 25 Jul 1996 15:56:09 -0700 (PDT) Received: from contec.UUCP by netcomsv.netcom.com with UUCP (8.6.12/SMI-4.1) id PAA09070; Thu, 25 Jul 1996 15:35:30 -0700 Received: from contec13.contec.COM by contec.COM (4.1/SMI-4.1) id AA07334; Thu, 25 Jul 96 15:38:05 PDT Received: by contec13.contec.COM (5.0/SMI-SVR4) id AA28801; Thu, 25 Jul 1996 15:35:06 +0800 Date: Thu, 25 Jul 1996 15:35:06 +0800 From: dileep@contec.contec.COM (Dileep Divekar) Message-Id: <9607252235.AA28801@contec13.contec.COM> To: ibis@vhdl.org Subject: Modeling Principles for Developers and Users Cc: dileep@contec.contec.COM X-Sun-Charset: US-ASCII "Everything should be made as simple as possible, but not any simpler." - Albert Einstein "A model of a physical device is a mahtematical entity with precise laws relating its variables. The model is always distinct from the physical device, though its behavior ordinarily approximates that of the physical device represented. Thus a model is never strictly equivalent to the device it represents." - John Linvill From owner-ibis Wed Jul 31 15:30:30 1996 Received: from icx.com (root@fw.icx.com [205.238.6.33]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id PAA26088 for ; Wed, 31 Jul 1996 15:30:24 -0700 (PDT) Received: by icx.com (/\oo/\ Smail3.1.29.1 #29.2) id ; Wed, 31 Jul 96 15:20 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jul 96 15:20 PDT Received: by icx.com (/\==/\ Smail3.1.28.1 #28.14) id ; Wed, 31 Jul 96 15:22 PDT Message-Id: Date: Wed, 31 Jul 96 15:22 PDT From: bob@icx.com ( Bob Ross) To: ibis@vhdl.org Subject: EGG12 SPECIFICATION ADDITONS To IBISians (Since I will be on vacation through August 13, I will not be responding to any comments on this.) Here is a brief note to start discussion on Specification additions to IBIS for Version 3.0 With respect to input thresholds, we currently support the model subparameters: Vinl Vinh They support fixed values of thresholds for all columns. However, some technologies have different thresholds for the min and max columns. So I propose adding the optional input thresholds Vinl_min Vinl_max Vinh_min Vinh_max for the min and max columns. This is similar to the V_fixture_min and V_fixture_max extensions for [Rising Waveform] and [Falling Waveform] keywords. These additions solve the problem of thresholds being a percentage of the voltage range (as in CMOS technology) and as an offset from a voltage rails (as in PECL). In all cases, voltage values need to be calculated. This avoids new notation for percentage threshold and offset threshold. This does not deal with hystersis. Other parameters for discussion include hard coded overshoot and undershoot values and selections of measurement locations (die, pin). Bob Ross Interconnectix, Inc.